Analog demultiplexing

Abstract

The analog demultiplexer (FIG. 6) includes an input amplifier (A1), and output amplifiers (AMP1-AMPN). The output and inverting (−) input of amplifiers (AMP1-AMPN) are connected by a respective capacitor (C1-CN). Switches (S1a, S1b, etc.) connect the output of amplifier (A1) to the inverting input of one of (AMP1-AMPN). Switches (S2a, S2b, etc.) connect the output of one of (AMP1-AMPN) to the non-inverting input of the amplifier A1. Switches (S2a, S2b, etc.) and (S1a, S1b, etc.) open and close together in pairs. With feedback from the output of (AMP1-AMPN) through (A1), the gain and any offset of (AMP1-AMPN) is divided down by the gain of (A1). Amplifier (A1) has capacitors (CS1 and CS2) connected to its inputs. Switch (S50) connects the inverting input of amplifier (A1) to its output, and switch (S40) connects the non-inverting input of (A1) to a voltage reference (VREF) matching (VREF) applied to (AMP2). Switches (S30) and (S35) connect (CS1) and (CS2) to the demultiplexer input (2). In operation, switches (S40, S50, S30 and S35) are initially closed, while switches (S2a, S2b, etc.) are open to charge both capacitors (CS1) and (CS2) and the inputs and output of (A1) to (VREF). Switch (S50) provides feedback to divide down gain errors and offset of (A1). Switches (S30, S35, S40 and S50) are then open, while one of switches (S2a, S2b, etc.) is closed with one switch (S1a, S1b, etc) to drive one of the output voltages (VOUT1-VOUTN). With inputs and outputs of (A1) and the connected (AMP1-AMPN) initially be at (VREF), very little settling time is needed.

Description

BACKGROUND

1. Technical Field

The present invention relates to analog demultiplexer for distributing signals from a single input line to one of multiple output lines. In particular, the present invention relates to an analog demultiplexer for distributing a video input signal to one of several video display column drivers, with the analog demultiplexer having minimal offset due to its amplifiers, and having a minimal amplifier settling time.

2. Related Art

FIG. 1 shows one conventional configuration for an analog demultiplexer. The analog demultiplexer allows a multiplexed analog input voltage V_IN received at input 2 to be demultiplexed using a switch S₁ to provide an output voltage V_OUT1-V_OUTN at a respective one of outputs 4₁- 4_N. The logic control driving switch S₁ toggles switch S₁ to direct an input voltage V_IN to one specific output buffer AMP₁-AMP_N. In this way, an input voltage provided at input V_IN can be demultiplexed to one of numerous output buffers AMP₁-AMP_N.

Assuming the input voltage V_IN at input 2 is to be sampled as output voltage V_OUT1 at output 4₁, switch S₁ closes to connect amplifier A₁ to the capacitor C₁ and the input of amplifier AMP₁. The voltage at V_IN is sampled onto capacitor C₁ and the buffered voltage appears on V_OUT1. Then the switch S₁ is opened. The hold capacitor C₁ retains the sampled voltage, and thus, the voltage at V_OUT1 remains constant for a period of time. In a similar manner, the input voltage V_IN at input 2 can be connected using switch S₁ to sample and hold the input voltage V_IN using another one of the capacitors C₂-C_N and its corresponding amplifier AMP₂-AMP_N.

The undesirable effects of the analog demultiplexer of the configuration of FIG. 1 are as follows:

• • (1) The amplifiers A₁ and AMP₁-AMP_N all create a voltage offset from the signal at V_IN;
  • (2) The amplifiers A₁ and AMP₁-AMP_N are all shown with a gain of +1, but gain errors occur;
  • (3) A pedestal voltage offset error occurs when the switch S₁ opens; and
  • (4) The output amplifiers AMP₁-AMP_N are NOT identical—Or the same input voltage at V_IN generates a different output at each output VOUT₁-VOUT_N.

To improve the performance of analog demultiplexers, several approaches have been used. These approaches are described to follow.

1st Improvement

A first improvement over the analog demultiplexer of FIG. 1 is shown in FIG. 2. In operation, assuming the voltage V_IN at input 2 is to be sampled as an output voltage V_OUT1 at output 4₁, then switch S₁ closes and connects the output of amplifier A₁ to capacitor C₁ and the non-inverting input of amplifier AMP₁. At the same instant a second switch S₂ closes, connecting the output of amplifier AMP₁ to the inverting input of amplifier A₁. Note components carried over from FIG. 1 to FIG. 2 are similarly labeled, even though they are connected in a different manner, as will be components carried over into subsequent figures. The equivalent circuit for this switch state for FIG. 2 is shown in FIG. 3.

With feedback from output amplifier AMP₁ to A₁, the equivalent circuit is assumed to have a unity gain configuration. Assuming that the circuit is stable and the gain of both amplifier A₁ and amplifier AMP₁ are very large, any offset of AMP₁ is divided down by the gain of A₁. The voltage V_IN plus the offset of amplifier A₁ is sampled onto the hold capacitor C₁. So, V_OUT1=V_IN+Vos(offset of A₁)

Advantages of the configuration of FIG. 2 are as follows:

• • (1) The voltage offset of AMP₁ is divided down by the gain of A₁; and
  • (2) The gain error or AMP₁ is divided down by the gain of A₁.

Undesirable effects of the configuration of FIG. 2 are as follows:

• • (1) The voltage offset of amplifier A₁;
  • (2) A voltage offset caused by charge injection of switch S₂ when it opens;
  • (3) The gain error of amplifier A₁; and
  • (4) A long settling time after switch S₂ closes.

Before switch S₂ of FIG. 2 closes, amplifier A₁ would be in an open loop configuration. Thus, its output will be in an undetermined voltage state. Amplifier A₁ is “saturated”. Amplifier A₁ returns into its “active” region by glitching and ringing its output before it settles. (Settling time depends on the Bandwidth and Phase Margin of the cascaded amplifiers). When the output of amplifier A₁ rings, so does V_OUT1, an undesirable effect.

2^nd Improvement

A second improvement over the analog demultiplexer of FIG. 1 is shown in FIG. 4. In the circuit of FIG. 4, a hold capacitor C₁, C₂, etc. is placed between the inverting input and output of each of the output amplifiers AMP₁, AMP₂, etc. Switches S₁ and S₂ operate as a pair to connect one of the output amplifiers AMP₁, AMP₂, . . . between the output of amplifier A₁ and its non-inverting input. A switch S₃ connects the output of A₁ to a reference voltage V_REF when the switches S₁ and S₂ are not connected. The non-inverting input of the output amplifiers AMP₁, AMP₂, . . . are likewise connected to the reference V_REF.

In operation it is first assumed that V_IN is to be sampled to V_OUT1. Switch S₁ then closes and connects the output of amplifier A₁ to capacitor C₁ and the inverting input of amplifier AMP₁. At the same instant, switch S₂ closes, connecting the output of amplifier AMP₁ to the non-inverting input of amplifier A₁. Switches S₁ and S₃ are non-overlapping, or are not connected at the same time. The equivalent circuit of such a connection is shown in FIG. 5.

With feedback, the circuit is in a unity gain configuration. If the gain of amplifier A₁ and AMP₁ are large, then V_OUT1˜V_IN+V_os1(offset of amplifier A₁).

With amplifier AMP₁ in a feedback path, its inverting input (which is also the output of amplifier A₁) is approximately equal to V_REF. For this unity-gain configuration to settle fast, both sides of switch S₁ have to be approximately V_REF before switch S₁ closes.

So, the output of the amplifier A₁ should be approximately at V_REF before switch S₁ closes. This is done by clamping the output of A₁ to V_REF by turning on switch S₃ (note: switch S₁ and S₃ are non-overlapping). This ensures that amplifier A₁ stays in the “active” region resulting in a faster settling time.

Advantages of the configuration of FIG. 4 are as follows:

• • (1) The voltage offset of AMP₁ is divided down by the gain of A₁, and is negligible.
  • (2) The settling time is reduced (Voltage at both sides of switch S₁ are approximately the same and amplifier A₁ is in its active region when switch S₁ closes).
  • (3) The gain error of AMP₁ is divided down by the gain of A₁.

Undesirable effects of the configuration of FIG. 4 are as follows:

• • (1) The voltage offset of amplifier A₁ remains;
  • (2) The gain error of amplifier A₁ remains; and
  • (3) Charge injection of switch S₁ to the output capacitor causing an offset error on the output.

SUMMARY

In accordance with an embodiment of the present invention, an analog demultiplexer is provided with the voltage offset and gain error of amplifiers AMP₁-AMP_N and A₁ divided down to a minimal value. Further, the analog demultiplexer has a minimal settling time, and charge injection from switch S₁ to the output generates a minimal offset error.

The analog demultiplexer in accordance with an embodiment of the present invention (referring to FIG. 6) includes an input amplifier A₁, and a plurality of output amplifiers AMP₁-AMP_N, similar to FIG. 2. The output and inverting (−) input of amplifiers AMP₁-AMP_N are connected by a respective capacitor C₁-C_N, as in FIG. 2. Also, similar to FIG. 2, a switch S₁ (in the case of FIG. 6 multiple switches S_1a, S_1b, etc.) serve to connect the output of amplifier A₁ to the inverting input of a respective one of amplifiers AMP₁-AMP_N. Similar to FIG. 2, a switch S₂ (in the case of FIG. 6 multiple switches S_2a, S_2b, etc.) serve to connect the output of one of amplifiers AMP₁-AMP_N to the non-inverting input of the amplifier A₁. As in FIG. 2, switches S_2a, S_2b, etc. can function to switch together with respective ones of switches S_1a, S_1b, etc. As in FIG. 2, with feedback from the output of amplifiers AMP₁-AMP_N through A₁, the gain as well as the offset of any of AMP₁-AMP_N is divided down by the gain of A₁.

Unlike the circuit of FIG. 2, in an embodiment, the amplifier A₁ has a capacitor C_S1 connected to its non-inverting input and another capacitor C_S2 connected to its inverting input. A switch S₅₀ connects the inverting input of amplifier A₁ to its output, and a switch S₄₀ connects the non-inverting input of amplifier A₁ to a voltage reference V_REF matching a voltage reference V_REF applied to the non-inverting input of amplifier AMP₂. A switch S₃₀ connects the capacitor C_S1 to receive the demultiplexer input 2, while a switch S₃₅ connects the capacitor C_S2 to the demultiplexer input 2. In operation, switches S₄₀, S₅₀, S₃₀ and S₃₅ are initially closed, while switches S_2a, S_2b, etc. are open to charge up both capacitors C_S1 and C_S2 to V_REF to assure both inputs of amplifier A₁ and its output are at V_REF. Switch S₅₀ provides feedback to assure gain errors and offset of A₁ are divided down. Switches S₃₀, S₃₅, S₄₀ and S₅₀ are then open, while one of switches S_2a, S_2b, etc. is closed in correspondence with a switch S_1a, S_1b, etc. Since the inputs and output of both A₁ and the corresponding amplifier AMP₁-AMP_N will initially be at V_REF, very little settling time will be required to stabilize the respective output voltage V_OUT1-V_OUTN.

To improve switching speed in one embodiment, the switches S_1a, S_1b, etc. are preferably formed from as a CMOS switch made from a combined PMOS and NMOS transmission gate. The NMOS transistor enables the circuit to switch fast, while the PMOS transistor being on after the circuit settles removes voltage offset typically existing with only an NMOS transistor. Using a CMOS switch, in one embodiment a dummy switch can be added in series with the CMOS switch which is half the size to cancel any charge offset produced by the active switch. In another embodiment, the gate size of transistors for switches S_1a, S_1b etc. are reduced to limit any offset due to these switches.

BRIEF DESCRIPTION OF THE DRAWINGS

Further details of the present invention are explained with the help of the attached drawings in which:

FIG. 1 shows one conventional configuration for an analog demultiplexer;

FIG. 2 shows a first improvement over the analog demultiplexer of FIG. 1;

FIG. 3 shows an equivalent circuit for the switch state of FIG. 2;

FIG. 4 shows a second improvement over the analog demultiplexer of FIG. 1;

FIG. 5 shows an equivalent circuit for the switch state of FIG. 4;

FIG. 6 shows an analog demultiplexer in accordance with the present invention;

FIG. 7 shows the analog demultiplexer of FIG. 7 with connections only between the input amplifier A₁ and output amplifier AMP₁.

FIG. 8 shows an equivalent circuit for the switch state of FIG. 7.

FIG. 9 shows the equivalent circuit for FIG. 7 with switches S₄₀ and S₅₀ changing to an open state;

FIG. 10 shows the equivalent circuit for FIG. 7 with the S₄₀ and S₅₀ of FIG. 9 remaining open and additionally switches S₃₀ and S₃₅ opening;

FIG. 11 shows an equivalent circuit for FIG. 7 with the switches S₃₀, S₄₀, S₅₀ remaining open, but switches S_2a and S_1a closing;

FIG. 12 shows an equivalent circuit with switches S₃₀, S₄₀, S₅₀ remaining open, and switch S_2a remaining closed, but S_1a reopening;

FIG. 13 shows transistors used to create a switch S_1a, and voltages applied to reduce any offset due to charge injection; and

FIG. 14 shows components for an embodiment of the input amplifier A₁.

DETAILED DESCRIPTION

An approach for an analog demultiplexer in accordance with the present invention is shown in FIG. 6. Using this circuit and switching S_1a, S_1b . . . etc. and S_2a, S_2b . . . etc., control logic can guide V_IN to be sampled and held on a specific one of the output buffers AMP₁-AMP_N. Note that FIG. 6 shows use of multiple switches S_1a, S_1b . . . etc. and S_2a, S_2b . . . etc., as an alternative, a single switch could be used for all of switches S_1a, S_1b . . . etc. or S_2a, S_2b . . . etc.. However, use of multiple switches permits the input amplifier A₁ to be connected to more than one of the output amplifiers AMP₁-AMP_N at one time. Further note that although switches such as S_1a and S_2a typically open and close together simultaneously in prior art designs, in the present invention the switches may or may not close simultaneously.

For a description of operation, to simplify the system of FIG. 6, FIG. 7 is included showing only two amplifiers, assuming V_IN is to be sampled to an output amplifier AMP₁. Further, it is initially assumed that the gain of amplifier A₁=A₁ and the gain of amplifier AMP₁=A₂. The connection of switches in FIG. 7 enable the value V_REF to be maintained at the inputs and output of amplifiers A₁ and AMP₁-AMP_N prior to connection of the amplifier A₁ to one of amplifiers AMP₁-AMP_N is described to follow with equivalent circuits shown for each stage.

1^st Stage

First, switches S₄₀, S₅₀, S₃₀ and S₃₅ are closed, making the circuit portion shown in FIG. 7 appear as shown in the equivalent circuit of FIG. 8. Amplifier A₁ is in a unity-gain configuration. Amplifier AMP₁ is in the “hold” state, keeping the previously set V_OUT1 constant. Thus, the following applies. $\begin{array}{c}\mathrm{Vx}=\mathrm{A1}\left(V_{+}+V_{\mathrm{OS1}}-V_{-}\right)\\ =\mathrm{A1}\left(V_{\mathrm{REF}}+V_{\mathrm{OS1}}-\mathrm{Vx}\right)\\ \mathrm{Vx}\left(1+\mathrm{A1}\right)=\mathrm{A1}\left(V_{\mathrm{REF}}+V_{\mathrm{OS1}}\right)\\ \mathrm{Vx}=\left[\mathrm{A1}/\left(1+\mathrm{A1}\right)\right]\left(\mathrm{Vref}+V_{\mathrm{OS1}}\right)\\ \mathrm{Voltage}\mathrm{across}\mathrm{capacitor}{C}_{\mathrm{S1}}=V_{\mathrm{CS1}}\\ =V_{\mathrm{IN}}-V_{\mathrm{REF}}\\ \mathrm{Voltage}\mathrm{across}\mathrm{capacitor}{C}_{\mathrm{S2}}=V_{\mathrm{CS2}}\\ =V_{\mathrm{IN}}-V_X\\ =V_{\mathrm{IN}}-\left[\mathrm{A1}/\left(1+\mathrm{A1}\right)\right]\left(V_{\mathrm{REF}}+V_{\mathrm{OS1}}\right).\end{array}$ 2^nd Stage

Next, switches S₄₀ and S₅₀ are opened creating a circuit as shown in FIG. 9. When switches S₄₀ and S₅₀ are opened, there is charge injected into capacitors C_S1 and C_S2. The offset would be common mode if S₄₀/C_S1˜S₅₀/C_S2. Assuming the size of switches S₄₀=S₅₀ and C_S1=C_S2, the offset to both capacitors caused by charge injection would be the same.

3^rd Stage

Next, in addition to the switches open in FIG. 9, switches S₃₀ and S₃₅ are opened creating a circuit as shown in FIG. 10. As a further option in this state, switch S_1x can be closed, connecting V_X to V_REF, so V_X is clamped to V_REF. Switch S_1x is then opened before stage 4.

4^th Stage

Next, switches S_1a, S_2a and S₃₅ are closed creating a circuit as shown in FIG. 11. As configured in FIG. 11, the equations of Appendix I of this application apply.

5^th Stage

Next, switch S_1a is reopened as shown in FIG. 12, as the amplifier AMP₁ has sampled and will hold the value V_IN at the output V_OUT1.

6^th Stage

Next, or in conjunction with switch S_1a, switch S_2a is reopened, to prepare for a subsequent sampling since V_IN has been sampled and held by output amplifier AMP₁. The control logic can now start to sample V_IN to a different amplifier (for example AMP₂). With sampling to AMP₂, all the stages explained herein are then performed again, but with AMP₂ replacing AMP₁. After V_IN is sampled to AMP₂, the control logic samples V_IN to another amplifier and so on. To overcome voltage droop, the output amplifiers AMP₁-AMP_N are refreshed repetitively by a subsequent sampling of V_IN.

The advantages of the configuration in accordance with the present invention are as follows:

• • (1) The offset for both amplifier A₁ and AMP₁ are reduced by the gain of A₁;
  • (2) The circuit settles fast because both sides of switch S_1a are almost at the same potential before switch S_1a closes; and
  • (3) CMRR and gain error for both amplifiers are corrected.

To improve the charge injection in switch S_1a, the following additional steps can be performed:

• • (1) Use a small switch; and
  • (2) Use charge injection cancellation techniques like:
    • in CMOS, use PMOS and NMOS transmission gates; and
    • use a dummy switch.

Use of small switch, simply implies use of one or more transistors making up the switch with a small gate size. The smaller gate size reduces charge buildup, and thus charge injection when the switch opens or closes. Typically, a high voltage transmission gate is large in dimension to withstand the higher voltage applied on it. Due to the large gate size, a large charge will be lying underneath the gate when it is in its “on” state. When the switch opens, the charge will inject into the hold capacitor creating an offset seen on the output amplifier. The voltage driving the transmission gate switches will be between a high voltage and ground. The large voltage swing on the transmission gate feeds through to the hold capacitor through the overlap capacitance of the large switch, providing another source offset.

Use of CMOS designs enables reduction in charge injection since it uses PMOS transistors causing less charge buildup. The CMOS design still includes an NMOS transistor to which turns on initially much faster than the PMOS transistor. In CMOS high voltage designs, charge injection will still produce an offset in the hold capacitors of the output amplifiers. The offset is caused by the charge under the gate injecting into the hold capacitor when the switch opens. The amount of offset is determined by: (1) the control voltage swing of the switch; and (2) the size of the switch.

A low voltage CMOS switch 10 used for switch S_1a includes PMOS and NMOS transistors 11 and 12 as shown in FIG. 13. The source-drain path of the NMOS transistor 11 and PMOS transistor 12 are connected in parallel between the output of amplifier A₁ and an input of amplifier AMP₁. The gates of transistors 11 and 12 receive complementary control signals ø and øbar.

To avoid offset, particular control voltages as well as use of a dummy switch may be employed as further illustrated in FIG. 13. In the approach of FIG. 13, two supply voltages are used for amplifier A₁. (Vdd=High voltage; V1d=low voltage). The output of amplifier A₁ is prevented from going above V1d (output of amplifier A1 can swing between Vss1 and V1d; Note: Vss1 and Vss could be tied together). The dummy switch 15 has transmission gates half the size of the transmission gates of transistors 11 and 12 forming the low voltage switch 10. The transmission gates of the dummy switch 10 are driven by a signal ø and øbar, similar to switch 10. Signals ø and øbar swing between voltages of V1d and Vss1. The output of amplifier A₁ is prevented from going above V1d so that a low voltage switch 10 and dummy switch 15 can be used for switch S_1a.

By using a low voltage switch (small gate area—small charge under the gate), the offsets caused by charge injection and clock feed through can be further minimized. The dummy switch 15 that is half the size of switch 10 is used to cancel the charge produced by switch 10.

Another improvement is having the value of V_REF between V1d and Vss. When the circuit settles in the unity gain configuration, the output of amplifier A₁ would be at V_REF. The chosen V_REF voltage is dependent on the size of the PMOS and NMOS transistors in switch S_1a. If the PMOS and NMOS transistors in switch S_1a are the same size, the charge in both the transistors (holes recombining with the electrons) would cancel each other out if: V_REF=(V1d+Vss)/2.   (1)

An example of a circuit implementation of amplifier A₁ is shown in FIG. 14. Amplifier A₁ includes two PMOS transistors 21 and 22 connected in a differential fashion. Transistor 21 has a gate forming the inverting (−) input of amplifier A₁, while the gate of transistor 22 forms the non-inverting (+) input of amplifier A₁. The sources of transistors 21 and 22 are fed from a current sink 20 connected to Vdd. Drains of transistors 21 and 22 are connected through respective NMOS transistors 24 and 25 to Vss. Note Vss and Vss1 are the same voltage. Transistors 24 and 25 are then connected in a current mirror configuration with respective NMOS transistors 27 and 28. Transistor 27 has a source-drain path connected in series with transistor 30 between V1d and Vss1, while transistor 28 has a source-drain path connected in series with transistor 31 between V1d and Vss1. The connection between the source-drain paths of transistors 28 and 31 form the output of the amplifier A₁.

Although the present invention has been described above with particularity, this was merely to teach one of ordinary skill in the art how to make and use the invention. Many additional modifications will fall within the scope of the invention, as that scope is defined by the claims which follow. $\begin{array}{cc}\begin{array}{c}{V}_X=\mathrm{A1}\left(V_{+}+V_{\mathrm{cs1}}-V_{-}\right)\mathrm{Where}\\ V_{+}=V_{\mathrm{OUT1}}-V_{\mathrm{cs1}}\\ =V_{\mathrm{OUT}}-V_{\mathrm{IN}}+V_{\mathrm{REF}}\\ V_{-}=V_{\mathrm{IN}}-V_{\mathrm{cs2}}\\ =V_{\mathrm{IN}}-V_{\mathrm{IN}}+\frac{\mathrm{A1}}{1+\mathrm{A1}}\left(V_{\mathrm{REF}}+V_{\mathrm{os1}}\right)\\ \Rightarrow V_x=\mathrm{A1}(V_{\mathrm{OUT1}}-V_{\mathrm{IN}}+V_{\mathrm{REF}}+V_{\mathrm{os1}}-\\ \frac{\mathrm{A1}}{1+\mathrm{A1}}\left(V_{\mathrm{REF}}+V_{\mathrm{os1}}\right))\\ ={\mathrm{A1V}}_{\mathrm{OUT1}}-{\mathrm{A1V}}_{\mathrm{IN}}+\frac{\mathrm{A1}}{1+\mathrm{A1}}{V}_{\mathrm{REF}}+\\ \frac{\mathrm{A1}}{1+\mathrm{A1}}{V}_{\mathrm{os1}}\\ V_{\mathrm{OUT1}}=\mathrm{A2}\left(V_{\mathrm{REF}}+V_{\mathrm{os2}}-V_X\right)\\ =\mathrm{A2}(V_{\mathrm{REF}}+V_{\mathrm{os2}}-{\mathrm{A1V}}_{\mathrm{OUT1}}+{\mathrm{A1V}}_{\mathrm{IN}}-\\ \frac{\mathrm{A1}}{1+\mathrm{A1}}{V}_{\mathrm{REF}}-\frac{\mathrm{A1}}{1+\mathrm{A1}}{V}_{\mathrm{os1}})\\ V_{\mathrm{OUT1}}\left(1+\mathrm{A1A2}\right)={\mathrm{A2V}}_{\mathrm{REF}}+{\mathrm{A2V}}_{\mathrm{os2}}+{\mathrm{A1A2V}}_{\mathrm{IN}}-\\ \frac{\mathrm{A1}}{1+\mathrm{A1}}{V}_{\mathrm{REF}}-\frac{\mathrm{A1A2}}{1+\mathrm{A1}}\\ V_{\mathrm{OUT1}}\frac{\mathrm{A2}}{1+\mathrm{A1A2}}{V}_{\mathrm{REF}}+\\ \frac{\mathrm{A2}}{1+\mathrm{A1A2}}{V}_{\mathrm{os2}}+\frac{\mathrm{A1A2}}{1+\mathrm{A1A2}}{V}_{\mathrm{IN}}\\ \frac{-\mathrm{A1A2}}{\left(1+\mathrm{A1A2}\right)\left(1+\mathrm{A1}\right)}{V}_{\mathrm{REF}}\\ \frac{-\mathrm{A1A2}}{\left(1+\mathrm{A1A2}\right)\left(1+\mathrm{A1}\right)}{V}_{\mathrm{os1}}\end{array}& \mathrm{Appendix}1\end{array}$ Assuming $\begin{array}{c}1+\mathrm{A1A2}\approx \mathrm{A1A2}\\ 1+\mathrm{A1}\approx \mathrm{A1}\end{array}\hspace{1em}\}$ True if gain of A1 and A2 are large $\Rightarrow V_{\mathrm{OUT1}}=\frac{V_{\mathrm{REF}}}{\mathrm{A1}}+\frac{V_{\mathrm{os2}}}{\mathrm{A1}}+V_{\mathrm{IN}}-\frac{V_{\mathrm{REF}}}{\mathrm{A1}}+\frac{V_{\mathrm{os1}}}{\mathrm{A1}}\Rightarrow V_{\mathrm{OUT1}}=V_{\mathrm{IN}}-\frac{V_{\mathrm{os1}}}{\mathrm{A1}}+\frac{V_{\mathrm{os2}}}{\mathrm{A1}}$

Claims

1. A method for demultiplexing an input signal (VIN) using an input amplifier (A1) and a plurality of output amplifiers (AMP1-AMPN), the input amplifier (A1) having first and second inputs and an output, the output amplifiers (AMP1-AMPN) each having first and second inputs and an output, the method comprising the steps of: providing a first input capacitor (CS1) having a first terminal, and having a second terminal connected to the first input of the input amplifier (A1); providing a second input capacitor (CS2) having a first terminal, and having a second terminal connected to the second input of the input amplifier (A1); accepting the input signal (VIN) at an input terminal (2); selectively connecting the input terminal (2) to the first terminal of the first input capacitor (CS1); selectively connecting the input terminal (2) to the first terminal of the second input capacitor (CS2); selectively connecting the output of the input amplifier (A1) to the first input of one of the output amplifiers (AMP1-AMPN); and selectively connecting the output of one of the output amplifiers (AMP1-AMPN) to the first terminal of the first input capacitor (CS1).

2. The method of claim 1, further comprising providing feedback capacitors (C1-CN), each feedback capacitor connecting the first input of one of the output amplifiers (AMP1-AMPN) to its output.

3. The method of claim 1, wherein the selective connecting is performed such that when the first input of one of the output amplifiers (AMP1-AMPN) is initially connected to the output of the input amplifier (A1), the output of said one of the output amplifiers (AMP1-AMPN) is simultaneously connected the first terminal of the first input capacitor (CS1).

4. The method of claim 1, further comprising selectively connecting the second input of the input amplifier (A1) to the output of the input amplifier (A1).

5. The method of claim 4, further comprising selectively connecting the first input of the input amplifier (A1) to a reference voltage (VREF).

6. The method of claim 5, wherein the selective connecting is performed such that at the same time: the first input of the input amplifier (A1) is connected to the reference voltage (VREF), the second input of the input amplifier (A1) is connected to the output of the input amplifier (A1), the input terminal (2) is connected to the first terminal of the first input capacitor (CS1), and the input terminal (2) is connected to the first terminal of the second input capacitor (CS2).

7. The method of claim 6, wherein the selective connecting is performed such that the output of none of the output amplifiers (AMP1-AMPN) is connected to the first terminal of the first input capacitor (CS1) when: the first input of the input amplifier (A1) is connected to the output of the input amplifier (A1), the first input of the input amplifier (A1) is connected to the reference voltage (VREF), the input terminal (2) is connected to the first terminal of the first input capacitor (CS1), and the input terminal (2) is connected to the first terminal of the second input capacitor (CS2).

8. The method of claim 1, further comprising providing a reference voltage (VREF) to the second input of each of the output amplifiers (AMP1-AMPN).

9. The method of claim 8, further comprising connecting the output of the input amplifier (A1) to the reference voltage (VREF) when the output of the input amplifier (A1) is not connected to the first input of any of the output amplifiers (AMP1-AMPN).

10. A method for demultiplexing an input signal (VIN) using an input amplifier (A1) and a plurality of output amplifiers (AMP1-AMPN), the input amplifier (A1) having an inverting (−) input, a non-inverting (+) input and an output, the output amplifiers (AMP1-AMPN) each having an inverting (−) input, a non-inverting (+) input and an output, the method comprising the steps of: providing a first input capacitor (CS1) having a first terminal, and having a second terminal connected to the non-inverting (+) input of the input amplifier (A1); providing a second input capacitor (CS2) having a first terminal, and having a second terminal connected to the inverting (−) input of the input amplifier (A1); accepting the input signal (VIN) at an input terminal (2); selectively connecting the input terminal (2) to the first terminal of the first input capacitor (CS1); selectively connecting the input terminal (2) to the first terminal of the second input capacitor (CS2); selectively connecting the output of the input amplifier (A1) to the inverting (−) input of one of the output amplifiers (AMP1-AMPN); and selectively connecting the inverting (−) input of the input amplifier (A1) to the output of the input amplifier (A1).

11. The method of claim 10, further comprising providing feedback capacitors (C1-CN), each feedback capacitor connecting the inverting (−) input of one of the output amplifiers (AMP1-AMPN) to its output.

12. The method of claim 10, further comprising selectively connecting the output of one of the output amplifiers (AMP1-AMPN) to the first terminal of the first input capacitor (CS1).

13. The method of claim 12, wherein the selective connecting is performed such that when the inverting (−) input of one of the output amplifiers (AMP1-AMPN) is initially connected to the output of the input amplifier (A1), the output of said one of the output amplifiers (AMP1-AMPN) is simultaneously connected the first terminal of the first input capacitor (CS1).

14. The method of claim 10, further comprising selectively connecting the non-inverting (+) input of the input amplifier (A1) to a reference voltage (VREF).

15. The method of claim 14, wherein the selective connecting is performed such that at the same time: the non-inverting (+) input of the input amplifier (A1) is connected to the reference voltage (VREF), the inverting (−) input of the input amplifier (A1) is connected to the output of the input amplifier (A1), the input terminal (2) is connected to the first terminal of the first input capacitor (CS1), and the input terminal (2) is connected to the first terminal of the second input capacitor (CS2).

16. The method of claim 15, wherein the selective connecting is performed such that no output of the output amplifiers (AMP1-AMPN) is connected to the first terminal of the first input capacitor (CS1) when the non-inverting (+) input of the input amplifier (A1) is connected to the reference voltage (VREF), the inverting (−) input of the input amplifier (A1) is connected to the output of the input amplifier (A1), the input terminal (2) is connected to the first terminal of the first input capacitor (CS1), and the input terminal (2) is connected to the first terminal of the second input capacitor (CS2).

17. The method of claim 10, further comprising providing a reference voltage (VREF) to the non-inverting input (+) of each of the output amplifiers (AMP1-AMPN).

18. The method of claim 10, further comprising connecting the output of the input amplifier (A1) to the reference voltage (VREF) when the output of the input amplifier (A1) is not connected to the inverting input (−) of any of the output amplifiers (AMP1-AMPN).

19. A method of demultiplexing an input signal (VIN) using an input amplifier (A1) and a plurality of output amplifiers (AMP1-AMPN), the method comprising the steps of: (a) connecting a reference voltage VREF to a first input and an output of the input amplifier (A1); (b) storing the reference voltage VREF value so that it remains for a period of time on the first input of the input amplifier (A1) after the voltage reference VREF is no longer connected to the first input and output of the input amplifier (A1); (c) disconnecting the voltage reference VREF from the first input and output of the input amplifier (A1); (e) providing the input signal (VIN) to the first input of the input amplifier (A1); (f) connecting the output of the input amplifier (A1) to an input of a given one of the output amplifiers (A1-AN); and (g) connecting the output of the given output amplifier to the second input of the input amplifier (A1).