Claims
- 1. An analog multiplier for receiving a primary input analog signal having a primary voltage of V.sub.1 and a secondary input analog signal having a secondary voltage of V.sub.2 to produce a primary output current and a secondary output current at a first output terminal and a second output terminal, respectively, which collectively constitute an output based on a product of said primary and secondary voltages, said analog multiplier comprising:
- a primary pair of first and second transistors, said first transistor having a base electrode connected to a first input terminal and a collector electrode connected to said first output terminal supplied with said primary output current, said second transistor having a base electrode connected to a second input terminal and a collector electrode connected to said second output terminal supplied with said secondary output current;
- a secondary pair of third and fourth transistors, said third transistor having a base electrode connected to a third input terminal and a collector electrode connected to said second output terminal, said fourth transistor having a base electrode connected to a fourth input terminal and a collector electrode connected to said first output terminal;
- a first current source connected to emitter electrodes of said first through said fourth transistors; and
- a voltage supplying circuit connected to said first through said fourth input terminals for producing, in response to said primary and said secondary voltages of V.sub.1 and V.sub.2, a first voltage of (1/2)V.sub.1, a second voltage of (-1/2)V.sub.1, a third voltage of {(1/2)V.sub.1 -V.sub.2 }, and a fourth voltage of {(-1/2)V.sub.1 -V.sub.2 } to supply said first through fourth voltages of (1/2)V.sub.1, (-1/2)V.sub.1, {(1/2)V.sub.1 -V.sub.2 }, and {(-1/2)V.sub.1 -V.sub.2 } to said first through fourth input terminals, respectively;
- the output of the analog multiplier being present between the first and second output terminals.
- 2. The analog multiplier as claimed in claim 1, wherein said emitter electrodes of said first through said fourth transistors are directly connected to each other and to said first current source.
- 3. The analog multiplier as claimed in claim 2, wherein said voltage supplying circuit is supplied with said primary voltage (V.sub.1) between first and second circuit input terminals and said secondary voltage (V.sub.2) between third and fourth circuit input terminals to produce said first through said fourth voltages and comprises:
- a plurality of transistors connected to said first through said fourth circuit input terminals and to said first through said fourth input terminals and supplied with a constant current source to supply said first through said fourth voltages to said first through said fourth input terminals, respectively; and
- first and second resistors connected to said plurality of transistors and to said first and second output terminals, respectively, to produce said output voltage between said first and said second output terminals in response to a difference current between said primary and said secondary output currents.
- 4. The analog multiplier as claimed in claim 3, wherein:
- said plurality of transistors comprise fifth through thirteenth transistors, each of which has a base electrode, an emitter electrode, and a collector electrode, the eighth, the tenth, and the eleventh transistors are diode connected;
- said third and said fourth input terminals are connected to the base electrode of said eighth and said tenth transistors, respectively;
- said first through said fourth circuit input terminals are connected to the base electrodes of the seventh, the ninth, the fifth, and the sixth transistors, respectively;
- the base electrodes of said eleventh through said thirteenth transistors are commonly connected;
- the collector electrodes of said fifth and said sixth transistors are connected to the emitter and the collector electrodes of said eleventh transistor, respectively, the collector electrodes of said seventh and said eighth transistors are connected to the emitter and the collector electrodes of said thirteenth transistor respectively, the collector electrodes of said ninth and said tenth transistors are connected to the emitter and the collector electrodes of the twelfth transistor, respectively;
- the emitter electrodes of said fifth and said sixth transistors are connected to a second current source, the emitter electrodes of said seventh and said eighth transistors are connected to a second current source, the emitter electrodes of said ninth and said tenth transistors are connected to a fourth current source, and said second through said fourth current sources constitutes said constant current source;
- the emitter electrodes of said tenth through said thirteenth transistors are connected to a common node, said first and said second resistors are connected to said common node and to said first and said second output terminals, respectively.
- 5. The analog multiplier as claimed in claim 4, wherein each current of said second to said fourth current sources are equal to a half of a current of said first current source connected to the emitter electrodes of said first through said fourth transistors.
Priority Claims (1)
Number |
Date |
Country |
Kind |
4-328258 |
Dec 1992 |
JPX |
|
Parent Case Info
This is a Continuation of application Ser. No. 08/665,918 filed Jun. 19, 1996, now abandoned, which is a continuation of prior application Ser. No. 08/458,008 filed Jun. 1, 1995, U.S. Pat. No. 5,576,653 which is a continuation of prior application Ser. No. 08/162,261 filed Dec. 7, 1993, now abandoned.
US Referenced Citations (16)
Non-Patent Literature Citations (4)
Entry |
Zhenhua Wang, "A CMOS Four Quadrant Analog Multiplier with Single Ended Voltgae Output and Improved Temperature Performance", IEEE Journal of Solid State Circuits, No. 9, pp. 1293-1301, Sep. 1991. |
Patent Abstracts of Japan, Abstract of JP-A 3-033989. |
K. Kimura, "A Unified Analysis of Four-Quadrant Multipliers Consisting of Emitter and on Low Supply Voltage," IEICE Transactions on Electronics, vol. E76-C, No. 5, May 1993, pp. 714-737. |
K. Kimura, "A Bipolar Very Low-Voltage Multiplier Core Using a Quadritail Cell," IEICE Trans. Fundamentals, vol. E78-A, No. 5 May 1995, pp. 560-565. |
Continuations (3)
|
Number |
Date |
Country |
Parent |
665918 |
Jun 1996 |
|
Parent |
458008 |
Jun 1995 |
|
Parent |
162261 |
Dec 1993 |
|