Patent Grant
6940548
The present invention relates to image processing, and, more particularly, to an analog front end for a charge coupled device and CMOS imager, which provides analog optical black and offset correction having a wide gain range.
Advances in integrated circuit design and manufacturing have enabled low cost, highly integrated, high performance image processing products, including the digital electronic cameras. A conventional camera comprises an image sensor, typically an array charge coupled device (CCD), an analog front end (AFE) and a digital image processor. The CCD is an integrated array of photocells used in digital imaging. Most analog front ends having optical black and offset calibration include schemes that integrate the error signal across a capacitor during an optical black period and feed back the voltage generated to the input to cancel the offset or the optical black value during the video interval.
As shown in circuit 100 of
Moreover, the loop gain of the correction circuit changes when the programmable gain changes. In order to keep the loop gain constant, the loop gain needs to be changed significantly because the programmable gain can change from 0 to 36 dB. In addition, this approach relies on device matchings which may cause a yield issue.
Thus, there exists a need for an analog optical black and offset correction circuit for CCD signal processing having a wide gain range that does not require a large capacitor or an extremely small capacitor.
To address the above-discussed deficiencies of the analog front end circuitry having optical black and offset correction, the present invention teaches an offset and optical black correction circuit having a wide gain range. A first embodiment of the image processing apparatus in accordance with the present invention includes a first circuit to sample the incoming optical black signal output from a CCD. This first circuit includes a correlated double sampler coupled to a first programmable gain amplifier. An adder connects between the first programmable gain amplifier and a second gain amplifier for adding in the optical black offset to the optical black signal input from the CCD. A second circuit couples to the first circuit to provide a feedback loop for the first circuit. It includes a reverse programmable gain amplifier connected to the output of the second programmable gain amplifier to amplify the optical black level inversely proportional to the gain from the second programmable gain amplifier. The second circuit also includes an integrator coupled to the reverse programmable gain amplifier to integrate the difference between the incoming signal and the desired optical black value. The second circuit couples to the adder to add the positive and negative difference to the optical black signal. An analog-to-digital converter converts the sampled signal for further processing at the output of the image processing apparatus.
The image processing apparatus may be implemented using switch capacitors. In addition, this design provides further flexibility in that the programmable gain amplifiers and the reverse programmable gain amplifier may be implemented using single-ended or differential amplifiers.
Advantages of this design include but are not limited to an analog front end circuit having mixed signal optical black and offset circuitry that is highly programmable. This circuit has an improved dynamic range for image processing over other approaches. As such, this highly programmable design can be used both in discrete and continuous time systems and does not require any off-chip components.
For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings in which like reference numbers indicate like features and wherein:
In accordance with the present invention, the sum of the channel offset and optical black level is averaged using an analog low-pass filter. Particularly, a first embodiment of an analog front end circuit 200 in accordance with the present invention is shown in FIG. 2. This circuit 200, which receives an input signal from a CCD, provides a CCD signal processing method for optical black offset correction. AFE 200 receives a CCD input. Capacitor C2 is an AC coupling capacitor that clamps the direct current (DC) value of the error signal. CDS 202 couples between capacitor C2 and a first PGA 204 which amplifies the error signal. An adder 206 receives the output from PGA 204 and supplies the signal to a second PGA 208. The output of PGA 208 is fed back to RPGA 212 which transfers the error signal to integrator 214. Integrator 214 averages the error signal and couples to adder 206 to sum the output of the first PGA 204.
This embodiment splits the PGA into two stages a first PGA 204 and a second PGA 208. The correction signal is fed back to a point after PGA 204 and before PGA 208 leaving only PGA 208 within the optical black control loop. Effectively, the output from PGA 208 within the correction loop cancels the error of PGA 204. The range of PGA 208 may be from 1 to 4. Accordingly, the RPGA 212 has an adjustable gain range proportional to the reciprocal of PGA 208 which is easier to implement than the conventional approach.
Circuit 300 is controlled by the control signal having a first and a second phase, φ1 and φ2. In operation, during the first phase φ1 of a control signal for the analog front end circuit 300, switches S1, S2, S5, S6, S9, S12, S13, and S15 close, while all others remain open. The converse is true during the second phase φ2 of the control signal: switches S3, S4, S7, S8, S10, S11, S14, and S16 close, while all others remain open. Thus, during the first phase φ1 within a first cycle of the control signal, the input signal is stored by capacitor C3 and the correction signal Vf is stored by capacitor C4. During the second phase φ2 within the first cycle of the control signal, the input signal is amplified by differential amplifier 303 to yield an output Vout1. Switches S3, S4, S7, S8, S10, and S11 close, enabling capacitors C5 and C6 to charge up to voltage Vout1 and capacitor C7to charge up to voltage VCM. During a first phase φ1 within a second cycle of the control signal, capacitor C7 charges to voltage Vout2, since switch S9 and S12 close. In addition, switches S13 and S15 close to effectively charge capacitor C8 to voltage Vout2. During the second phase φ2 within the second cycle of the control signal, switches S14 and S16 close to charge capacitor C8 to the difference between voltages Vout2 and Vb, the desired optical black value. Differential amplifier 307 amplifies signal Vout2 inversely proportional to the gain of amplifier 305. As a result, capacitor C9's charge increases by a fraction of the difference between voltages Vout2 and Vb. The output of integrator 306 provides a correction signal or feedback voltage Vf which couples into the first programmable gain amplifier 302 as shown.
Specifically, gain G1 of PGA1302 is:
G1=C3/C5 [1]
where capacitor C3 varies and capacitor C5 is constant. The output Vout1 of PGA 302 is:
Vout1=G1* Vin+(C4/C5)* Vf [2]
Where C4 is also constant. The output of PGA 304 is
Vout2=G2*Vout1=G2*G1*Vin+G2*(C4/C5)*Vf [3]
As shown in the equation above, the correction signal Vf is only amplified by gain of PGA 304, G2, not by gain G1 of PGA 302. Since gain G1 of PGA 302 is adjusted by changing sampling capacitor C3 instead of feedback capacitor, the correction signal Vf is not amplified by PGA 302. Thus, the correction signal is effectively injected after PGA 302 and before PGA 304.
Integrator 306 acts as a reverse programmable gain amplifier and integrator. To maintain a constant loop gain, the RPGA gain of integrator 306 only needs to adjust when gain G2 changes. Since the variation of gain G2 is already greatly reduced, if the loop gain requirement is not strict we may use a constant RPGA gain within integrator 306 which simplifies the design significantly.
The advantage of the present invention includes but is not limited to a CMOS AFE having optical black correction where device matching is relaxed for the voltage comparison. This is a key improvement over other approaches specifically for designs that use smaller capacitors.
In the alternative, another embodiment in accordance with the present invention may include a single-ended amplifier implementation to substitute for the differential amplifier implementation shown in FIG. 3.
The present invention finds application in a great many video systems including digital still cameras, digital video cameras, digital video processing systems, CCD signal processors, and CMOS imagers, in a variety of industrial, medical, and military sensor and imaging applications.
The reader's attention is directed to all papers and documents which are filed concurrently with this specification and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.
All the features disclosed in this specification (including any accompany claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.
The terms and expressions which have been employed in the foregoing specification are used therein as terms of description and not of limitation, and there is no intention in the use of such terms and expressions of excluding equivalents of the features shown and described or portions thereof, it being recognized that the scope of the invention is defined and limited only by the claims which follow.
The present invention relates to a copending application U.S. Application No. TBN, Filed Nov. 1, 2000, a continuation application from U.S. application Ser. No. 09/353,919, filed Jul. 15, 1999 which claims priority under 35 U.S.C. § 119(e)(1) of provisional application No. 60/092,912, filed Jul. 15, 1998. In addition, the present invention relates to a copending application entitled “A CMOS Analog Front End Architecture with Variable Gain for Digital Cameras and Camcorders,” U.S. application Ser. No. 09/654,192, filed Sep. 1, 2000, which claims priority under 35 U.S.C. § 119(e)(1) of provisional application No. 60/152,436, filed Sep. 3, 1999 and claims benefit of 60/251,024, filed Dec. 4, 2000.
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