Patent Application
20100123612
1. Technical Field
The present disclosure relates to an analog-to-digital conversion circuit and device (ADC), preferably for mobile telephony.
2. Description of the Related Art
In mobile telephony, in some cases, an analog-to-digital conversion of single-ended type electric signals is required, i.e., of electric signals having a single voltage reference, preferably to the ground.
Generally, an analog-to-digital conversion device is arranged to receive in input a single-ended type electric signal coming from a relative external source having a distinctive output impedance which is not usually known or, if it is known, of a high value.
In these operative conditions, the need is felt to have the use of an analog-to-digital conversion device arranged for the reading of the high impedance input electric signal without incurring the typical errors associated with the division between source impedance and input impedance.
In order to meet this need, the analog-to-digital conversion device should be arranged to have also a very high input impedance, ideally an infinite one; therefore, a corresponding very low switched input or sampling capacitance (typically on the order of some fractions of pF, for example, at most of 0.3 pF), and a very high input resistance (typically of the order of some MOhms) is used.
Currently, the above requirement relative to the switched input capacitance is not found in known analog-to-digital conversion devices.
In fact, an analog-to-digital conversion device of a known design, directly arranged for the 10-bit sampling of an input electric signal, has an input capacitance of some pFs (for example, 5-6 pFs) to obviate further drawbacks related to usual problems such as, for example, the linearity or the noise. The operative choice of an input or sampling capacitance of some pFs contrasts with the choice of having a very low input or sampling capacitance value (at most equal to 0.3 pF).
In an alternative solution to the described one, the use is suggested of a unitary voltage buffer (for example, implemented with operational amplifiers) of the input electric signal arranged upstream of the analog-to-digital conversion device. Such a solution does not give an input or sampling capacitance that is as low as that required, and it also results in unreliability in terms of accuracy for conversion of single-ended type signals. This is due to the fact that, while the single-ended type analog-to-digital conversion device are arranged to convert the input signal from a ground voltage level (0V) to a predetermined reference level, which can even be very high, in any case the analog voltage buffer does not result in the ability to achieve the ground voltage level because it has active structures that begin to switch off when the voltage level is near to 0.
In other words, the single-ended type analog-to-digital conversion device with an input signal unitary voltage buffer arranged upstream has a criticality in reaching the ground voltage level.
Again, as an alternative, typically resistive structures could be employed, but this again has performance results that are unable to meet the requirement of a high input impedance.
The present disclosure provides an analog-to-digital conversion device having an alternative and improved design and function compared to the analog-to-digital conversion devices of the above-mentioned known art, and particularly which ensures reduced conversion criticalities of a ground voltage level or another reference voltage level.
In accordance with the present disclosure, an analog-to-digital conversion device is provided that includes an input stage arranged to receive an input signal and to provide an output analog signal as a function of the input signal; and an analog-to-digital conversion block arranged to receive the analog output signal and to provide a respective output digital signal, wherein the input stage includes a first voltage buffer arranged to provide the analog output signal to the conversion block as a translation of the input signal of an amount equivalent to a translation voltage; and a second voltage buffer arranged to provide a first reference signal to the conversion block that is representative of a translation of a first reference voltage of an amount equivalent to the translation voltage, so that the conversion block stores the input signal as a difference between the input signal and the first reference voltage, regardless of the translation voltage.
In accordance with the present disclosure, a circuit is provided that includes an input stage having an input and an output, the input stage including a first transistor having a drain and a source adapted to receive first and second voltage references, respectively, and a gate adapted to receive input signals; a second transistor having a drain and a source adapted to receive the first and second voltage references, and a gate adapted to receive the first voltage reference; and a third transistor having a drain and a source adapted to receive the first and second voltage references, respectively, and a gate adapted to receive a third reference voltage, the first transistor adapted to output on its source a translated voltage input signal, the second transistor adapted to output on its source a first reference signal, and the third transistor adapted to output on its source a second reference signal.
In accordance with the present disclosure, a mobile device is provided that includes a circuit that includes an input stage having an input and an output, the input stage including a first transistor having a drain and a source adapted to receive first and second voltage references, respectively, and a gate adapted to receive input signals; a second transistor having a drain and a source adapted to receive the first and second voltage references, and a gate adapted to receive the first voltage reference; and a third transistor having a drain and a source adapted to receive the first and second voltage references, respectively, and a gate adapted to receive a third reference voltage, the first transistor adapted to output on its source a translated voltage input signal, the second transistor adapted to output on its source a first reference signal, and the third transistor adapted to output on its source a second reference signal.
Further characteristics and advantages of the device according to the disclosure will be more readily appreciated from the description reported below of preferred exemplary embodiments, given by way of non-limiting, indicative example, when taken in conjunction with the annexed Figures, in which:
With reference to
The conversion device 100, which can be also referred to with the acronym ADC (Analogical to Digital Converter), finds application preferably in the mobile telephony technology in which single-ended type signals are employed.
The conversion device 100 includes an input stage 200 so arranged as to receive an analog-type input signal vin coming from a conventional signal source (not shown in the Figures) and to provide an analogical output signal vin′ which is a function of the input signal vin.
The conversion device 100 further includes an analog-to-digital conversion block 300, hereinafter also simply conversion block, per se known and operatively cascade-connected to the input stage 200 to receive in input the output analog signal vin′, and to provide in output a respective digital signal Vout.
An example of a conversion block 300 is described in U.S. Pat. No. 6,897,801 owned by the Applicant.
The input stage 200 includes a first voltage buffer B1, preferably a first source follower device.
The first source follower device B1 includes a first P-channel MOS-type transistor T1 having a predetermined channel width/length equal to W1/L1.
The first transistor T1 has the gate terminal G1 arranged to receive the input signal vin.
The drain terminal D1 of the first transistor T1 is operatively coupled to a first reference voltage Vss, the ground potential (0V) in the example.
The source terminal S1 of the first transistor T1 is operatively coupled to a second reference voltage Vcc, for example, the supply voltage, through a first direct current generator I1. A typical supply voltage value for these applications is, for example, 2.5 V. The body of the first transistor T1 is electrically connected to the respective source terminal S1. The source terminal S1 of the first transistor D1 is operatively coupled to the analog-to-digital conversion block 300 in order to provide it with the input stage 200 output analog signal vin′.
The first source follower device B1 is structured or arranged so that the output analog signal vin′ is a translation of the input signal vin by an amount equal to a translation voltage Vsh:
v
in
=v
in′
+V
sh
in which Vsh=Vth (threshold voltage of the first transistor T1)+Vov (overdrive voltage of the first transistor T1).
It shall be noticed that the overdrive voltage Vov of the first transistor T1 is the voltage that is required to allow the first transistor T1 to transfer the current I imposed by the first current generator I1.
It shall be noticed, anyhow, that the overdrive voltage Vov of the first transistor T1 is independent from the input signal vin, except for negligible effects for accuracy conversions of the order, for example, of 10 bit.
The input stage 200 further includes a second voltage buffer B2, preferably a second source follower device.
The second source follower device B2 includes a second P-channel MOS-type transistor T2 that is similar to the first transistor T1, i.e., having a channel width/length ratio equal to W1/L1.
The second transistor T2 has the respective gate terminal G2 operatively connected to the first reference voltage Vss. The drain terminal D2 of the second transistor T2 is also electronically coupled to the first reference voltage Vss. The source terminal S2 of the second transistor T2 is operatively coupled to the second reference voltage Vcc, for example, the input voltage, through a second direct current generator 12 is similar to the first current generator I1. The body of the second transistor T2 is electronically connected to the respective source terminal s2.
The source terminal S2 of the second transistor T2 is, in turn, operatively connected to the analog-to-digital conversion block 300 to provide it with a first reference signal Vrif1.
The second source follower device B2 is structured or arranged so that the first reference signal Vrif1 is representative of the translation of the first reference voltage Vss by an amount equal to the translation voltage Vsh:
V
rif1
=Vss+V
sh
It shall be noticed that the translation voltage Vsh of the second source follower device B2 is substantially the same as the first source follower device B1 since, as already stated above, the second transistor T2 is substantially identical to the first transistor T1.
It is pointed out that a difference between the translation voltages, which is determined by statistic mismatches of the transistors and the currents results to be, in any case, sizeable at will during the device manufacturing step, therefore it is considerable as well as negligible.
The input stage 200 further includes a third voltage buffer B3, preferably a third source follower device.
The third source follower device B3 includes a third P-channel MOS-type transistor T3 completely similar to the first T1 and the second T2 transistors already described above, i.e., having a channel width/length ratio equal to W1/L1.
The third transistor T3 has the respective gate terminal G3 operatively connected to a third reference voltage Vref, preferably a fraction of the second reference voltage Vcc. In the case where the first reference voltage Vcc (supply voltage) is equal to 2.5 V, the third reference voltage Vref results to be equal, for example, to 1.25 V.
The source terminal S3 of the third transistor T3 is operatively coupled to the second reference voltage Vcc, through a third direct current generator 13, which is substantially similar to the first I1 and the second I2 current generators described above. The body of the third transistor T3 is electrically connected to the respective source terminal S3.
The source terminal S3 of the third transistor T3 is, in turn, operatively connected to the analog-to-digital conversion block 300, in order to provide it with a second reference signal Vrif2.
The third source follower device B3 is arranged so that the second reference signal Vrif2 is representative of the translation of the second reference voltage Vref by an amount equal to the translation voltage Vsh:
V
rif2
=V
ref
+V
sh
It shall be noticed that the translation voltage Vsh of the third source follower device B3 is substantially the same as the first B1 and the second B2 source follower devices since, as already stated above, the third transistor T3 is substantially identical to the first T1 and the second T2 transistors.
Referring to the conversion block 300 of the example described, it is structured or arranged to receive in input the output analog signal vin′ the first reference signal Vrif1, and the second reference signal Vrif2 coming from the input stage 200, respectively.
As known, the conversion block 300, in order to generate the output digital signal Vout, carries out a first storing operation of the input signal vin relative to the first reference voltage Vss (being a single-ended type conversion block), and a second comparison operation of the input signal vin that is stored with the third reference voltage Vref in order to achieve the analog-to-digital conversion of the same input signal vin (by implementing, for example, a successive-approximation algorithm, per se known).
Referring to the first storing operation, the conversion block 300 performs, during the first storing operation, the difference between the output analog signal vin′ and the first reference signal Vrif1, as indicated herein below:
v
in′
−v
rif1
=v
in
+v
sh−(Vss+Vsh)
whereby, cancelling out the terms relative to the translation voltage Vsh, it is obtained that:
v
in′
−v
rif1
=v
in
−V
ss
As it shall be noticed, advantageously, the stored input signal vin is, in effect, compared to the first reference voltage Vss (in the example, the ground voltage).
Furthermore, it shall be noticed that the compensation of the translation voltage Vsh allows the conversion block to recover the input signal vin as the difference of the input signal vin and the first reference voltage Vss independently from the translation voltage Vsh.
This results to be rather advantageous, since the translation voltage Vsh, being a function of the threshold voltage Vth and the overdrive voltage Vov of the transistor T1, is process- and temperature-dependant and, for example, it would not allow the proper identification of the level 0 of the input signal Vin by the conversion block 300.
This is due to the use of the first B1 and second B2 voltage buffers that allow having, in input at the conversion block 300, the input signal Vin and the first reference voltage translated by the same translation voltage Vsh.
As regards the second comparison operation between the stored input signal vin and the third reference voltage Vref, it is pointed out that the conversion block 300 establishes, according to a successive-approximation algorithm (per se known), whether the input signal is higher or lower compared to a comparison level that is equal to Vref/2, and then compared to a comparison level that is equal to Vref/4 or 3/4Vref, and so on.
From an operative point of view, the conversion block 300 is structured or arranged as to contextually obtain the third reference voltage Vref as a difference between the second reference signal Vrif2 and the first reference signal Vrif1, as indicated herein below:
V
rif2
−V
rif1
=V
ref
+V
sh−(Vss+Vsh)
whereby, by cancelling out the terms relative to the translation voltage Vsh, it is obtained that:
V
rif2
−V
rif1
=V
ref
−V
ss
As it shall be noticed, the third reference voltage Vref that is employed in the second comparison operation with the stored input signal vin is obtained as the difference between the third reference voltage Vref and the first reference voltage Vss (ground voltage).
Furthermore, it shall be noticed that the compensation of the translation voltage Vsh allows the conversion block 300 to retrieve the third reference voltage Vref as the difference of the third reference voltage Vref and the first reference voltage Vss, independently from the translation voltage Vsh.
This results to be rather advantageous, since the translation voltage Vsh, being a function of the threshold voltage Vth and the overdrive voltage Vov of the transistor T1, is process- and temperature-dependant, and it would not allow, for example, the proper identification of the exact level of the third reference voltage Vref, thus involving the missampling of the input signal vin by the conversion block 300.
This is due to the use of the second B2 and the third B3 voltage buffers, which allows having, in input at the conversion block 300, the input signal Vin and the first reference voltage translated by the same translation voltage Vsh.
In this manner, the conversion block 300 is such as to provide in output the digital signal Vout by comparing the actual input signal Vin to the actual third reference voltage Vref.
It shall be noticed that according to the example of the disclosure described, the conversion block 300 is arranged to perform the first recovery operation of the input signal Vin and the second recovery operation of the reference voltage Vref by employing the same fixed reference, i.e., the first reference voltage Vss, that is the ground voltage (0V).
It shall be noticed that the conversion block 300 described can be referred to as being of the pseudo-differential type. Alternatively, the analog-to-digital conversion device 100 may include a differential-type conversion block.
As stated above, the analog-to-digital conversion device 100 of the described example advantageously allows comparing the input signal Vin and the third reference voltage Vref by compensating the presence of the translation voltage, and avoiding that the action of process and/or temperature variations that could condition or alter the accuracy of the reference signals and voltages that are employed by the conversion block 300 to generate the digital signal Vout.
Referring back to the input stage 200, it is pointed out that the use of a first voltage buffer, particularly a first source follower device, allows having the required requirements met by an analog-to-digital conversion device that is dedicated, in particular, to single-ended type signals. Such requirements, which are typical for a source follower device, are: high input impedance (ideally, infinite), low input capacitance (below 0.3 pF), transfer linearity, and high band (typically of the order of Mhzs) necessary for the transfer from input to output of the analog signal also in the presence of a considerable capacitive charge, as the analog-to-digital conversion block 300 can be.
Referring now to
Instead, as regards the electric connection to the first reference voltage Vss of the gate terminal G2, it is pointed out that an optional variation of the first reference voltage Vss would involve an equal variation of the first reference signal Vrif1. Therefore, to obviate this drawback, the gate terminal G2 of the second transistor T2 is electrically connected to the common pad PD through a dedicated second electrical connection path P2. It shall be noticed that, since the gate G2 does not absorb current anyhow, the second path P2 can be manufactured with a relatively high resistance (even of hundreds of Ohm), without varying the first reference voltage Vss value, and with a reduced use of the area or reduced area usage.
Therefore, the particular layout shown in
Referring to
The analog-to-digital conversion device 100′ is structured or arranged for the conversion of single-ended type signals relating to a first reference voltage, for example, the supply voltage.
It shall be noticed that, compared to the example of
The analog-to-digital conversion device 100′ includes a dual input stage 200′ as the above-described input stage 200, and an analog-to-digital conversion block 300′ which is completely similar to that described above.
The input stage 200′ includes a first voltage buffer B1, preferably a first source follower device, including a first N-channel MOS-type transistor T1' having: the respective gate terminal G1′ arranged to receive the input signal vin; the respective drain terminal D1′ connected to the first reference voltage Vcc; the source terminal S1′ connected to a second reference voltage Vss, in the example, the ground voltage (0V), through a first current generator I1′; and a body connected to the source terminal S1′.
The input stage 200′ further includes a second voltage buffer B2, preferably a second source follower device, including a second N-channel MOS-type transistor T2′ having: the respective gate G2′ and drain D2′ terminals connected to the first supply voltage Vcc; the source terminal S2′ connected to the second reference voltage Vss (0V) through a second current generator 12′; and a body connected to the source terminal S2′.
The input stage 200′ further includes a third voltage buffer B3, preferably a third source follower device, including a third N-channel MOS-type transistor T3′ having: the respective gate terminal G3′ connected to the third reference voltage Vref; the respective drain terminal D3′ connected to the first reference voltage Vcc; and the source terminal S3 connected to the second reference voltage Vss (0V) through a third current generator 13.
The first voltage buffer B1′ is structured or so arranged as to provide the conversion block 300′ with an output analog signal vin″ which is representative of the translation of the input signal vin by an amount equal to a translation voltage Vsh′.
The second voltage buffer B2′ is structured or arranged as to provide the conversion block 300′ with a first reference signal Vrif′ which is representative of the translation of the first reference voltage Vcc by an amount equal to the translation voltage Vsh′.
The third voltage buffer B3′ is structured or arranged to provide the conversion block 300′ with a second reference signal Vrif2′ that is representative of the translation of the third reference voltage Vref by an amount equal to the translation voltage Vsh′.
It is pointed out that the first T1′, the second T2′, and the third T3′ transistors have the same channel width/length W2/L2, and therefore the translation voltage Vsh′ is the same for each of the transistors.
Furthermore, the first I1′, the second I2′, and the third I3′ current generators are preferably completely identical one to the other.
The conversion block 300′, in the first storing operation of the input signal vin, is structured to store the input signal vin as the difference between the input signal vin and the first reference voltage Vcc regardless of the translation voltage Vsh′. This avoids the criticality of the identification of input signal voltage levels nearest to the second reference voltage Vcc.
Furthermore, the conversion block 300′, in the second comparison operation between the stored input signal vin and the third reference voltage Vref, is so arranged as to obtain the third reference voltage Vref as the difference between the second reference voltage Vcc and the third reference voltage Vref regardless of the translation voltage Vsh′. This eliminates or reduces the possibility of having an erroneous recovery of the third reference voltage Vref and a consequent malfunctioning of the conversion block 300′.
Furthermore, also for this further embodiment, the presence of source follower devices allows the input stage 200′ to meet the requirements of an analog-to-digital conversion device of single-ended signals as already indicated before, and that can be found, as already specified above, in a source follower device.
As it shall be noticed, the object of the disclosure is fully achieved, since the analog-to-digital conversion device according to the described embodiments allows reducing the criticalities in the identification of the input signal to be converted at the reference level equal to 0V or another reference level.
Furthermore, the input stage with voltage buffer adapted to translate the respective input signal by a same quantity (translation voltage vsh) allows the conversion device to store the input signal (vin) and to obtain the sampling comparison signal (third reference voltage Vref) regardless of the translation voltage that results to be being a function of the threshold and overdrive voltage of the transistors employed, and therefore varying with the process and the temperature.
Finally, the reliability of the proposed conversion device is also improved by the requirements of high input impedance, low input capacitance, transfer linearity, and high band, which are ensured by the type of voltage buffers (source follower devices) that is employed in the input stage.
To the above-described embodiments of the device, those of ordinary skill in the art, in order to meet contingent needs, will be able to make modifications, adaptations, and replacements of elements with functionally equivalent other ones, without departing from the scope of the following claims. Each of the characteristics described as belonging to a possible embodiment can be implemented regardless of the other embodiments described.
The various embodiments described above can be combined to provide further embodiments. All of the U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet are incorporated herein by reference, in their entirety. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments.
These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| MI2008A002067 | Nov 2008 | IT | national |
