This application claims the benefit under 35 USC § 119 (a) of Korean Patent Application No. 10-2023-0193211, filed on Dec. 27, 2023 in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes.
The following description relates to an analog-to-digital converter (ADC) circuit and a method and device using the same.
Biosignal technology may include biosignal measurement, analysis of measurement results, and stimulation. A living body may be a part or the whole body of various living organisms, such as the human body, animals, and plants, and biosignal technology may include identifying biological structures, biological functions, etc. Since a biosignal is an analog signal, for analysis, a biosignal may be converted into a digital signal. An analog signal may be converted into a digital signal using an analog-to-digital converter (ADC). An ADC may convert analog signals collected from the natural world into a digital format that a computer can understand.
This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In one or more general aspects, an analog-to-digital converter (ADC) circuit includes an ADC module configured to convert an analog input signal into an original digital output signal, an error detection module configured to detect overflow of the original digital output signal due to the analog input signal being out of an input dynamic range of the ADC module and determine a current state of the original digital output signal as a normal state or an error state, and a correction module configured to, in response to the current state of the original digital output signal being the normal state, output a corrected digital output signal based on the original digital output signal, and, in response to the current state of the original digital output signal being the error state, output the corrected digital output signal based on a replacement output signal for replacing the original digital output signal.
The ADC module may include a digital-to-analog converter (DAC) module configured to convert a previous original digital output signal into a previous analog output signal, an adjustment module configured to adjust the analog input signal using the previous analog output signal, an oscillator module configured to generate an oscillator signal controlled by an output signal of the adjustment module, and a phase detection and quantization module configured to perform phase detection and quantization on the oscillator signal to generate the original digital output signal.
For the detecting of the overflow, the error detection module may be configured to detect the overflow of the original digital output signal based on a difference between the original digital output signal and a previous original digital output signal.
For the determining of the current state, the error detection module may be configured to, in response to the current state of the original digital output signal being the normal state and the difference between the original digital output signal and the previous original digital output signal exceeding a first threshold value, determine the current state of the original digital output signal as the error state.
For the determining of the current state, the error detection module may be configured to, in response to the current state of the original digital output signal being the error state and the difference between the original digital output signal and the previous original digital output signal being less than a second threshold value, determine the current state of the original digital output signal as the normal state.
For the determining of the current state, the error detection module may be configured to, in response to a state in which the difference between the original digital output signal and the previous original digital output signal is less than a second threshold value persisting for a threshold time, determine the current state of the original digital output signal as the normal state.
The correction module may include a buffer module configured to store original digital values of the original digital output signal, a delay selection module configured to select one of the original digital values as a temporary value from the buffer module based on a delay value that is set to correspond to a delay of the corrected digital output signal, and an output selection module configured to select the temporary value or a replacement value as a digital value of the corrected digital output signal based on the current state of the original digital output signal.
The correction module further may include a comparison module configured to compare the temporary value to a reference value.
The replacement value may include a first sub-replacement value and a second sub-replacement value, and, for the selecting of the temporary value or the replacement value, the output selection module may be configured to, in response to the replacement value being selected as the digital value of the corrected digital output signal, select the first sub-replacement value or the second sub-replacement value as the digital value of the corrected digital output signal based on a comparison result between the temporary value and the reference value.
The replacement value may be a boundary value of the original digital output signal or a temporary restoration value of a replacement waveform for temporarily restoring a waveform of the analog input signal that is out of the input dynamic range.
The ADC circuit may include a memory configured to store temporary restoration values of the replacement waveform including the temporary restoration value.
The ADC circuit may include a digital filter configured to perform digital filtering of the corrected digital output signal and a decimation filter configured to perform decimation on an output of the digital filter.
The ADC circuit may be a delta sigma (DS) ADC.
The ADC circuit may be a voltage-controlled oscillator (VCO)-based DS ADC.
In one or more general aspects, an electronic device includes the ADC circuit and one or more processors configured to determine biometric information of one or more nerves based on the corrected digital output signal, wherein the analog input signal is measured from the one or more nerves.
In one or more general aspects, an electronic device includes signal measuring instruments configured to determine digital output signals corresponding to analog input signals measured from nerves, the signal measuring instruments comprising an analog-to-digital converter (ADC) circuit comprising an analog-to-digital converter (ADC) module configured to convert an analog input signal of the analog input signals into an original digital output signal, an error detection module configured to detect overflow of the original digital output signal due to the analog input signal being out of an input dynamic range of the ADC module and determine a current state of the original digital output signal as a normal state or an error state, and a correction module configured to, in response to the current state of the original digital output signal being the normal state, output a digital output signal of the digital output signals based on the original digital output signal, and, in response to the current state of the original digital output signal being the error state, output the digital output signal of the digital output signals based on a replacement output signal for replacing the original digital output signal, and one or more processors configured to determine biometric information of the nerves based on the digital output signals including the output digital output signal.
The biometric information may include any one or any combination of any two or more of a neural signal, a neural response, connectivity of nerves, and connection strength of nerves.
For the detecting of the overflow, the error detection module may be configured to detect the overflow of the original digital output signal based on a difference between the original digital output signal and a previous original digital output signal.
For the determining of the current state, the error detection module may be configured to, in response to the current state of the original digital output signal being the normal state and the difference between the original digital output signal and the previous original digital output signal exceeding a first threshold value, determine the current state of the original digital output signal as the error state.
In one or more general aspects, a signal processing method includes converting an analog input signal into an original digital output signal, detecting overflow of the original digital output signal due to the analog input signal being out of an input dynamic range of an analog-to-digital converter (ADC) module and determining a current state of the original digital output signal as a normal state or an error state, outputting a corrected digital output signal based on the original digital output signal, in response to the current state of the original digital output signal being the normal state, and outputting the corrected digital output signal based on a replacement output signal for replacing the original digital output signal, in response to the current state of the original digital output signal being the error state.
Other features and aspects will be apparent from the following detailed description, the drawings, and the claims.
Throughout the drawings and the detailed description, unless otherwise described or provided, the same drawing reference numerals will be understood to refer to the same elements, features, and structures. The drawings may not be to scale, and the relative size, proportions, and depiction of elements in the drawings may be exaggerated for clarity, illustration, and convenience.
The following detailed description is provided to assist the reader in gaining a comprehensive understanding of the methods, apparatuses, and/or systems described herein. However, various changes, modifications, and equivalents of the methods, apparatuses, and/or systems described herein will be apparent after an understanding of the disclosure of this application. For example, the sequences within and/or of operations described herein are merely examples, and are not limited to those set forth herein, but may be changed as will be apparent after an understanding of the disclosure of this application, except for sequences within and/or of operations necessarily occurring in a certain order. As another example, the sequences of and/or within operations may be performed in parallel, except for at least a portion of sequences of and/or within operations necessarily occurring in an order, e.g., a certain order. Also, descriptions of features that are known after an understanding of the disclosure of this application may be omitted for increased clarity and conciseness.
Although terms such as “first,” “second,” and “third”, or A, B, (a), (b), and the like may be used herein to describe various members, components, regions, layers, or sections, these members, components, regions, layers, or sections are not to be limited by these terms. Each of these terminologies is not used to define an essence, order, or sequence of corresponding members, components, regions, layers, or sections, for example, but used merely to distinguish the corresponding members, components, regions, layers, or sections from other members, components, regions, layers, or sections. Thus, a first member, component, region, layer, or section referred to in the examples described herein may also be referred to as a second member, component, region, layer, or section without departing from the teachings of the examples.
Throughout the specification, when a component or element is described as “on,” “connected to,” “coupled to,” or “joined to” another component, element, or layer, it may be directly (e.g., in contact with the other component, element, or layer) “on,” “connected to,” “coupled to,” or “joined to” the other component element, or layer, or there may reasonably be one or more other components elements, or layers intervening therebetween. When a component or element is described as “directly on”, “directly connected to,” “directly coupled to,” or “directly joined to” another component element, or layer, there can be no other components, elements, or layers intervening therebetween. Likewise, expressions, for example, “between” and “immediately between” and “adjacent to” and “immediately adjacent to” may also be construed as described in the foregoing.
The terminology used herein is for describing various examples only and is not to be used to limit the disclosure. The articles “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. As non-limiting examples, terms “comprise” or “comprises,” “include” or “includes,” and “have” or “has” specify the presence of stated features, numbers, operations, members, elements, and/or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, operations, members, elements, and/or combinations thereof, or the alternate presence of an alternative stated features, numbers, operations, members, elements, and/or combinations thereof. Additionally, while one embodiment may set forth such terms “comprise” or “comprises,” “include” or “includes,” and “have” or “has” specify the presence of stated features, numbers, operations, members, elements, and/or combinations thereof, other embodiments may exist where one or more of the stated features, numbers, operations, members, elements, and/or combinations thereof are not present.
As used herein, the term “and/or” includes any one and any combination of any two or more of the associated listed items. The phrases “at least one of A, B, and C”, “at least one of A, B, or C”, and the like are intended to have disjunctive meanings, and these phrases “at least one of A, B, and C”, “at least one of A, B, or C”, and the like also include examples where there may be one or more of each of A, B, and/or C (e.g., any combination of one or more of each of A, B, and C), unless the corresponding description and embodiment necessitates such listings (e.g., “at least one of A, B, and C”) to be interpreted to have a conjunctive meaning.
Unless otherwise defined, all terms, including technical and scientific terms, used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure pertains and based on an understanding of the disclosure of the present application. Terms, such as those defined in commonly used dictionaries, should be construed to have meanings matching with contextual meanings in the relevant art and the disclosure of the present application, and are not to be construed to have an ideal or excessively formal meaning unless otherwise defined herein.
The features described herein may be embodied in different forms, and are not to be construed as being limited to the examples described herein. Rather, the examples described herein have been provided merely to illustrate some of the many possible ways of implementing the methods, apparatuses, and/or systems described herein that will be apparent after an understanding of the disclosure of this application. The use of the term “may” herein with respect to an example or embodiment (e.g., as to what an example or embodiment may include or implement) means that at least one example or embodiment exists where such a feature is included or implemented, while all examples are not limited thereto. The use of the terms “example” or “embodiment” herein have a same meaning (e.g., the phrasing “in one example” has a same meaning as “in one embodiment”, and “one or more examples” has a same meaning as “in one or more embodiments”).
Hereinafter, examples will be described in detail with reference to the accompanying drawings. When describing the examples with reference to the accompanying drawings, like reference numerals refer to like components and a repeated description related thereto will be omitted.
The ADC module 110 may convert the analog input signal 101 into an original digital output signal. The ADC module 110 may include an amplifying module 111 (e.g., one or more amplifiers), an adjustment module 112 (e.g., one or more adjusters), an oscillator module 113 (e.g., one or more oscillators), a phase detection and quantization module 114 (e.g., one or more phase detectors and quantizers), and a digital-to-analog converter (DAC) module 115 (e.g., one or more DACs).
The ADC module 110 may be based on a delta sigma (DS) ADC. For example, the ADC module 110 may be a DS ADC. The DS ADC is a type of ADC and may operate by correcting an output signal (e.g., a digital signal corresponding to a conversion result) based on the difference between an input signal and the output signal. Since the DS ADC has relatively many parts that may be implemented digitally, an implementation area may be effectively reduced when using a fine complementary metal-oxide-semiconductor (CMOS) process. In addition, due to unique operation characteristics of the DS ADC, a frequency component of a quantization error that occurs when converting to digital data may be adjusted. The frequency component may be adjusted by noise shaping. Subsequently, the frequency component may be removed through a digital filter and low-noise digital data may be obtained. The DS ADC may be used effectively when a chip size is limited or a multi-channel low-noise ADC is required. The DS ADC may also be used in a multi-channel neural network neural signal measurement system.
The ADC module 110 may be based on a voltage-controlled oscillator (VCO)-based DS ADC. For example, the ADC module 110 may be a VCO-based DS ADC. The VCO-based DS ADC may be an ADC that implements an operation of the DS ADC based on a VCO. The VCO may generate signals at different frequencies depending on the amplitude of a control signal. In the VCO-based DS ADC, the difference between the input signal and the output signal may be used as the control signal of the VCO. A function of the DS ADC may be implemented by processing the frequency of an oscillation signal that is output according to the control signal. The VCO-based DS ADC may maximize advantages of digital implementation. The VCO may be implemented as a ring oscillator, and a method of detecting a phase-based frequency of an oscillation signal of the VCO may be used in the VCO-based DS ADC, since both the ring oscillator and the method of detecting a phase-based frequency are suitable for digital implementation.
The amplifying module 111 may amplify the analog input signal 101. For example, the amplifying module 111 may be or include an operational transconductance amplifier (OTA). However, examples are not limited thereto. When the amplifying module 111 includes the OTA, the analog input signal 101 may be a voltage signal and an output signal of the amplifying module 111 may be a current signal. Referring to
The DAC module 115 may convert a previous original digital output signal into a previous analog output signal. The previous original digital output signal may refer to an original digital output signal generated at a previous time. The adjustment module 112 may adjust the analog input signal 101 using the previous analog output signal. The adjustment module 112 may be or include one or more adders. The analog input signal 101 may be an output of the amplifying module 111. The adjustment module 112 may adjust the analog input signal 101 through a control technique of the DS ADC.
The oscillator module 113 may generate an oscillator signal that is controlled by an output signal of the adjustment module 112. The oscillator module 113 may be or include one or more oscillators. A frequency of the oscillator signal may be adjusted by the output signal of the adjustment module 112. The phase detection and quantization module 114 may perform phase detection and quantization on the oscillator signal to generate an original digital output signal. When the analog input signal 101 corresponds to a differential signal, the oscillator signal may also correspond to a differential signal and the frequency difference of the differential oscillator signal may be converted into a phase difference through signal integration. The original digital output signal may be generated according to quantization based on the phase difference.
When the ADC module 110 uses a phase, the ADC module 110 may have an input dynamic range. The input dynamic range may represent a range of the amplitude of an input signal, in which the input signal may be converted into a digital signal without ambiguity. When the analog input signal 101 is out of the input dynamic range of the ADC module 110, overflow may occur in the original digital output signal. Overflow may refer to a state of an original digital signal in which an expression value of the original digital signal does not reflect an actual value.
The error detection and correction module 120 may detect the overflow, may determine a current state of the original digital output signal as a normal state or an error state, and may output a corrected digital output signal based on the determined current state of the original digital output signal. When the current state of the original digital output signal is the normal state, the error detection and correction module 120 may output the corrected digital output signal based on the original digital output signal and when the current state of the original digital output signal is the error state, the error detection and correction module 120 may output the corrected digital output signal based on a replacement output signal for replacing the original digital output signal.
The filtering and decimation module 130 may be or include a digital filter for performing digital filtering of the corrected digital output signal and a decimation filter for performing decimation on an output of the digital filter. The digital output signal 131 may be a result of filtering and decimation on the corrected digital output signal.
The analog input signal 101 may be measured from nerves. Biometric information of nerves may be determined (e.g., by at least one processor 1020 of
The error detection module 310 may detect the overflow of the original digital output signal 301 based on the difference between the original digital output signal 301 and a previous original digital output signal. For example, the original digital output signal 301 may be a current value of the original digital output signal 301 and the previous original digital output signal may be a previous value of the original digital output signal 301.
When the current state of the original digital output signal 301 is the normal state and the difference between the original digital output signal 301 and the previous original digital output signal exceeds a first threshold value, the error detection module 310 may determine the current state of the original digital output signal 301 as the error state. When the current state of the original digital output signal 301 is the error state and the difference between the original digital output signal 301 and the previous original digital output signal is less than a second threshold value, the error detection module 310 may determine the current state of the original digital output signal 301 as the normal state. When a state in which the difference between the original digital output signal 301 and the previous original digital output signal is less than a second threshold value persists for a threshold time, the error detection module 310 may determine the current state of the original digital output signal 301 as the normal state.
The state machine 311 may represent the current state of the original digital output signal 301 as the normal state or the error state. The comparison and count module 312 may determine the difference between a current digital value X[n] and a previous digital value X[n−1] of the original digital output signal 301. When the current state is the normal state and the difference therebetween exceeds the first threshold value, the comparison and count module 312 may convert the current state from the normal state to the error state. When the current state is the error state and the difference is less than the second threshold value, the comparison and count module 312 may convert the current state from the error state to the normal state. When the difference therebetween is less than the second threshold value, the comparison and count module 312 may not immediately convert the current state from the error state to the normal state. For example, when a state in which the difference therebetween is less than the second threshold value persists for a threshold time, the comparison and count module 312 may convert the current state from the error state to the normal state. For example, when the difference therebetween has been less than the second threshold value for a predetermined number of time iterations, the comparison and count module 312 may convert the current state from the error state to the normal state. For example, when the difference between the digital value X[n] and the digital value X[n−1], the difference between the digital value X[n−1] and a digital value X[n−2], . . . , and the difference between a digital value X[n−(N−1)] and a digital value X[n−N] (where N is a predetermined natural number greater than n) are each less than the second threshold value, the comparison and count module 312 may convert the current state from the error state to the normal state. The second threshold value may be less than the first threshold value. The conditions for converting the error state to the normal state may be defined more strictly than the conditions for converting the normal state to the error state, as the conditions for converting the error state to the normal state require the threshold time and the second threshold value to be less than the first threshold value.
The correction module 320 may generate the corrected digital output signal 302 based on the original digital output signal 301. The original digital output signal 301 may be represented by X and the corrected digital output signal 302 may be represented by Y. The buffer module 321 may store original digital values (e.g., X[n] and X[n−1]) of the original digital output signal 301. The delay selection module 322 may select one of the original digital values as a temporary value from the buffer module 321 based on a delay value set to correspond to a delay of the corrected digital output signal 302. The output selection module 324 may select the temporary value or a replacement value as a digital value of the corrected digital output signal 302 based on the current state of the original digital output signal 301.
The comparison module 323 may compare the temporary value to a reference value. The replacement value may include a first sub-replacement value and a second sub-replacement value. When the output selection module 324 selects the replacement value as the digital value of the corrected digital output signal 302, the output selection module 324 may select the first sub-replacement value or the second sub-replacement value as the digital value of the corrected digital output signal 302 based on a comparison result between the temporary value and the reference value. For example, the reference value may be 0, a first replacement value may be a positive replacement value, and a second replacement value may be a negative replacement value. When the temporary value is greater than 0, the output selection module 324 may select the positive replacement value as the digital value of the corrected digital output signal 302 and when the temporary value is less than 0, the output selection module 324 may select the negative replacement value as the digital value of the corrected digital output signal 302.
When overflow is detected, the current state may be converted from the normal state 410 to the error state 420. A condition for the conversion may be expressed as ABS (X[n]−X[n−1])>THRES1. ABS may represent an absolute value and THRES1 may represent a first threshold.
In the error state 420, the corrected digital output signal may be output based on a replacement output signal for replacing the original digital output signal. The corrected digital output signal of the error state 420 may be expressed as Y [n]=A1 (TMP_X>REFR), Y [n]=A2 (TMP_X<REFR). A1 may represent a first sub-replacement value, A2 may represent a second sub-replacement value, and RFER may represent a reference value. For example, a replacement value may be a boundary value of the original digital output signal. For example, when the original digital output signal has a minimum value of −16 and a maximum value of 15, the first sub-replacement value of the replacement value may be 15 and the second sub-replacement value of the replacement value may be −16. The reference value may be 0. In another example, the replacement value may be a temporary restoration value of a replacement waveform for temporarily restoring a waveform of an analog input signal that is out of an input dynamic range.
When overflow is not continuously detected, the current state may be converted from the error state 420 to the normal state 410. A condition for the conversion may be expressed as ABS (X[n]−X[n−1])<THRES2 occurring CNT times continuously. THRES2 may represent a second threshold and CNT may represent a threshold count value corresponding to a threshold time.
In general, a waveform of a nerve signal is known to be in the form of a spike with a short amplitude. When analyzing the waveform of the measured nerve signal, the size of the signal does not change significantly for most of the time and the signal keeps being high or low only for a short period of time. When a neural signal is measured for the purpose of analyzing a neural network configuration, it may be important to measure a signal level (e.g., post-synaptic potential (PSP)) of the occurrence time of a spike waveform of the neural signal and before the occurrence of the spike waveform of the neural signal, rather than measure the entire spike waveform of the neural signal. An ADC circuit of one or more embodiments may manage with overflow when analyzing the neural network configuration by using a corrected digital output signal based on the replacement output signal without adjusting an input gain or an additional analog circuit.
In operation 920, it may be checked whether overflow has occurred. Whether overflow has occurred may be checked based on a condition such as ABS (X[n]−X[n−1])>THRES1. When overflow has occurred, a current state may change from the normal state to an error state. When overflow has not occurred, operation 910 may be performed again. When overflow has occurred, the current state may be determined as the error state. In operation 930, the temporary value may be compared to a reference value.
When the temporary value is greater than the reference value, a corrected digital signal in the error state may be output based on a first sub-replacement value, in operation 940. The corrected digital signal may be expressed as Y [n]=A1 (TMP_X>REFR).
In operations 950 and 970, it may be checked whether overflow does not occur continuously. Whether overflow does not occur continuously may be checked based on a condition such as ABS (X[n]−X[n−1])<THRES2 occurring CNT times continuously. When overflow does not occur continuously, the current state may convert from the error state to the normal state.
The signal measuring instruments 1010 may determine digital output signals corresponding to analog input signals measured from nerves. For example, the signal measuring instruments 1010 may include any one, any combination, or all of the components of
The at least one processor 1020 may determine biometric information of nerves based on the digital output signals. The biometric information may include a nerve signal, a nerve response, connectivity of nerves, connection strength of nerves, or a combination thereof. The at least one memory 1030 may include a non-transitory computer-readable storage medium storing instructions that, when executed by the at least one processor 1020, configure the at least one processor 1020 to perform any one, any combination, or all of the operations and/or methods disclosed herein with reference to
The ADC circuits, ADC blocks, error detection and correction blocks, filtering and decimation blocks, amplifying blocks, adjustment blocks, oscillator blocks, phase detection and quantization blocks, DAC blocks, error detection blocks, correction blocks, state machines, comparison and count blocks, delay selection blocks, output selection blocks, electronic devices, signal measuring instruments, processors, memories, ADC circuit 100, ADC block 110, error detection and correction block 120, filtering and decimation block 130, amplifying block 111, adjustment block 112, oscillator block 113, phase detection and quantization block 114, DAC block 115, error detection and correction block 300, error detection block 310, correction block 320, state machine 311, comparison and count block 312, delay selection block 322, comparison block 323, output selection block 324, ADC circuit 500, electronic device 1000, signal measuring instruments 1010, at least one processor 1020, and at least one memory 1030 described herein, including descriptions with respect to respect to
The methods illustrated in, and discussed with respect to,
Instructions or software to control computing hardware, for example, one or more processors or computers, to implement the hardware components and perform the methods as described above may be written as computer programs, code segments, instructions or any combination thereof, for individually or collectively instructing or configuring the one or more processors or computers to operate as a machine or special-purpose computer to perform the operations that are performed by the hardware components and the methods as described above. In one example, the instructions or software include machine code that is directly executed by the one or more processors or computers, such as machine code produced by a compiler. In another example, the instructions or software includes higher-level code that is executed by the one or more processors or computer using an interpreter. The instructions or software may be written using any programming language based on the block diagrams and the flow charts illustrated in the drawings and the corresponding descriptions herein, which disclose algorithms for performing the operations that are performed by the hardware components and the methods as described above.
The instructions or software to control computing hardware, for example, one or more processors or computers, to implement the hardware components and perform the methods as described above, and any associated data, data files, and data structures, may be recorded, stored, or fixed in or on one or more non-transitory computer-readable storage media, and thus, not a signal per se. As described above, or in addition to the descriptions above, examples of a non-transitory computer-readable storage medium include one or more of any of read-only memory (ROM), random-access programmable read only memory (PROM), electrically erasable programmable read-only memory (EEPROM), random-access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, non-volatile memory, CD-ROMs, CD-Rs, CD+Rs, CD-RWs, CD+RWs, DVD-ROM, DVD-Rs, DVD+Rs, DVD-RWs, DVD+RWs, DVD-RAMs, BD-ROMs, BD-Rs, BD-R LTHs, BD-REs, blue-ray or optical disk storage, hard disk drive (HDD), solid state drive (SSD), flash memory, a card type memory such as multimedia card micro or a card (for example, secure digital (SD) or extreme digital (XD)), magnetic tapes, floppy disks, magneto-optical data storage devices, optical data storage devices, hard disks, solid-state disks, and/or any other device that is configured to store the instructions or software and any associated data, data files, and data structures in a non-transitory manner and provide the instructions or software and any associated data, data files, and data structures to one or more processors or computers so that the one or more processors or computers can execute the instructions. In one example, the instructions or software and any associated data, data files, and data structures are distributed over network-coupled computer systems so that the instructions and software and any associated data, data files, and data structures are stored, accessed, and executed in a distributed fashion by the one or more processors or computers.
While this disclosure includes specific examples, it will be apparent after an understanding of the disclosure of this application that various changes in form and details may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are to be considered in a descriptive sense only, and not for purposes of limitation. Descriptions of features or aspects in each example are to be considered as being applicable to similar features or aspects in other examples. Suitable results may be achieved if the described techniques are performed in a different order, and/or if components in a described system, architecture, device, or circuit are combined in a different manner, and/or replaced or supplemented by other components or their equivalents.
Therefore, in addition to the above and all drawing disclosures, the scope of the disclosure is also inclusive of the claims and their equivalents, i.e., all variations within the scope of the claims and their equivalents are to be construed as being included in the disclosure.
Number | Date | Country | Kind |
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10-2023-0193211 | Dec 2023 | KR | national |