Claims
- 1. An analog to digital converter comprising:
- a set of three two-terminal resistive elements having a first terminal of each element connected to a common electrical node, wherein the first two of said resistive elements have the same resistance value and the third of said resistive elements has a resistive value of half of either of the first two resistive elements;
- analog integrator means having inverting and non-inverting inputs, said inverting input being connected to said common electrical node with said three two terminal resistive elements;
- analog comparator means also having inverting and non-inverting input nodes, said inverting input node of said comparator means being connected to the output of said integrator means;
- single bit clocked flip-flop means operating to change output states in response to the output of said comparator means;
- inverting means connected at its input to the non-inverted output of said flip-flop means and connected at its output to the second terminal of said second resistive element;
- means for supplying a voltage V.sub.DD to the second terminal of said third resistive means;
- means for supplying a voltage V.sub.DD /2 to the non-inverting nodes of said integrator means and said comparator means,
- whereby an analog signal applied to the second terminal of said first resistive element is converted to a serial binary signal from said flip-flop means in which the number of bits is representative, over a period of time, of the level of said analog signal.
- 2. The converter of claim 1 in which said integrator means comprises an operational amplifier having a capactive element connected between its output and an inverting input of said operational amplifier.
- 3. The converter circuit of claim 1 in which voltages V.sub.DD and V.sub.DD /2 are supplied from the same source.
- 4. The converter circuit of claim 1 in which said analog mean, said comparator means and said flip-flop means and said inverting means receive power from the same source that supplies said analog input signal.
- 5. The converter circuit of claim 1 in which said clock of said flip-flop means is operable at a frequency greater than the Nyquist frequency of said input signal.
- 6. An analog to digital converter comprising:
- an over-sampled analog-to-digital converter including an integrating operational amplifier with inverting and non-inverting inputs, an analog comparator also having inverting and non-inverting input nodes, said inverting input of said comparator being coupled to the output of said integrating amplifier and a single bit clocked flip-flop means coupled to the output of said comparator so as to change output states in response to the output of said comparator:
- inversion means coupled at its input to the output of said flip-flop means;
- means for supplying a voltage V.sub.DD /2 to the non-inverting input nodes of said operational amplifier and said comparator; and
- bias means for receiving voltage signals from an analog input source, from a supply having a voltage V.sub.DD and from the output of said inversion means, and for supplying a current to the inverting input node of said operational amplifier, said current being the sum of individual currents each individual current being proportional to one of said voltage V.sub.DD, said analog input and said inverter output voltage.
Parent Case Info
This application is a continuation of application Ser. No. 074,103, filed July 16, 1987, now abandoned.
US Referenced Citations (2)
Number |
Name |
Date |
Kind |
4542354 |
Robinton et al. |
Sep 1985 |
|
4573037 |
Robinton et al. |
Feb 1986 |
|
Non-Patent Literature Citations (3)
Entry |
Candy, James C., "A Use of Limit Cycle Oscillations to Obtain Robust Analog-to-Digital Converters", IEEE Trans, on Comm. vol. COM-22, No. 3; p.298. |
Inose, Hiroshi et al, "A Unity Bit Coding Method by Negative Feedback", Proceedings of the IEEE, Nov. 1963, pp. 1524-1535. |
Brainard, Ralph C. et al "Direct-Feedback Coders: Design and Performance with Television Signals"; Proc. of the IEEE May 1969, pp. 776-786. |
Continuations (1)
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Number |
Date |
Country |
Parent |
74103 |
Jul 1987 |
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