Analog-to-digital Converter Using Lookahead Pipelined Architecture and Open-loop Residue Amplifiers

Abstract

A lookahead pipelined ADC architecture uses open-loop residue amplifiers with calibration. This approach is able to achieve a high-speed, high-accuracy ADC with reduced power consumption. In one aspect, an ADC pipeline unit includes a plurality of lookahead pipeline stages (i.e., an ADC lookahead pipeline) coupled to a calibration unit. The ADC lookahead pipeline uses open-loop residue amplifiers. The calibration unit compensates for non-linearity in the open-loop amplifiers.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The invention has other advantages and features which will be more readily apparent from the following detailed description of the invention and the appended claims, when taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram illustrating a pipelined ADC architecture, suitable for use with the present invention.

FIG. 2 is a block diagram of a lookahead ADC pipeline with open-loop residue amplifiers, according to the invention.

FIG. 3 is a block diagram of a lookup table approach to compensate for amplifier non-linearity.

FIG. 4 is a block diagram illustrating calibration of the lookup table in FIG. 3.

FIG. 5 is a block diagram of an interleaved ADC using parallel ADC channels.

FIG. 6 is a block diagram illustrating calibration of an ADC channel.

FIGS. 7A and 7B show simulation results for an example ADC with and without calibration, respectively.

Claims

1. An ADC pipeline unit for converting input analog values to N-bit digital representations, the ADC pipeline unit comprising: a plurality of lookahead pipeline stages that generate a total of M raw bits, with M>N, the stages including open-loop residue amplifiers; anda calibration unit coupled to the lookahead pipeline stages to compensate for non-linearity in the open-loop residue amplifiers.

2. The ADC pipeline unit of claim 1 comprising M lookahead pipeline stages, wherein each lookahead pipeline stage generates 1 raw bit.

3. The ADC pipeline unit of claim 1 wherein the calibration unit comprises a lookup table.

4. The ADC pipeline unit of claim 3 wherein the lookup table uses the M raw bits as an address to the lookup table and the lookup table contains a corresponding N-bit digital representation at each M-bit address.

5. The ADC pipeline unit of claim 3 wherein the calibration unit updates the lookup table.

6. The ADC pipeline unit of claim 3 wherein the calibration unit updates the lookup table using an LMS algorithm.

7. The ADC pipeline unit of claim 1 wherein, for each stage other than the first stage, the stage includes a sub-ADC that determines possible raw bits for the stage without knowledge of the raw bits determined by a previous stage and then selects from among the possible raw bits based on the raw bits determined by the previous stage.

8. The ADC pipeline unit of claim 1 wherein the plurality of lookahead pipeline stages comprise: an input sample-and-hold stage for receiving the input analog value;a first lookahead pipeline half-stage coupled to the input sample-and-hold, for producing a first raw bit; andM−1 lookahead pipeline stages coupled in series to the first lookahead pipeline half-stage, each lookahead pipeline stage producing an additional raw bit;wherein each of the half-stage and the first M−2 stages includes an open-loop residue amplifier.

9. The ADC pipeline unit of claim 8 wherein: the first lookahead pipeline half-stage includes a single comparator for determining the first raw bit; andeach of the M−1 lookahead pipeline stages includes two comparators, one comparator for determining the raw bit for the stage assuming that the raw bit from a previous stage was 0 and another comparator for determining the raw bit for the stage assuming that the raw bit from the previous stage was 1.

10. The ADC pipeline unit of claim 9 wherein each of the M−1 lookahead pipeline stages further includes: a switch for selecting an output from one of the two comparators based on the raw bit from the previous stage.

11. The ADC pipeline unit of claim 1 wherein each stage other than the beginning stages and end stages includes: a sub-ADC for determining the raw bits for that stage; anda sub-DAC coupled to a subtractor for determining a residue for that stage, wherein the open-loop residue amplifier applies a gain to the determined residue.

12. The ADC pipeline unit of claim 1 wherein the lookahead pipeline stages can operate at a conversion rate of 1.25 GS/s or higher at an effective resolution of at least 5 bits per sample.

13. The ADC pipeline unit of claim 1 wherein the lookahead pipeline stages can operate at a quantization energy of 0.3 pJ/conv-step or less.

14. The ADC pipeline unit of claim 1 wherein N≧8.

15. The ADC pipeline unit of claim 1 wherein N≧5.

16. The ADC pipeline unit of claim 1 wherein the lookahead pipeline stages can operate at a conversion rate of 1.25 GS/s or higher at an effective resolution of at least 5 bits per sample, the lookahead pipeline stages can operate at a quantization energy of 0.3 pJ/conv-step or less, and N≧5.

17. An interleaved analog-to-digital converter (ADC) for converting an input stream of analog values to an output stream of N-bit digital representations, the ADC comprising: an analog demultiplexer for receiving an input stream of analog values and demultiplexing the input stream into K analog channels;K ADC channels coupled to the analog demultiplexer, each ADC channel for converting one of the analog channels to a digital channel of corresponding N-bit digital representations; anda digital multiplexer coupled to the K ADC channels for multiplexing the digital channels into the output stream of N-bit digital representations.

18. The interleaved ADC of claim 17 wherein the interleaved ADC can operate at a conversion rate of 10 GS/s or higher at an effective resolution of at least 5 bits per sample.

19. The interleaved ADC of claim 17 wherein each ADC channel includes an ADC pipeline unit comprising: a plurality of lookahead pipeline stages that generate a total of M raw bits, with M>N, the stages including open-loop residue amplifiers; anda calibration unit coupled to the lookahead pipeline stages to compensate for non-linearity in the open-loop residue amplifiers.

20. The interleaved ADC of claim 19 wherein each ADC channels includes at least two ADC pipeline units.

21. The interleaved ADC of claim 20 wherein, for each ADC channel, one ADC pipeline unit is in operation when the other ADC pipeline unit is in calibration.

22. The interleaved ADC of claim 20 wherein, for each ADC channel, one ADC pipeline unit is in operation when the other ADC pipeline unit is in calibration and the ADC pipeline units automatically interchange operation and calibration.

23. The interleaved ADC of claim 19 wherein each ADC pipeline unit has a sub-radix architecture.

24. The interleaved ADC of claim 19 wherein the calibration unit comprises a lookup table.

25. The interleaved ADC of claim 24 wherein the lookup table uses the M raw bits as an address to the lookup table and the lookup table contains a corresponding N-bit digital representation at each M-bit address.

26. The interleaved ADC of claim 19 wherein the plurality of lookahead pipeline stages comprise: an input sample-and-hold stage for receiving the input analog value;a first lookahead pipeline half-stage coupled to the input sample-and-hold, for producing a first raw bit; andM−1 lookahead pipeline stages coupled in series to the first lookahead pipeline half-stage, each lookahead pipeline stage producing an additional raw bit;wherein each of the half-stage and the first M−2 stages includes an open-loop residue amplifier.

27. The interleaved ADC of claim 26 wherein: the first lookahead pipeline half-stage includes a single comparator for determining the first raw bit; andeach of the M−1 lookahead pipeline stages includes two comparators, one comparator for determining the raw bit for the stage assuming that the raw bit from a previous stage was 0 and another comparator for determining the raw bit for the stage assuming that the raw bit from the previous stage was 1.

28. The interleaved ADC of claim 27 wherein each of the M−1 lookahead pipeline stages further includes: a switch for selecting an output from one of the two comparators based on the raw bit from the previous stage.

29. The interleaved ADC of claim 19 wherein each stage other than the beginning stages and end stages includes: a sub-ADC for determining the raw bits for that stage; anda sub-DAC coupled to a subtractor for determining a residue for that stage, wherein the open-loop residue amplifier applies a gain to the determined residue.

30. The interleaved ADC of claim 19 wherein the interleaved ADC can operate at a conversion rate of 10 GS/s or higher at an effective resolution of at least 5 bits per sample.

31. The interleaved ADC of claim 19 wherein the lookahead pipeline stages can operate at a conversion rate of 1.25 GS/s or higher.

32. The interleaved ADC of claim 19 wherein the lookahead pipeline stages can operate at a quantization energy of 0.3 pJ/conv-step or less.

33. The interleaved ADC of claim 19 wherein N≧5.