Claims
- 1. An analog-to-digital converter including:
- a main array of capacitors;
- a non-linear function generator capable of generating a voltage proportional to a quadratic error term associated with conversion error due to capacitor value dependence upon voltage; and
- a correction capacitor array, said correction array including an adjustable gain, said correction capacitor array being operable in combination with said non-linear function generator to add a correction factor, to said main array of capacitors, which is substantially equal in magnitude and opposite in sign to said quadratic error term.
- 2. An analog-to-digital converter as recited in claim 1 wherein said non-linear function generator is coupled to said main array of capacitors through said correction capacitor array.
- 3. An analog-to-digital converter as recited in claim 2 wherein said array if a single capacitor.
- 4. An analog-to-digital converter as recited in claim 2 wherein said correction capacitor array is a binary weighted capacitor array.
- 5. An analog to digital converter as recited in claim 1 wherein said non-linear function generator comprises:
- a first squarer circuit operable to generate a first current including a component dependent upon the square of differential input voltages;
- a first multiplier circuit, operable to generate a first output current proportional to the product of a differential input voltage, coupled to said first squarer circuit;
- a second multiplier circuit coupled to said first multiplier circuit and being operable to generate a second output current proportional to the product of a differential input voltage; and
- a second squarer circuit, operable to generate a second current including a component dependent upon the square of a differential reference voltage, coupled to said second multiplier circuit.
- 6. A self-calibration method for an analog-to-digital converter to correct a quadratic error term associated with conversion error due to capacitor value dependence upon voltage which includes:
- determining the sign of a correction term by comparing the sum of digital words after subtracting a reference word value against a threshold value; and
- iteratively adjusting the gain factor of a capacitor array.
- 7. The method of claim 6 wherein said iterative adjustment is accomplished by a binary method.
OBJECTS OF THE INVENTION
This application is a continuation of application Ser. No. 07/356,475, filed on May 24, 1989, now abandoned.
The dependence of capacitance on voltage can be expressed by the Taylor series expansion equation
Capacitor voltage dependence in relation to conversion error within an analog-to-digital (A/D) converter will be discussed with reference to the schematic drawing of an analog-to-digital converter including a single-ended charge redistribution capacitor array illustrated in FIG. 1a. Capacitors in the array are connected at a common top plate to inverter 2, which is connected across a switch 15, that is capable of shorting the input to the output of the inverter. As shown, capacitors within the array have weighted values of capacitance according to powers of 2. Each capacitor is connected to three switches labeled with a subscripted S, 0, and 1, where the subscripted N represents an integer which are operable to connect to a reference voltage V.sub.REF, an input voltage V.sub.IN and ground. In operation, sampling is accomplished by connecting the bottom plate of the capacitors to voltage V.sub.IN and by closing the switch across the inverter 2. Thus, charge is distributed across the capacitor plates due in part to the fact that inverter 2 has a current path established to circuit ground. Therefore, the top plate of the capacitors are charged to voltage V.sub.RS, the trip point of inverter 2. After the sampling operation, the voltage across the capacitors is held in a hold operation by opening the switch across inverter 2 and the switch connecting the bottom plate of the capacitors to V.sub.IN. The rest of the hold operation comprises connecting the bottom plate of the capacitor to ground. Charges are redistributed in a redistribution operation which follows the hold operation. Successive approximation of the input signal is accomplished by connecting one bottom plate of a single capacitor to V.sub.REF while connecting the bottom plates of remaining capacitors to ground. If the output of inverter 2 is a logic 1, then the switch connection to V.sub.REF is maintained, otherwise the connection to V.sub.REF is opened and the bottom plate of the capacitors is returned to ground. In a similar manner, the remaining capacitors are connected to either of two levels, a reference voltage V.sub.REF and ground. Effectively, a digital representation is carried out through summing proportioned factors of V.sub.REF until the sum substantially equals V.sub.IN. The coefficients of the summed proportions are the digital representation of the input voltage. During redistribution, the voltage into inverter 2 is as follows: ##EQU1##
Upon completion of the successive approximation steps, the common top plate of the capacitors will return to V.sub.RS. FIG. 1b is a schematic drawing which represents the A/D converter of FIG. 1a during the sampling operation or sampling phase. Note that capacitor C.sup.P is shown connected to the array and represents parasitic capacitance. FIG. 1c illustrates an equivalent circuit of the schematic drawing of FIG. 1a during the redistribution operation or phase. Capacitor C.sup.A represent the parallel sum of all capacitors in the array with the bottom plate switched to reference voltage V.sub.REF. Capacitor C.sub.B represent the parallel sum of all capacitors in the array with the bottom plate switched to ground. The ratio of capacitor C.sup.A to the sum of the quantity C.sup.A plus C.sup.B represents the fractional digital output. The perfect A/D converter will have such a ratio equal to V.sub.IN /V.sub.REF. Ideally, the binary weighting between all the array capacitors should be constant, unfortunately, array capacitances vary with voltage across the capacitors. Therefore, when the successive approximation algorithm implemented by the A/D converter trims capacitor C.sup.A to bring the node identified as being at voltage potential V.sub.t back to voltage V.sub.RS, then if, for example, an array capacitor that is switched to V.sub.REF on its bottom plate is less than its ideal binary value, the algorithm will later add more capacitance to produce a C.sup.A in order to achieve a V.sub.T =V.sub.RS. For example, if the current capacitor test in the successive approximation algorithm switches the bottom plate of a capacitor from ground to V.sub.REF, and if that capacitor is normally 16 pico farads (pf) but in actuality is only 15.9 pf because of bias voltage dependence, then the net effect on voltage V.sub.T will be less, and additional smaller capacitors will have to be switched up to V.sub.REF as well in order to reach the target of making V.sub.T =V.sub.RS.
Typically, CMOS ADCs up to 10-bit resolution are implemented in the single-ended topology of FIG. 1a; and voltage coefficients up to 800 ppm/volt can be tolerated. Beyond 10-bit resolution, fully differential topologies are used due to their general characteristics of improved noise immunity as well as an important extra degree of freedom in the sample-and-hold operations.
FIG. 2a illustrates a fully differential A/D converter architecture which comprises two identical arrays of capacitors which are connectable through a switch in each array to comparator 6. Voltage V.sub.SAM can be connected to each capacitor array through switches S.sub.SAM. Each capacitor in the arrays is associated with its own switch S.sub.C. The switches in the first array of capacitors are operable to connect either to voltages V.sub.IN-, V.sub.REF or ground. The switches in the second array of capacitors are operable to connect either to voltages V.sub.IN+, -V.sub.REF, or ground. During a sampling operation, switches S.sub.SAM, S.sub.A and S.sub.CM (switches S.sub.CM connect the common mode signal to comparator 6 and switches S.sub.A connect the arrays to the comparator) are closed and the switches of the first array are connected to voltage V.sub.IN- while the switches of the second array are connected to voltage V.sub.IN+. Thus, the top plates (top plates refer to the capacitor plates which directly contact the inputs of the comparator when the comparator switches are closed) of both arrays are charged to V.sub.SAM while the bottom plates of the first array are charged V.sub.IN- and the bottom plates of the second array are charged V.sub.IN+. In a hold operation, switches S.sub.SAM are opened and switches S.sub.C are connected to ground. After the hold operation switches connecting a common mode input voltage to comparator 6 are closed. Next, a charge redistribution operation is carried out implementing successive approximation of the input signal by connecting the bottom plates of the capacitors either to V.sub.REF or ground as in the previously discussed single-ended case. When a particular capacitor in one array is connected to V.sub.REF, the corresponding capacitor in the other array is connected to ground. Completion of conversion leaves both top plates at the potential of the common mode input voltage. FIG. 2b illustrates an equivalent circuit of the schematic drawing of FIG. 2a during the sampling operation or sampling phase. FIG. 2c is an equivalent circuit of the schematic drawing of FIG. 2a during the redistribution operation or phase. The fractional digital output ##EQU2## is as follows: with V.sub.T+ and V.sub.T- ((V.sub.T+ +V.sub.T-)/2=V.sub.T) approaching V.sub.REF /2 after successive approximation ##EQU3##
The error of the fully differential A/D converter architecture can be expressed (assuming for this case a zero voltage common mode input to comparator 6) as ##EQU4## C.sub.1 and C.sub.2 are coefficients and V.sub.IND is the differentially applied input voltage, V.sub.IN+ -V.sub.IN-. In A/D converters required to meet today's conversion accuracy demands, it is necessary to efficiently cancel both the first and second order factors of error. Until now, no existing A/D converters have accomplished this.
It is an object of the invention to provide a new and improved A/D converter.
It is another object of the invention to provide a new and improved A/D converter which corrects errors in measurement.
It is a further object of the invention to provide a new and improved A/D converter, having weighted capacitors, which corrects errors in measurement due to the capacitor value dependence upon voltage.
It is still a further object of the invention to provide a method for A/D error correction.
It is yet another object of the invention to provide a method for A/D error correction due to errors caused by capacitor value dependence upon voltage.
These and other objects of the invention, together with the features and advantages thereof, will become apparent from the following detailed specification when read together with the accompanying drawings, in which applicable reference numerals, reference symbols and reference letters have been carried forward.
The foregoing objects of the invention are accomplished by an apparatus and method which adds a correction term to an intermediate voltage of an A/D converter which uses capacitors or other devices whose values are capable of variation with voltage, in order to correct A/D conversion errors caused by value variation.
The apparatus comprises a non-linear function generator whose output is proportional to the input voltage of the capacitor multiplied by the quantity of a reference voltage of the converter squared minus the input voltage squared. The non-linear function generator is connected to a correction capacitor array, including adjustable gain, which scales the value of the generator output voltage so as to provide the proper correction factor necessary to be added to the A/D converter.
A method for adjusting/calibrating the gain factor of the capacitor array is provided by the invention, as well as a method for using the apparatus along with the gain factor adjustment/calibration.
US Referenced Citations (6)
Continuations (1)
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356475 |
May 1989 |
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Patent Grant
4975700
