Analog-to-digital converter

Abstract

An analog-to-digital converter includes a track hold circuit, a reference voltage generating circuit, a switched capacitor circuit, a preamplifier that amplifies a voltage held by the switched capacitor circuit, a comparator that generates a logic level corresponding to an output from the preamplifier, and an encoder that converts the logic level into a binary code (n-bit digital output). If capacitors constituting the switched capacitor circuit are charged and the charges in these capacitors then vary, each capacitor is recharged by an amount corresponding to the particular variation.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

A general architecture that implements the various feature of the invention will now be described with reference to the drawings. The drawings and the associated descriptions are provided to illustrate embodiments of the invention and not to limit the scope of the invention.

FIG. 1 is a diagram illustrating the configuration of a parallel A/D converter according to a first embodiment of the invention;

FIGS. 2A, 2B, 2C, 2D, 2E and 2F are timing charts, each of which illustrates the mutual relationship between signals obtained from a timing generating circuit for the A/D converter shown in FIG. 1;

FIG. 3 is a circuit diagram illustrating a specific example of a timing generating circuit for the A/D converter shown in FIG. 1;

FIG. 4 is a circuit diagram illustrating a specific example of a switched capacitor circuit and a preamplifier for the A/D converter shown in FIG. 1; and

FIG. 5 is a diagram illustrating the configuration of a parallel A/D converter according to a second embodiment of the invention.

Claims

1. An analog-to-digital converter comprising: a track hold circuit which follows a variation in analog input value and which holds the analog input value at a predetermined timing, the track hold circuit outputting the analog input hold value;a reference value generating circuit which generate predetermined reference values;a switched capacitor circuit including a switch circuit which is switched on and off at a predetermined timing and a capacitor circuit which is charged at the predetermined timing under a first voltage corresponding to the predetermined reference values, the switched capacitor circuit holding a second voltage corresponding to a difference between the predetermined reference values or the first voltage and the analog input hold value;a preamplifier which amplifies the second voltage held by the switched capacitance circuit to provide a preamplifier output and which has an input capacitance smaller than the capacity of the capacitor circuit;a comparator which generates a logic level corresponding to the preamplifier output; andan encoder which converts the logic level generated by the comparator into a binary code corresponding to the analog input value.

2. The analog-to-digital converter according to claim 1, further comprising a circuit which, if charges in the capacitor circuit charged under the first voltage vary, recharges the capacitor circuit by an amount corresponding to the variation.

3. The analog-to-digital converter according to claim 1, further comprising a timing generating circuit which generates first and second timing signals which set the predetermined timings with respect to a predetermined clock, the timing generating circuit being configured to generate the first and second timing signals and to generate a first pulse signal having a pulse width of a predetermined duration starting from a rear signal edge of the predetermined clock and a second pulse signal having a pulse width of a predetermined duration starting from a front signal edge of the predetermined clock, wherein the analog input hold value includes first and second analog input hold values, the predetermined reference values include first and second reference values, and the preamplifier output includes first and second preamplifier outputs,the capacitor circuits includes first and second capacitors, and the switch circuit includes a first switch which switches on and off a connection between one end of the first capacitor and the first reference value in accordance with the first timing signal, a second switch which switches on and off a connection between one end of the second capacitor and the second reference value in accordance with the first timing signal, a third switch which switches on and off a connection between one end of the first capacitor and the first analog input hold value in accordance with the second timing signal, and a fourth switch which switches on and off a connection between one end of the second capacitor and the second analog input hold value in accordance with the second timing signal, andthe preamplifier comprises a first transistor having a gate connected to the other end of the first capacitor, a drain providing the second preamplifier output, and a source, a second transistor having a gate connected to the other end of the second capacitor, a drain providing the first preamplifier output, and a source, a current source selectively connected to the sources of the first and second transistors, a fifth switch which switches on and off the gate and drain of the first transistor in accordance with the first pulse signal, a sixth switch which switches on and off the gate and drain of the second transistor in accordance with the first pulse signal, a seventh switch which switches on and off the current source and the source of each of the first and second transistors in accordance with the first pulse signal, and an eighth switch which switches on and off the current source and the source of each of the first and second transistors in accordance with the second pulse signal.

4. The analog-to-digital converter according to claim 3, which is configured so that if charges in the capacitor circuit charged under the first voltage vary, the seventh switch is turned on to recharge the capacitor circuit by an amount corresponding to the variation.

5. The analog-to-digital converter according to claim 1, wherein the track hold circuit is configured to output, as the analog input hold value, positive and negative analog hold input hold values corresponding to the analog input value, the reference value generating circuit is configured to generate positive and negative reference values as the predetermined reference value,the switched capacitor circuit is configured to hold, as the second voltage, a third difference between a first difference between the positive analog input hold value and the negative analog input hold value and a second difference between the positive reference value and the negative reference value,the preamplifier comprises a differential amplifying circuit which amplifies the third difference to provide positive and negative preamplifier outputs as the preamplifier output, andthe comparator is configured to generate the logic level on the basis of a numerical comparison of the positive preamplifier output with the negative preamplifier output.

6. The analog-to-digital converter according to claim 2, wherein the track hold circuit is configured to output, as the analog input hold value, positive and negative analog hold input hold values corresponding to the analog input value, the reference value generating circuit is configured to generate positive and negative reference values as the predetermined reference value,the switched capacitor circuit is configured to hold, as the second voltage, a third difference between a first difference between the positive analog input hold value and the negative analog input hold value and a second difference between the positive reference value and the negative reference value,the preamplifier comprises a differential amplifying circuit which amplifies the third difference to provide positive and negative preamplifier outputs as the preamplifier output, andthe comparator is configured to generate the logic level on the basis of a numerical comparison of the positive preamplifier output with the negative preamplifier output.

7. The analog-to-digital converter according to claim 3, wherein the track hold circuit is configured to output, as the analog input hold value, positive and negative analog hold input hold values corresponding to the analog input value, the reference value generating circuit is configured to generate positive and negative reference values as the predetermined reference value,the switched capacitor circuit is configured to hold, as the second voltage, a third difference between a first difference between the positive analog input hold value and the negative analog input hold value and a second difference between the positive reference value and the negative reference value,the preamplifier comprises a differential amplifying circuit which amplifies the third difference to provide positive and negative preamplifier outputs as the preamplifier output, andthe comparator is configured to generate the logic level on the basis of a numerical comparison of the positive preamplifier output with the negative preamplifier output.

8. The analog-to-digital converter according to claim 4, wherein the track hold circuit is configured to output, as the analog input hold value, positive and negative analog hold input hold values corresponding to the analog input value, the reference value generating circuit is configured to generate positive and negative reference values as the predetermined reference value,the switched capacitor circuit is configured to hold, as the second voltage, a third difference between a first difference between the positive analog input hold value and the negative analog input hold value and a second difference between the positive reference value and the negative reference value,the preamplifier comprises a differential amplifying circuit which amplifies the third difference to provide positive and negative preamplifier outputs as the preamplifier output, andthe comparator is configured to generate the logic level on the basis of a numerical comparison of the positive preamplifier output with the negative preamplifier output.

9. The analog-to-digital converter according to claim 1, wherein plural sets of the switched capacitor circuit, the preamplifier, and the comparator are provided, the reference value generating circuit is configured to generate different reference values the number of which corresponds to that of the plural sets, andthe switched capacitor circuits in the plural sets are configured to use the different reference values from the reference value generating circuit, as the predetermined reference values.

10. The analog-to-digital converter according to claim 2, wherein plural sets of the switched capacitor circuit, the preamplifier, and the comparator are provided, the reference value generating circuit is configured to generate different reference values the number of which corresponds to that of the plural sets, andthe switched capacitor circuits in the plural sets are configured to use the different reference values from the reference value generating circuit, as the predetermined reference values.

11. The analog-to-digital converter according to claim 3, wherein plural sets of the switched capacitor circuit, the preamplifier, and the comparator are provided, the reference value generating circuit is configured to generate different reference values the number of which corresponds to that of the plural sets, andthe switched capacitor circuits in the plural sets are configured to use the different reference values from the reference value generating circuit, as the predetermined reference values.

12. The analog-to-digital converter according to claim 4, wherein plural sets of the switched capacitor circuit, the preamplifier, and the comparator are provided, the reference value generating circuit is configured to generate different reference values the number of which corresponds to that of the plural sets, andthe switched capacitor circuits in the plural sets are configured to use the different reference values from the reference value generating circuit, as the predetermined reference values.

13. The analog-to-digital converter according to claim 5, wherein plural sets of the switched capacitor circuit, the preamplifier, and the comparator are provided, the reference value generating circuit is configured to generate different reference values the number of which corresponds to that of the plural sets, andthe switched capacitor circuits in the plural sets are configured to use the different reference values from the reference value generating circuit, as the predetermined reference values.

14. The analog-to-digital converter according to claim 8, wherein plural sets of the switched capacitor circuit, the preamplifier, and the comparator are provided, the reference value generating circuit is configured to generate different reference values the number of which corresponds to that of the plural sets, andthe switched capacitor circuits in the plural sets are configured to use the different reference values from the reference value generating circuit, as the predetermined reference values.

15. The analog-to-digital converter according to claim 1, wherein at least two sets of the switched capacitor circuit and the preamplifier are present, and the number of comparators is larger than that of combinations of the switched capacitor circuit and the preamplifier, the reference value generating circuit is configured to generate at least two different reference values,two of the switched capacitor circuits are configured to use the different reference values from the reference value generating circuit, as the predetermined reference values,an interpolation/averaging resistor column having at least one intermediate tap is provided between two of the preamplifiers, andinputs to two of the comparators are connected to outputs from two of the preamplifiers, and an input to any comparator which is different from the two comparators is connected to the at least one intermediate tap is provided between two of the preamplifiers, and the outputs from all the comparators are provided to the encoder.

16. The analog-to-digital converter according to claim 2, wherein at least two sets of the switched capacitor circuit and the preamplifier are present, and the number of comparators is larger than that of combinations of the switched capacitor circuit and the preamplifier, the reference value generating circuit is configured to generate at least two different reference values,two of the switched capacitor circuits are configured to use the different reference values from the reference value generating circuit, as the predetermined reference values,an interpolation/averaging resistor column having at least one intermediate tap is provided between two of the preamplifiers, andinputs to two of the comparators are connected to outputs from two of the preamplifiers, and an input to any comparator which is different from the two comparators is connected to the at least one intermediate tap is provided between two of the preamplifiers, and the outputs from all the comparators are provided to the encoder.

17. The analog-to-digital converter according to claim 3, wherein at least two sets of the switched capacitor circuit and the preamplifier are present, and the number of comparators is larger than that of combinations of the switched capacitor circuit and the preamplifier, the reference value generating circuit is configured to generate at least two different reference values,two of the switched capacitor circuits are configured to use the different reference values from the reference value generating circuit, as the predetermined reference values,an interpolation/averaging resistor column having at least one intermediate tap is provided between two of the preamplifiers, andinputs to two of the comparators are connected to outputs from two of the preamplifiers, and an input to any comparator which is different from the two comparators is connected to the at least one intermediate tap is provided between two of the preamplifiers, and the outputs from all the comparators are provided to the encoder.

18. The analog-to-digital converter according to claim 4, wherein at least two sets of the switched capacitor circuit and the preamplifier are present, and the number of comparators is larger than that of combinations of the switched capacitor circuit and the preamplifier, the reference value generating circuit is configured to generate at least two different reference values,two of the switched capacitor circuits are configured to use the different reference values from the reference value generating circuit, as the predetermined reference values,an interpolation/averaging resistor column having at least one intermediate tap is provided between two of the preamplifiers, andinputs to two of the comparators are connected to outputs from two of the preamplifiers, and an input to any comparator which is different from the two comparators is connected to the at least one intermediate tap is provided between two of the preamplifiers, and the outputs from all the comparators are provided to the encoder.

19. The analog-to-digital converter according to claim 13, wherein at least two sets of the switched capacitor circuit and the preamplifier are present, and the number of comparators is larger than that of combinations of the switched capacitor circuit and the preamplifier, the reference value generating circuit is configured to generate at least two different reference values,two of the switched capacitor circuits are configured to use the different reference values from the reference value generating circuit, as the predetermined reference values,an interpolation/averaging resistor column having at least one intermediate tap is provided between two of the preamplifiers, andinputs to two of the comparators are connected to outputs from two of the preamplifiers, and an input to any comparator which is different from the two comparators is connected to the at least one intermediate tap is provided between two of the preamplifiers, and the outputs from all the comparators are provided to the encoder.

20. The analog-to-digital converter according to claim 14, wherein at least two sets of the switched capacitor circuit and the preamplifier are present, and the number of comparators is larger than that of combinations of the switched capacitor circuit and the preamplifier, the reference value generating circuit is configured to generate at least two different reference values,two of the switched capacitor circuits are configured to use the different reference values from the reference value generating circuit, as the predetermined reference values,an interpolation/averaging resistor column having at least one intermediate tap is provided between two of the preamplifiers, andinputs to two of the comparators are connected to outputs from two of the preamplifiers, and an input to any comparator which is different from the two comparators is connected to the at least one intermediate tap is provided between two of the preamplifiers, and the outputs from all the comparators are provided to the encoder.