Analog-to-digital converter

Abstract

An analog-to-digital converter for converting an analog input voltage signal to a digital output voltage signal of m upper bits and n lower bits includes at least (2.sup.m+n -1) resistors connected in a series circuit to a voltage source for establishing respective reference voltages; at least (2.sup.m -1) upper bit voltage comparators for generating outputs indictive of the m upper bits, and having first and second inputs, the analog input voltage being applied to the first inputs and the second inputs being connected to the series circuit at respective intervals defining groups of the resistors; an upper bit encoder receiving the outputs of the upper bit voltage comparators and generating a switch control signal and a digital output voltage signal of m upper bits; at least (2.sup.n -1) lower bit voltage comparators for generating outputs indicative of the n lower bits, and having first and second inputs, the analog input voltage signal being applied also to the first inputs of the lower bit voltage comparators; switch elements associated with each of the groups and being responsive to the switch control signal for selectively connecting the second inputs of the lower bit comparators to respective resistors in the associated resistor groups; and a lower bit encoder receiving the outputs of the lower bit voltage comparators and generating a digital output voltage signal of n lower bits.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to analog-to-digital converters, and more particularly, to an analog-to-digital converter having a minimal number of voltage comparing circuits.

2. Description of the Prior Art

Prior art analog-to-digital converters can generally be classified as either parallel-type converters or serial-to-parallel type converters.

Parallel-type analog-to-digital converters which produce n bit digital outputs generally require (2.sup.n -1) comparing circuits or comparators connected in parallel. An analog input voltage is supplied to the (2.sup.n -1) voltage comparators, and the outputs from the comparators are supplied to an encoder which then produces the n digit output.

In a serial-to-parallel type analog-to-digital converter having an output of m upper bits and n lower bits, the input voltage is supplied to a first stage of (2.sup.m -1) voltage comparing circuits or comparators, just as in the parallel-type analog-to-digital converter, to generate the m upper bits. The m upper bits are then supplied to a digital-to-analog converter and reconverted to an analog voltage. The reconverted analog voltage is then subtracted from the analog input voltage and the difference is supplied to a second stage of (2.sup.n -1) voltage comparators to derive the n lower bits.

In the parallel-type analog-to-digital converter, (2.sup.n -1) voltage comparators are required when the analog input voltage is converted to a digital output of n bits. A large number of circuit elements are required for such an analog-to-digital converter, and the resulting integrated circuit is large and has a correspondingly large power consumption.

In the serial-to-parallel analog-to-digital converter, only (2.sup.m +2.sup.n -2) voltage comparators are used when the output has m+n bits. The chip size and power consumption are reduced as compared to the parallel-type analog-to-digital converter. However, a serial-to-parallel analog-to-digital converter requires a digital-to-analog converter. If an error occurs between the first and second stages of the converter, the error is repeated in the digital output. For example, with a monotonically increasing voltage V.sub.in, if an error occurs between the first and second stages so that the output from the first stage is reduced, the digital output from the second stage will be reduced, and the digital output of the converter will not increase monotonically.

OBJECTS AND SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provide an analog-to-digital converter which can overcome the aforementioned problems of prior art analog-to-digital converters.

It is another object of the present invention to provide an analog-to-digital converter which uses fewer voltage comparing circuits than the prior art devices.

It is still another object of the present invention to provide an analog-to-digital converter that can be formed in a compact, integrated circuit.

It is still a further object of the present invention to provide an analog-to-digital converter with a reduced power consumption as compared to the prior art devices.

In accordance with one aspect of the present invention, an analog-to-digital converter for converting an analog input voltage signal to a digital output voltage signal of m upper bits and n lower bits includes at least (2.sup.m+n -1) resistors connected in a series circuit to a voltage source for establishing respective reference voltages. Upper bit comparators with first and second inputs generate outputs indicative of the m upper bits, with the analog input voltage signal being connected to the first inputs and the series circuit of resistors being connected to the second inputs at respective intervals defining groups of the resistors. An upper bit encoder receives the outputs of the upper bit comparators and generates a switch control signal and a digital output voltage signal of m upper bits. Lower bit comparators with first and second inputs generate outputs indicative of the n lower bits, with the analog input voltage being connected to the first inputs. Switch elements are associated with each of the groups and are responsive to the switch control signal for selectively connecting the second inputs of the lower bit comparators to respective resistors in the associated resistor groups. A lower bit encoder receives the outputs of the lower bit comparators and generates a digital output voltage signal of n lower bits.

The above, and other objects, features and advantages of the invention will be apparent from the following detailed description of an illustrative embodiment thereof which is to be read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a prior art parallel-type analog-to-digital converter;

FIG. 2 is a block diagram showing a prior art serial-to-parallel analog-to-digital converter;

FIG. 3A is a block diagram illustrating an analog-to-digital converter according to one embodiment of the present invention;

FIGS. 3B and 3C are partial block diagrams illustrating the operation of the analog-to-digital converter of FIG. 3A; and

FIGS. 4 and 5 are truth tables of encoders illustrated in the embodiment of FIG. 3A.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring initially to FIG. 1, a parallel-type analog-to-digital converter known in the prior art is disclosed in which an analog input voltage V.sub.in is converted to an n=8 bit digital output D.sub.0 to D.sub.7. The parallel-type analog-to-digital converter of FIG. 1 has 255, that is, (2.sup.8 -1), voltage comparing circuits or comparators A.sub.1 to A.sub.255, providing 255 reference voltage steps V.sub.1 to V.sub.255. Analog input voltage V.sub.in is compared with each of reference voltages V.sub.1 to V.sub.255, and outputs from comparator circuits A.sub.1 to A.sub.255 are supplied to an encoder ENC.sub.1 which generates digital outputs D.sub.0 to D.sub.7.

In FIG. 2, a serial-to-parallel type analog-to-digital converter is shown in which analog input voltage V.sub.in is converted to a digital output voltage of n=4 lower bits and m=4 upper bits. In the illustrative embodiment, the n lower bits are denoted as D.sub.0 to D.sub.3, while the m upper bits are denoted as D.sub.4 to D.sub.7. Input voltage V.sub.in is supplied to a first or front stage of the serial-to-parallel type analog-to-digital converter having 15, that is, (2.sup.4 -1), comparison circuits or comparators A.sub.1m to A.sub.15m and corresponding voltage steps V.sub.1m to V.sub.15m, from which digital outputs are supplied to a first encoder ENC.sub.m, from which digital outputs D.sub.4 to D.sub.7 are derived. Digital outputs D.sub.4 to D.sub.7 are supplied to a digital-to-analog converter where they are reconverted to an analog voltage V.sub.m. Analog voltage V.sub.m is then subtracted from input voltage V.sub.in, and the difference is supplied to a second or rear stage of the serial-to-parallel type analog-to-digital converter. The second stage has 15, that is, (2.sup.4 -1) comparison circuits A.sub.1n to A.sub.15n and corresponding voltage steps V.sub.1n to V.sub.15n, and supplies outputs to a second encoder ENC.sub.n, which generates n lower bits D.sub.0 to D.sub.3.

Referring now to FIG. 3A, it will be seen that, in the analog-to-digital converter according to the embodiment of the invention there illustrated, an analog input voltage V.sub.in is supplied to first or positive inputs of three voltage comparators M.sub.1 to M.sub.3 for determining an upper bit digital voltage and three voltage comparators N.sub.1 to N.sub.3 for determining a lower bit digital voltage. Resistors R.sub.1 to R.sub.16 are connected in series between a reference voltage supply source V.sub.r and ground. The resistors R.sub.1 to R.sub.4, R.sub.5 to R.sub.8, R.sub.9 to R.sub.12, and R.sub.13 to R.sub.16 are arranged in groups of four resistors, with each group providing four reference voltage steps. Comparator M.sub.1 has its second or negative input connected between resistors R.sub.4 and R.sub.5 and is supplied with voltage V.sub.m1. Comparator M.sub.2 has its second or negative input connected between resistors R.sub.8 and R.sub.9 and is supplied with voltage V.sub.m2. Comparator M.sub.3 has its second or negative input connected between resistors R.sub.12 and R.sub.13 and is supplied with voltage V.sub.m3.

Switch elements, preferably in the form of metal oxide semiconductor field effect transistors (MOS-FETs) Q.sub.11, Q.sub.21, Q.sub.31 and Q.sub.41 have their sources connected to the series resistor circuit between resistors R.sub.1 and R.sub.2, R.sub.7 and R.sub.8, R.sub.9 and R.sub.10, and R.sub.15 and R.sub.16, respectively, and their drains connected to a second or negative input terminal of comparator N.sub.1. Switch elements constituted by MOS-FETs Q.sub.12, Q.sub.22, Q.sub.32 and Q.sub.42 are similarly connected between resistors R.sub.2 and R.sub.3, R.sub.6 and R.sub.7, R.sub.10 and R.sub.11, and R.sub.14 and R.sub.15 and a second or negative input terminal of comparator N.sub.2. Switch elements constituted by MOS-FETs Q.sub.13, Q.sub.23, Q.sub.33 and Q.sub.43 are similarly connected between resistors R.sub.3 and R.sub.4, R.sub.5 and R.sub.6, R.sub.11 and R.sub.12, and R.sub.13 and R.sub.14 and a second or negative input terminal of comparator N.sub.3.

Comparators M.sub.1, M.sub.2 and M.sub.3 generate output signals P.sub.1, P.sub.2 and P.sub.3 indicative of the upper bits of the digital output voltage. Outputs P.sub.1, P.sub.2 and P.sub.3 are supplied to an encoder ENCM from which upper bits D.sub.2 and D.sub.3 of the digital output are derived. Upper bit encoder ENCM also selectively generates control signals B.sub.1 to B.sub.4 which are supplied to the gates of respective MOS-FETs Q.sub.11 to Q.sub.13, Q.sub.21 to Q.sub.23, Q.sub.31 to Q.sub.33, and Q.sub.41 to Q.sub.43, respectively. In addition, upper bit encoder ENCM generates a second control signal S.sub.0, whose function will be described below.

Control signals B.sub.1 to B.sub.4 from encoder ENCM selectively actuate MOS-FET's Q.sub.11 to Q.sub.13, Q.sub.21 to Q.sub.23, Q.sub.31 to Q.sub.33, and Q.sub.41 to Q.sub.43, respectively, to supply voltages V.sub.n1, V.sub.n2, and V.sub.n3 to the negative input terminals of comparators N.sub.1, N.sub.2, and N.sub.3, as shown in FIGS. 3A and 3C, which generate outputs Q.sub.1, Q.sub.2, Q.sub.3 supplied to the lower bit encoder ENCN. Encoder ENCN generates lower bits D.sub.0 and D.sub.1 from outputs Q.sub.1, Q.sub.2, and Q.sub.3 and control signal S.sub.0 supplied from upper bit encoder ENCM.

FIG. 4 illustrates the truth table for the encoder ENCM, while FIG. 5 illustrates the truth table for the encoder ENCN. The table of FIG. 4 indicates the outputs B.sub.1 to B.sub.4, S.sub.0, D.sub.3 and D.sub.2 for given input signals P.sub.1 to P.sub.3. The table of FIG. 5 indicates the outputs D.sub.1 and D.sub.0 for given input signals S.sub.0, Q.sub.1, Q.sub.2 and Q.sub.3.

The operation of the illustrated embodiment of the invention will now be described with reference to FIGS. 3A, 3B, and 3C. If analog input voltage V.sub.in is equal to a reference electric potential V.sub.1 at a connection point between resistors R.sub.6 and R.sub.7, as denoted by reference point .circle.1 in FIG. 3A, then analog input voltage V.sub.in is greater than V.sub.m1, but less than V.sub.m2 and V.sub.m3. Output P.sub.1, representing a comparison between V.sub.in and V.sub.m1, is equal to "1". Output P.sub.2, representing a comparison between V.sub.in and V.sub.m2, is equal to "0", since V.sub.in is less than V.sub.m2. Output P.sub.3 is equal to "0", as V.sub.in is less than V.sub.m3. Reading across the second row of the truth table of FIG. 4, bit D.sub.3 is equal to "0" and bit D.sub.2 is equal to "1" .

FIG. 3B illustrates the circuit of FIG. 3A from which the MOS-FETs Q.sub.11 to Q.sub.43, comparators N.sub.1 to N.sub.3, and encoder ENCN have been eliminated for clarity. Outputs P.sub.1, P.sub.2 and P.sub.3 are also indicated as "1", "0", and "0", respectively.

Referring to the second row of the truth table of FIG. 4, control signal B.sub.1 is equal to "0", control signal B.sub.2 is equal to "1", control signal B.sub.3 is equal to "0", and control signal B.sub.4 is equal to "0". Accordingly, MOS-FETs Q.sub.21, Q.sub.22 and Q.sub.23, indicated in FIG. 3C as switch assembly SW, are turned on to allow the electric potentials at the respective connection points between the adjacent resistors R.sub.8 and R.sub.7, R.sub.7 and R.sub.6, and R.sub.6 and R.sub.5, respectively, to be supplied to the comparators N.sub.1, N.sub.2 and N.sub.3 as voltages V.sub.n1, V.sub.n2, and V.sub.n3. Since input voltage V.sub.in is equal to the electric potential V.sub.1 at point .circle.1 , analog input voltage V.sub.in is less than reference voltage V.sub.n1, is equal to reference voltage V.sub.n2, and is greater than reference voltage V.sub.n3. Accordingly, Q.sub.1 is equal to "0", Q.sub.2 is equal to "1", and Q.sub.3 is equal to "1". Reading across the seventh row of the truth table of FIG. 5, with S.sub.0 equal to "1", bit D.sub.1 is equal to "1" and bit D.sub.0 is equal to "0".

When analog input voltage V.sub.in is equal to electric potential V.sub.1 at point .circle.1 , digital outputs D.sub.3 to D.sub.0 become "0 1 1 0". The electric potential at the point .circle.1 is the electric potential of the sixth step, counting from the ground side, where the ground electric potential is numbered as step zero. The decimal number six is binary number "0 1 1 0", so the digital output "0110" is correct.

By way of a second example, if analog input voltage V.sub.in is equal to an electric potential V.sub.2 at the connection point between resistors R.sub.9 and R.sub.10, as shown, for example, at point .circle.2 in FIG. 3A, electric potential V.sub.2 at point .circle.2 is greater than V.sub.m1 and V.sub.m2, but less than V.sub.m3. Accordingly, output P.sub.1 is equal to "1", output P.sub.2 is equal to "1", and output P.sub.3 is equal to "0". Reading across the third row of the truth table of FIG. 4, bit D.sub.3 is equal to "1" and bit D.sub.2 is equal to "0".

The truth table of FIG. 4 also indicates that control signal B.sub.1 is equal to "0", control signal B.sub.2 is equal to "0", control signal B.sub.3 is equal to "1", and control signal B.sub.4 is equal to "0". Accordingly, only MOS-FETs Q.sub.31, Q.sub.32 and Q.sub.33 are turned on to supply electric potentials at the respective connection points between adjacent resistors R.sub.9 to R.sub.12 to comparators N.sub.1, N.sub.2, N.sub.3. Since input voltage V.sub.in is the same as electric potential V.sub.2 at point .circle.2 , analog input voltage V.sub.in is equal to reference voltage V.sub.n1, but is less than reference voltages V.sub.n2 and V.sub.n3. Q.sub.1 is equal to "1", Q.sub.2 is equal to "0", and Q.sub.3 is equal to "0". From the truth table of FIG. 4, S.sub.0 is equal to "0". The truth table of FIG. 5 indicates in the second row that bit D.sub.1 is equal to "0", and bit D.sub.0 is equal to "1".

When analog input voltage V.sub.in is equal to electric potential V.sub.2, digital outputs D.sub.3 to D.sub.0 become "1 0 0 1". Electric potential V.sub.2 at point .circle.2 is the electric potential of the ninth step, counting from the ground side. The decimal number nine is binary number "1001", indicating that the digital output "1001" is correct.

In the illustrated embodiment of the invention, the voltage derived from each of the four groups of resistors into which resistors R.sub.1 to R.sub.16 are divided is compared with analog input voltage V.sub.in to derive upper bits D.sub.3 and D.sub.2 of the digital output and to select one of such resistor groups. The voltage derived from each resistor of the selected group is compared with analog input voltage V.sub.in to derive lower bits D.sub.1 and D.sub.0 of the digital output. If there are m upper bits and n lower bits of digital output required, the illustrated embodiment of the invention utilizes 2.sup.m -1 upper bit voltage comparators and 2.sup.n -1 lower bit voltage comparators. An analog-to-digital converter according to the present invention thus has far fewer comparators or comparison circuits than the prior art analog-to-digital converter of FIG. 1 which, for m+n bits of output, would require (2.sup.m+n -1) comparators. An analog-to-digital converter in accordance with the present invention can also be produced on a smaller chip which uses lesser amounts of power than the prior art devices.

An analog-to-digital converter in accordance with the present invention eliminates a digital-to-analog converter, as required by the serial-to-parallel analog-to-digital converter of FIG. 2, and any errors which may result therefrom.

When the analog-to-digital converter of the present invention is an integrated circuit, resistors R.sub.1 to R.sub.16 can be formed in a zigzag line on the chip. Resistors R.sub.1 to R.sub.16 occupy only small areas on the chip, so temperature variations have minimal effects upon the circuit elements, thereby contributing to a precision circuit.

Further, when the circuit elements are formed as shown in FIG. 3A, the semiconductor chip is compact. In a preferred embodiment of the present invention, a very compact circuit is produced when the bit ratio of the upper and lower bits is 1, as for example, a bit ratio of 4:4.

When an analog-to-digital converter is formed with resistors R.sub.1 to R.sub.16 in a zigzag pattern, the reference voltage increases from top to bottom, as shown in FIG. 3A, in resistor strings R.sub.1 to R.sub.4 and R.sub.9 to R.sub.12 (hereinafter referred to as group A), and decreases from top to bottom in resistor strings R.sub.5 to R.sub.8 and R.sub.13 to R.sub.16 (hereinafter referred to as group B). Since the reference bias conditions of the resistor strings of group A differ from those of the resistor strings of group B, voltage comparators N.sub.1, N.sub.2 and N.sub.3 should be accordingly interchanged when the different groups are connected by the respective switch assemblies SW. In the illustrated embodiment, outputs Q.sub.1, Q.sub.2 and Q.sub.3 of comparators N.sub.1, N.sub.2 and N.sub.3 are inverted in response to control signal S.sub.0 from upper bit encoder ENCM, rather than physically interchanging comparators N.sub.1, N.sub.2 and N.sub.3. For example, if outputs Q.sub.1, Q.sub.2 and Q.sub.3 equal "1", "0" and "0", they are inverted to be equal to "0", "1" and "1" respectively.

In the above second example in which analog input voltage V.sub.in is equal to an electric potential V.sub.2 at the connection point between resistors R.sub.9 and R.sub.10, as shown at point .circle.2 in FIG. 3A, as described above, upper bit encoder ENCM will generate control signal B.sub.3 equal to "1" to couple resistor string R.sub.9 to R.sub.12 to comparators N.sub.1, N.sub.2 and N.sub.3. Outputs Q.sub.1, Q.sub.2 and Q.sub.3 of comparators N.sub.1, N.sub.2 and N.sub.3 will be equal to "1", "0", and "0", respectively.

However, in the second example, the distance on the integrated circuit chip from resistor R.sub.9 to point .circle.2 is the same as the distance from the resistor R.sub.8 to point .circle.1 of the first example, and the voltage differences are the same. Accordingly, outputs Q.sub.1, Q.sub.2 and Q.sub.3, which are equal to "1", "0", and "0", must be inverted to be equal to "0", "1", and "1". Upper bit encoder ENCM generates control signal S.sub.0 to effect the required inversion.

Since the reference voltages derived from resistors R.sub.1 to R.sub.16 are used to generate digital outputs D.sub.3 to D.sub.0, a monotonic change in input voltage V.sub.in has a corresponding monotonic change in digital outputs D.sub.3 to D.sub.0.

In the embodiment of FIG. 3, the resistor R.sub.16 can be eliminated, and the invention will function as hereinbefore described.

The analog-to-digital converter of the present invention is not limited to the 4 bit analog-to-digital converter of the illustrative embodiment, but can also be applied equally to an 8 or 16 bit analog-to-digital converter.

Although a specific embodiment of the invention has been described in detail herein with reference to the accompanying drawings, it is to understood that the invention is not limited to that precise embodiment, and that various changes and modifications may be effected therein by one skilled in the art without departing from the scope and spirit of the invention as defined in the appended claims.

Claims

1. An analog-to-digital converter for converting an analog input voltage signal to a digital output voltage signal of m upper bits and n lower bits comprising:

a plurality of resistor means connected in a series circuit to a voltage source for establishing respective reference voltages;

upper bit comparators for generating outputs indicative of said m upper bits and having first inputs each receiving said analog input voltage and second inputs each connected to said series circuit at respective intervals defining groups of said resistor means therebetween, each of said groups including a plurality of resistor means;

upper bit encoder means receiving said outputs from said upper bit comparators for generating said m upper bits of said output signal and a switch control signal;

lower bit comparators for generating outputs indicative of said n lower bits and having first inputs each receiving said analog input voltage and second inputs;

switch means associated with each of said groups of said resistor means and being responsive to said switch control signal for selectively connecting each of said second inputs of said lower bit comparators to a respective resistor means in said associated group of resistor means; and

lower bit encoder means receiving said outputs from said lower bit comparators for generating said n lower bits of said digital output signal.

2. The analog-to-digital converter of claim 1; in which said resistor means are arranged in a plurality of rows, with each of said groups constituting one of said rows.

3. The analog-to-digital converter of claim 2; in which said rows of said resistor means are parallel.

4. The analog-to-digital converter of claim 2; in which said rows of said resistor means are arranged in a zigzag pattern.

5. The analog-to-digital converter of claim 1; in which said resistor means are arranged in a zigzag pattern, and said upper bit encoder means generates an inverting control signal; and further comprising means for supplying said inverting control signal to said lower bit encoder means.

6. The analog-to-digital converter of claim 1; in which there are at least 2.sup.m+n -1 resistor means connected in series.

7. The analog-to-digital converter of claim 6; in which there are at least 2.sup.m -1 upper bit comparators.

8. The analog-to-digital converter of claim 7; in which there are at least 2.sup.n -1 lower bit comparators.

9. The analog-to-digital converter of claim 8; in which there are at least 2.sup.m+n -1 switch means.

10. The analog-to-digital converter of claim 9; in which each of said groups of resistor means is 2.sup.n resistor means connected in series.

11. The analog-to-digital converter of claim 10; in which said resistor means are arranged in parallel rows, with each of said groups constituting one of said rows.

12. The analog-to-digital converter of claim 9; in which the number of said upper bit comparators equals the number of said lower bit comparators.

13. The analog to digital converter of claim 1; in which said switch means are metal oxide semiconductor field effect transistors.

14. The analog-to-digital converter of claim 13; in which said resistor means are formed on a semiconductor chip.

15. The analog-to-digital converter of claim 14; in which said resistor means are formed in a zigzag pattern on said semiconductor chip.