Analog to digital switched capacitor converter using a delta sigma modulator having very low power, distortion and noise

Abstract

Power available to a delta sigma modulator is controlled so that relatively high power is provided during one phase of operation, such as during an interval when slewing in a device is expected and relatively low power is provided during another phase. In one implementation, increased power is provided by switching in parallel current mirrors when power demands are expected to be high, whether or not high power is actually needed in a particular interval. A large step size is selected to reduce power corruption and feedback coefficients are optimized for low power by running at a higher oversampling rate than required by signal to quantization noise requirements.

Description

BACKGROUND OF THE INVENTION

Field of the invention

[0005] 1. Technical Field

[0006] The invention relates to analog to digital converters using a delta-sigma modulator and particularly to one having very low distortion and noise where power dissipation is a concern.

Description of Related Art

[0007] Amplifiers are well known in the art. For high precision switched capacitor circuits and ADC's the class A operational amplifier is well suited. A class A amplifier dissipates a constant amount of power independent on the input or output conditions. This is well suited for low-distortion systems, but poor from a power dissipation point-of-view.

[0008] Integrators are also known in the art. Some integrators are passive, in that they are made up of only components such as resistors or capacitors. Other integrators are active, using an amplifier to transfer the signal to an integration element, usually a capacitor. For low distortion, low noise applications, the active integrator is best suited. With CMOS integrated circuits, the switched capacitor integrator, and more generally, the switched capacitor filter is a commonly used circuit. In a switched capacitor circuit, a voltage is sampled on a capacitor in one phase, and the resulting charge is transferred in a second phase. This repeated moving of charge packets results in a current flow. This switched capacitor “branch” behaves much like a resistor when viewed at a low frequency. Its advantage in CMOS integrated circuits include manufacturability and matching to other elements. Delta-sigma modulators are also known which provide a series of binary signals at an output which in a certain frequency range is a digital representation of an input signal.

[0009] Systems for conducting seismic exploration are well known in the art. On land, a plurality of transducers are deployed over a region and configured to receive reflections of acoustic signals from different geophysical layers beneath the surface of the earth. Seismic sensors are connected over cables to signal conditioning, digitization and digital recording equipment. When utilizing a seismic system, a strong acoustic signal is generated by, for example, setting off an explosion or by utilizing an acoustic signal generator having a relatively high power output. Reflections of the acoustic signals from the geographical layers are then received at the seismic sensors deployed over a analysis.

[0010] One problem with seismic exploration is that it frequently occurs in remote areas. As a result, transportation becomes a problem. Such remote areas typically do not have sources of electrical power. Accordingly, when undertaking seismic exploration in a remote area, electric power must be transported in. Whether the transportation occurs by air or by people physically hiking into a rugged area, weight is a significant factor. A common form of power source utilized in seismic exploration makes use of batteries. Batteries are generally heavy. As a result, any power saving that can be achieved results in significantly reduced costs for a particular exploration.

[0011] When seismic exploration is undertaken over water, commonly an array of seismic sensors is towed behind a boat using cables which can extend over a mile in length. Like on land, an acoustic generator is utilized to generate an acoustic impulse, reflections of which occur at geophysical boundaries. Those reflections are detected by the seismic sensors towed behind the boat and recorded, typically, for later analysis. In any seismic environment, it is important to reproduce the captured signals with great precision to insure that the information of interest can be reliably obtained. Like on land, power dissipation is a concern in the marine application. This is because of the problem distributing power over the length of the towed cable.

SUMMARY OF THE INVENTION

[0012] A high performance, low power consumption analog to digital converter is shown which uses a delta-sigma modulator having filter coefficients optimized for reduced power consumption and which uses an amplifier supplied with different levels of power during different operational phases.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] FIG. 1 is a simplified schematic drawing of an amplifier used in accordance with the invention.

[0014] FIG. 2 is a schematic diagram of a switched capacitor integrator using the amplifier of FIG. 1.

[0015] FIG. 3 is a graph showing typical amplifier response to a step change in input.

[0016] FIG. 4 is a graph of current levels available during exemplary phases of amplifier operation.

[0017] FIG. 5 is a schematic diagram of a simple current mirror.

[0018] FIG. 6 is a schematic diagram of a parallel current mirror used during a high power phase of an amplifier's cycle.

[0019] FIG. 7 is a schematic diagram of a preferred control circuit for use with a current mirror in accordance with one aspect of the invention.

[0020] FIG. 8 is a schematic diagram of the control circuit of FIG. 7 controlling a current mirror, such as the high power current mirror of FIG. 6, along with a low power mirror.

[0021] FIG. 9 is a schematic diagram of a portion of control circuit of FIG. 8 showing exemplary current steering.

[0022] FIG. 10 is a block diagram of an analog to one-bit digital converter in accordance with the invention using a delta-sigma modulator.

[0023] FIG. 11 is a schematic diagram of the front end (integrator 1 and its switched capacitor inputs) of the delta-sigma modulator of FIG. 10.

[0024] FIG. 12 is a schematic diagram representing an equivalent model of the comparator of the Δ-Σ modulator of FIG. 3.

[0025] FIG. 13 is a graph showing an amplitude spectrum containing signal and noise in the output of the delta-sigma modulator.

[0026] FIG. 14 is a graph of maximum signal/noise ratio in a delta-sigma modulator as a function of noise shaping cut off frequency.

[0027] FIG. 15 is a graph relating signal to noise ratio at different oversampling rates.

[0028] FIG. 16 is a schematic diagram of a switched capacitor differential front end circuit providing additional power savings.

DETAILED DESCRIPTION OF THE INVENTION

[0029] FIG. 1 is a simplified schematic diagram of the amplifier used in accordance with the invention. The amplifier shown in FIG. 1 is a simplified folded cascode amplifier, fully differential operating class A. The total power dissipated is 4*I*Vdd. The maximum output current is +/−I. All current sources 130, 120, 140, 130′, 120′ and 140′ are switchable current mirrors having a plurality of current states, including a low current state, a nominal state and a high current state as discussed more hereinafter. In addition, current sources 130 and 130′ adjust to maintain common mode level. The construction of current mirrors will be discussed more hereinafter. The input signal to the amplifier of FIG. 1 is applied across terminals 100, 100′ and the output signal is taken across terminals 110 and 110′. In operation, during a slewing phase, the switchable current mirrors are switched into a high current mode. In the settling phase, the switched current sources are operated in an intermediate current mode. In the holding phase, current provided by the current sources is reduced even further.

[0030] FIG. 2 is a single ended representation of a schematic diagram of a switched capacitor integrator using the amplifier of FIG. 1. The input 200 receives an input signal Vin. Input 200 connects to a switched capacitor circuit. A plurality of switches are arranged around the capacitor Cin and are operated so that state 1 switches (those labelled 1) are closed to allow signals through when all state 2 switches (those labelled 2) are open and then, in another state, the state 1 switches are open and the state 2 switches are closed. Considering the capacitor Cin during a first time interval, the state 1 switches will be closed permitting capacitor Cin to charge to the Vin voltage level with reference to a signal ground. In a second state, the state 1 switches are opened and the state 2 switches are closed permitting the voltage charged on the capacitor Cin during a first state to be applied to the negative input of the integrator amplifier and the integrator capacitor Cint. Other arrangements for the switch capacitor are also well known. Among them are reversing the phases described. Using one phase to discharge the capacitor, and the other to charge the capacitor with respect to the amplifier input. A capacitor with one terminal referred to ground, and the other connected to the input in one phase and the amplifier in the other. Also, any of these techniques can be implemented differentially, or with respect to a non grounded reference. These arrangements all result in a similar charge transfer to the amplifier.

[0031] This normally causes charge to flow to or from Cint. When this occurs the op-amp produces an output which restores equilibrium. In an ideal amplifier equilibrium occurs when the negative input of the amp is at the same voltage as the positive input. In the case shown, this is the ground potential.

[0032] In this example, most of the work done by the amplifier occurs when the state 2 switches are initially closed. The op-amp shown has three loads, collectively referred to as CLT, that must be settled to their final values. They are Cpar, parasitic capacitance at the output terminal; Cload, any desired loading at the output; and the series connected capacitors, Cint in series with Cin.

[0033] The thermal noise in an integrator comes from two major sources, namely (1) the input switch capacitor network(s) and (2) the Op-Amp thermal noise.

[0034] Reducing power consumption in a critical amplifier, such as the Op-Amp of an integrator, presents many challenges. Care must be utilized in every aspects in the circuity implemented, whether special or standard, to optimize for minimum power consumption.

[0035] There are three major reasons to dissipate power in an amplifier, namely (1) to increase the device gm for low noise, (2) to increase output current for fast slew, and (3) to increase device gm for faster settling. For the high performance design required for some applications such as seismic sensing applications, very precise settling is desired. Because of the large total load capacitance CLT, the amplifier power requirement is determined by the settling requirements. Power management, as discussed herein, increases the time available for settling. For instance, by increasing the maximum output current during the period where slew is likely to occur, the current in the amplifier during settling can be decreased. This results in a net power savings as discussed more hereinafter.

[0036] In FIG. 2, during phase 1 of the integrator operation, that is, when switches 1 are closed and switches 2 are open, capacitor Cin is charged to some total charge. During phase 2, that is, when switches 2 are closed and switches 1 are opened, a charge Δq is transferred from Cin to Cint. During this charge transfer, the amplifier must be able to supply an output current I in order to achieve an equilibrium state. If the charge from Cin is large enough, the amplifier imbalance will cause it to output the maximum available current, as set by the amplifier bias condition. This condition is known as slew.

[0037] Work done in the slew interval is not dependent on the time taken to slew. 1$\begin{array}{cc}W=\frac{I·V·t_{\mathrm{slew}}}{2}=\frac{q}{t_{\mathrm{slew}}}·\frac{V}{2}·t_{\mathrm{slew}}=C\frac{V^2}{2}.& \left(1\right)\end{array}$

[0038] where C is Cin, and V is Vin.

[0039] Similarly, for a given input, the average power (in period T) required for slew is not dependent on Tslew. The power required is: 2$\begin{array}{cc}P=\frac{W}{T}=\frac{{\mathrm{CV}}^2}{2T}& \left(2\right)\end{array}$

[0040] However, the power required for settling is dependent on the time given to settle. The settling waveform is a negative exponential in which the remaining error voltage, that is the difference between the amplifier actual output voltage and its ideal settled voltage, as a function of time, is stated as:

V e (t)=Vie−t(gm/CLT)  (3)

[0041] where V1 is proportional to the charge transferred.

[0042] Thus, the error voltage can be reduced by either increasing the settling time t or by increasing gm of the amplifier device. gm of a MOSFET device, in strong inversion is proportional to the square root of the current flowing through it. gm of a MOSFET in weak inversion, and of a bipolar device is proportional to the current (I) in the device. To meet the design targets in accordance with the invention, to have a small enough error voltage, Ve, one requires a time of >10 τ to settle, where τ is calculated as follows for a MOSFET in strong inversion: 3$\begin{array}{cc}\tau =C_{\mathrm{total}\mathrm{load}}/g_m=C_{\mathrm{LT}}/\sqrt{2K\left(\frac{w}{l}\right)I}& \left(4\right)\end{array}$

[0043] Referring to FIG. 2, for a MOSFET amplifier, the equation governing settling, restated is:

V e (t)=Vie−t.{square root}{square root over (2K{fraction (W/L)})}I/CLT  (5)

[0044] Applying this concept in accordance with the invention, we can increase the current in the portion of the cycle where we expect slew. This has no net power penalty. The slew is completed in a time proportional to the current. By completing the slew faster, we allow more time for settling, and can run the amplifier at a reduced gm. Since accurate settling is often the deciding factor in amplifier power, there is a significant net power savings.

[0045] An additional savings is achieved by a further reduction of power of the amplifier after the slew/settling phase is complete. After the slew and settling phases are complete, the amplifier no longer integrates incoming signal charge on the integration capacitor. The negative input of the amplifier has been returned to the equilibrium value, which differs from some reference value by only non-idealities. In this hold phase, the amplifier non-idealities do not have a significant effect, and the performance of the amplifier can be modified to save power.

[0046] The reason that noise and offset caused by the amplifier in the hold phase are less relevant in some applications can be seen by looking at the amplifier output voltage. In an ideal case, the terminal of Cint connected to the amplifier is at the same voltage as the non-inverting terminal. For this example, one assumes 0 volts, or ground. The integration capacitor has a voltage across it that is the integral of the input(s), and the output voltage is this integral.

[0047] If the amplifier has non-idealities, such as noise, the input connected to Cint is not at ground, but at some noise voltage Vn. This means the output differs from the proper value by this voltage Vn. Clearly, the noise adds to the output value, and at low frequencies, where the signal band is located, an integrator often has a very large amount of gain. It would take a very small input signal, to correct for the error Vn which means it is not a significant noise contribution. For this reason, where the amplifier does not have to transfer charge or settle the input(s), we can reduce the power in the amplifier. By contrast, when signal is being settled, any noise Vn results in a final noise charge not being delivered from the input(s). In this phase, the input referred noise is Vn.

[0048] When reducing power during a hold phase, adequate power must remain to settle any activity that can occur in the phase. In the case of a Δ-Σ modulator, such as one described hereinafter, the second integrator switched capacitor input samples a first integrator's output. However, this sampling cap is much smaller than integrator 1's input capacitors, and the disturbance is negligible. In this phase, a 4:1 reduction creates no problems.

[0049] There is another savings in power in the hold phase. The large integrator input capacitors are not connected to the amplifier in this phase. The amp does not have to settle this capacitance, meaning less power is required to settle any disturbances in this phase. This assumes that any loads switched to the output of integrator 1 are small compared to integrator 1's input capacitors.

[0050] FIG. 3 is a graph showing typical amplifier response to a step change. When a signal on the input of the amplifier output changes from a first level V1 to a second level V2, the output to the amplifier changes in a manner represented in the graph of FIG. 3. With the input of the amplifier at V1, the output of the amplifier will substantially be that shown at the portion of the curve 300. When the input signal changes substantially simultaneously from V1 to a different value V2, the output of the amplifier will begin to change to restore equilibrium. Equilibrium is eventually restored as shown at portion of the curve 330. In between portions of the output curve 300 and 330 there are essentially two areas of interest, namely a slewing portion 310 and a settling portion 320. During the slewing portion of the curve 310, the input conditions on the amplifier cause the amplifier to provide (or sink) its maximum current. This current transfers charge to the integration capacitor, eventually restoring the inputs to the equilibrium condition, and reducing the output current. The amplifier will output (or sink) the maximum current until the inputs are very near each other in voltage, and linear settling takes place. In slew, output current is maximum, either sourced or sinked.

[0051] The class A amplifier, without power management, consumes the same power whether slewing, settling or holding its value. In accordance with the invention, this power changes according to the operational phase (expected activity); not according to the signal.

[0052] In accordance with the invention, in a preferred form, current provided to the amplifier during a slew phase is N times that provided during a settling phase, where N=4 in the examples discussed herein. The current provided to the amplifier during a hold phase is reduced to one quarter of that provided during the settling phase. How this is done is discussed more hereinafter.

[0053] FIG. 4 is a graph of current levels available during exemplary phases of amplifier operation. In a clocked system, certain changes occur, if at all, during pre-defined portions of the clock cycle. In accordance with the invention, the current available to the amplifier changes based on the expected activity that could occur during an operational phase. For example, in FIG. 4, during a slew interval, the current provided to the amplifier is, in this case, four times that provided during the settling phase. That current is available to the amplifier, whether or not a signal actually exists on the input which would cause the amplifier to slew. Similarly, the current available during the settle interval is available, whether or not a transition has occurred during the slew interval which would require settling. Thus the current and therefore the power available to an amplifier varies as a function of expected activity whether or not actual activity occurs during that interval. During a hold phase, very little current is required and so the current provided to the amplifier during a hold phase is reduced yet further. In the examples shown in FIG. 4, a current I is provided during the settle phase, a current 4I is provided during the slew phase and a current I÷4 is provided during the hold phase. These ratios can be adjusted depending on a particular application.

[0054] FIG. 5 is a schematic diagram of a simple current mirror. The current sources shown in FIG. 1 are current mirrors such as shown in FIG. 5. As shown in FIG. 5, one can increase the output current by increasing the reference current Iref. However, this causes head-room problems. Head room refers to the minimum voltage across a current source required for proper functioning. One could increase the width of the output device M2 (W2) by switching in a parallel output device, but this would cause settling problems and timing problems with other mirrors. One can also decrease the output current by decreasing Iref, or switching out parallel devices.

[0055] FIG. 6 is a schematic diagram of parallel current mirrors used during a high power phase of an amplifiers operational cycle. Rather than disturbing the low power mirror, one can simply turn on another mirror in parallel during a high power phase. This results in the least disturbance to the amplifier in the lower power phases, since the high power mirror is off, and the lower power mirror can be optimized for the critical settling phase, specifically to contribute minimum noise and to settle any glitches quickly.

[0056] FIG. 6 shows a current mirror comprising devices M1 and M2 together with a second current mirror comprising devices M3 and M4. Note that although the low current mirror shown on the right provides a contribution to Iout based on Iref, the high powered mirror on the left provides a contribution to Iout based on n.Iref. The switch P shown in FIG. 6 indicates that the high power current mirror selectively is switched on or off. When high power is expected to be required in amplifiers, such as during an expected slewing phase, the switch P is closed and both current mirrors provide current to the amplifier in a high power mode. When high power is not required, such as during the settling phase, and/or during the holding phase, the switch P will be opened and amplifier is supplied by only the right current mirror M1 and M2.

[0057] The implementation shown in FIG. 6 has many problems. Problems occur mostly at turn on/off. First, if the current in M3 is turned fully off, the gate voltage is not controlled, and some undefined current can flow in M4. A small current could remain in M3, but then the gm will be very weak for the amount of gate capacitance, and control of the gate node will be very slow. Also, with a small amount of current in M3, M4 will contribute to the bias currents in the amplifier. This means that the high power circuits would have to be designed to not adversely affect the amplifier, especially with noise. Secondly, the gate node could be controlled with a pull down resistor or transistor. This causes its own problems. First timing of switches is more difficult depending on the arrangement. Secondly, un-acceptable delay, since upon turn-on, the node would have to be changed over a significant voltage range from the pulled-down state. It is preferred to utilize the control circuit shown in FIG. 7 for activating a parallel current mirror in high power mode.

[0058] In FIG. 7, device M4 corresponds generally to device M4 of FIG. 6. The bias line 610 shown in FIG. 7 corresponds to bias line 610 of FIG. 6. Current source IR of FIG. 7, corresponds generally to current source nIref of FIG. 6. The bias line control circuit shown in the dashed box of FIG. 7 controls the bias line 610 without the adverse effects previously described. Control of current in M4 of FIG. 7 is accomplished by a small change in current IR. This method used to charge IR will be presented following explanation of the control circuit.

[0059] Consider the circuit of FIG. 7. IR takes on two values. When M4 should act as a current source, IR=Iconstant, also referred to as IC. When M4 should be off, IR is reduced. These two states are referred to as IR high state and IR low state, respectively. Device M7 provides a consistent high gm controlling the bias line to output device M4. The voltage Vgs6 is equal to Vgs7 when current IR is in a high state. However, Vgs6<Vgs7 when IR is low. This guarantees shutdown. Vgs5 defines Vgs4 when IR is high. Vgs5 does not have to match Vgs6 or Vgs7, however to simplify discussion, devices M5, M6, M7 are assumed to match.

[0060] To explain why a small change in IR makes a complete shutdown:

[0061] Assume M5=M6=M7. IR has a high state, where IR=Ic, and a low state, IR=Ic/4.

[0062] Consider a loop

V out =V gs5 +V gs6 −V gs7

[0063] When IR=Ic, all Vgs's match, and

V out =V gs1 =V T +ΔV H .

[0064] The gate of M4 has this voltage, and will conduct well because it is turned on by an amount ΔVH in excess of threshold voltage, VT.

[0065] ΔV is: 4$\Delta V=\sqrt{\frac{2}{K^{\prime }}\frac{L}{W}{I}_D}$

[0066] In the low state, with 5$I_R=\frac{1}{4}{I}_c$

V out =2VT+2ΔVL−(VT+ΔVH)

V out =V T +2ΔVL−ΔVH

[0067] 6 $$ V out = V T + 2 ⁢ 2 K ′ ⁢ L W ⁢ I c 4 - 2 K ′ ⁢ L W ⁢ I C 7 $$ V out = V T + 2 K ′ ⁢ L W ⁢ I C - 2 K ′ ⁢ L W ⁢ I C

[0068] Now, M4 does not conduct because there is no ΔV above VT. With a greater than 4:1 ratio, Vout would drop below VT, assuring shutdown. In a preferred implementation, a ratio of 10:1 is used.

[0069] Current IC and IR as well as the devices discussed could be scaled without affecting the performance.

[0070] Thus a simple very effective technique for controlling a current source may be achieved by steering currents away from M5. (A ratio of approximately 10 to 1 in current reaching M5 is more than enough to get 1000:1 ratio in output current between the on and off states.)

[0071] When comparing a similar amplifier without the power management just described with an amplifier which has slew and settling power management, one can see some striking improvements.

		Without
	With	(conventional)
	% of time in Slew	30		53
	Tail current while slewing	2500	uA	1450	uA
	Tail current while settling	660	uA	1450	uA
	Current ratio	3.8:1		1:1
	Power	11.7	mW	18.2	mW

[0072] The 11.7 mW consumed by a device using power management described herein, represents a 35% savings in power over the 18.2 mW which would be consumed without power management in a similar configuration.

[0073] FIG. 8 is a schematic diagram of the control circuit of FIG. 7 used as a high power current mirror, in parallel with a constant current mirror. The circuitry to the right of the dashed line in FIG. 8 corresponds to the same in FIG. 6. The circuitry to the left of the dashed line in FIG. 8 replaces the switched mirror to the left of the dashed line in FIG. 6. As discussed above, a change in current IR (in FIG. 8) results in turning on or off the current contribution from device M4 to the output current. Control of the switching current IR is described more in conjunction with FIG. 9.

[0074] FIG. 9 is a schematic diagram of a portion of control circuit of FIG. 8 showing exemplary current steering. This is a circuit that implements IR of FIG. 8. As shown, the output current varies 10:1. Io is a constant reference circuit. M1 and M2 match, while M3 is one tenth the width/length. The current in M2 is Io, and in M3 is Io/10. P is a control signal that will steer either Io or Io/10 into device M8, which is mirrored in device M9 as the output current. All device sizes and current levels are for illustration and could be changed as needed. pb is the complement of p.

[0075] When p is high, pb is low, M5 and M6 are conducting. M4 and M7 are not conducting. M2's Io will flow through M5 and M8. Io/10 from M3 will be sourced from the supply. Io will be mirrored by M9. When pb is high, M2's current Io is sourced from the supply. M2's current Io/10 is sourced through M7 and M8, resulting in Io/10 being mirrored out with M9.

[0076] In the hold phase, reduction of the current can be performed over a limited range by simply adjusting IR in FIG. 6. This is because headroom is not a problem when reducing current levels. The current steering circuit of FIG. 9 is used to implement the current reduction in the hold phase. For the hold phase, the transistors are sized to give current Io and Io/4, and transistor M9 of FIG. 6 replaces source Iref of FIG. 6. A control circuit similar to that of FIG. 7 could have been used for the hold phase current reduction, but was not needed.

[0077] The circuit is slightly simplified in that cascade devices not relevant are not shown.

[0078] Another power savings comes from maximizing the output step size in the switched capacitor integrator, by reducing Cint. Though this places added difficulty on the amplifier design, the power savings is significant. The reduction in Cint results in a proportional reduction of parasitics associated with Cint. The parasitic of Cint is often a significant component of total load capacitance CLT.

[0079] Looking at equation (4), for a given time constant τ, if CLT is reduced by a factor of two, the current through a MOSFET in strong inversion could be reduced by a factor of 4. The term Vi is proportional to the charge to be transferred. The increased step size may increase the voltage Vi. However, since the ideal settle voltage has been increased, larger error Ve(t) is acceptable. As mentioned earlier, such a switched capacitor integrator is often used in a Δ-Σ modulator. Each integrator in FIG. 10 can be a switched capacitor integrator as described, with the step size maximized. Similar savings would result for stages whose gm is governed by other equations, such as the MOSFET in weak inversion, or the bipolar device.

[0080] FIG. 16 is a schematic diagram of a switched capacitor differential front end circuit providing additional power savings. A cross coupled input structure is used to boost the signal charge integrated in each cycle. In phase p1, CinA is charged to voltage Vin+−VCM. In phase p2, CinA is connected between the amplifier (inputs at approximately VCM) and Vin-. The final voltage on the cap at the end of phase p2 is Vin-−VCM. The total charge transferred to CintA is:

Q=CV

Q p1 =C inA (Vin+−Vcm)

Q p2 =C inA (Vin-−Vcm)

Q total A =Q p1 −Q p2 =C inA (Vin+−Vcm−Vin-+Vcm)

Q total A =C inA (Vin+−Vin-)

[0081] If Vin is balanced around Vcm, then Vin+=−Vin-, so

Q total A =C inA ·2Vin+

[0082] Likewise, CinB delivers

Q total B =C inB ·2Vin-

[0083] By using a cross coupled input, through switched S1 and S2, we double the delivered charge. In a non-cross coupled circuit, these switches would connect the capacitors to VCM. The power savings arises because in a non-cross coupled circuit, CinA and CinB would have to be larger to deliver the same charged. CinA and CinB increase the loading on the amplifier, and would require more power to settle.

[0084] FIG. 10 is a block diagram of a Δ-Σ modulator used to digitize the incoming signal. The incoming signal is applied at input 1000 (Ain) and the analog incoming signal is applied to one input of subtraction circuit 1010. Subtraction 1010 receives as the other input, the output of comparator 1080. The output of subtraction of circuit 1010 is integrated with a series of cascaded integration circuits 1020, 1030, 1040 and 1050. The output of each integrator is applied, using a respective weighing coefficients, a1, a2, a3 and a4 to a summing circuit 1060 where the values of the signals are summed. The Δ-Σ modulator operates at a sampling rate fs, and in each cycle, the summed value is compared to some threshold value. If the output of summing circuit 1060 is greater than a threshold value, a digital pulse is applied to output 1090 as well as to a subtraction input of subtraction circuit 1010. If the output of the summing circuit 1060 is less than the threshold, then no digital output will be produced. These comparisons occur at a sampling rate as discussed more hereinafter. At low frequencies, the noise at output 1090 is dominated by thermal noise, usually generated in the front end, 1000, 1010, 1020 and 1095. At higher frequencies, the noise is dominated by the quantization introduced by the comparator 1080. The output D is a digital representation of Ain. D is a 1-bit stream at a rate fs, and contains two levels. In other “multi-bit” modulators, D is a multi-bit signal at rate fs, representing a multi level comparison.

[0085] The Δ-Σ modulator is oversampled, meaning that the data rate is much greater than the minimum required to sample accurately the input signal Ain (greater than the Nyquist rate). The data at D, viewed in the frequency domain can be described over a range from 0 to Fs/2 (FIG. 13). The signal band is at the lower frequency end. In the signal band, a low amount of quantization noise is required. The rest of the spectrum of the Δ-Σ modulator output contain large amounts of quantization noise, which will be removed by a digital filter. The digital filter will often reduce the sample rate to the much lower Nyquist rate.

[0086] In a low noise Δ-Σ ADC (with a large oversampling ratio), the in-band quantization noise will usually be insignificant when compared to the thermal noise produced by the analog circuits. Further, the noise is dominated by the front end (1000, 1010, 1020, 1095) thermal noise. The coefficients a1, a2, a3 and a4 produce the quantization noise shaping and are selected, as discussed more hereinafter, to contribute to reduced power consumption in a unique way. A resonator b (1070) may be used to help reduce the quantization noise in the signal-band. Using the design described above, less than 12 mW of power is consumed in integrator 1 (1020).

[0087] FIG. 11 is a simplified schematic diagram of the front end (integrator 1 and the switched capacitor input branches) of the delta-sigma modulator of FIG. 10. FIG. 11 is very similar to FIG. 2, differing in the existence of a second input. Input line 1105 corresponds to the subtraction input to subtraction circuit 1010 of FIG. 10. It receives, as feedback, the complement from the comparator 1080 having a logic value {overscore (D)}. The analog input comes from line 1000 of FIG. 10. The switched capacitor operation is substantially that described above in conjunction with FIG. 2. However, from the feedback input 1105, the polarity of the charge is controlled by the logic value of the feedback signal {overscore (D)}. By using the complement, we implement subtraction. Thus the inputs to the integrator function as the subtraction circuit 1010 shown in FIG. 10 as well as serving as an input to the integrator.

[0088] Returning to FIG. 10, each of the feedback coefficients a1, a2, a3 and a4 are selected to optimize low power consumption in the Δ-Σ modulator. The Δ-Σ modulator is deliberately operated at a higher sampling rate than would ordinarily be used so that the coefficients can be optimized for power minimization. Although the discussion of the coefficients which follows applies to any higher order modulator, the fourth order modulator shown in FIG. 10 will be utilized as an example.

[0089] FIG. 12 is a schematic diagram representing an equivalent model of the comparator of the Δ-Σ modulator shown in FIG. 11. The input E(z) is the white noise useful in modeling the 1-bit quantization noise resulting from a busy digital input signal. White noise has an even energy distribution across frequency.

[0090] Being 1-bit, E(z) is large. However, over sampling (running at a much greater frequency than the minimum sampling frequency, i.e. the Nyquist frequency) spreads this noise over a larger frequency range. Also, feedback loop has the effect of reducing the quantization noise at the low frequency end where the signal is found. Noise increases to a maximum at half the sample rate. This high frequency noise can be removed by a digital filter.

[0091] FIG. 13 is a graph showing a typical spectrum containing signal and noise in the output of a Δ-Σ modulator. FIG. 13 shows that the quantization noise in the band (up to fb) is low but not zero.

[0092] The strength of value of the coefficient a1, a2, a3 and a4 (FIG. 3) determine noise shaping. The set of coefficients was determined to give a Butterworth shape to the quantization noise model; that is, to the white noise spectrum. This can be done several ways, however, one way was disclosed in the masters thesis of co-inventor Wei Lee from Massachusetts Institute of Technology in 1987. Though the Butterworth equation was used to determine the noise shaping, other methods are also applicable to the technique to reduce power described. Common methods include other filter types (Elliptical, Chebyshev, etc.) as well as random generation and evaluation of coefficients. A method to reduce the power through coefficient selection at an increased sample rate will be described for the Butterworth filter analysis.

[0093] A higher cut-off frequency results in stronger attenuation of the in-band low frequency noise. However, this compromises the stability of the modulator resulting in lower maximum input.

[0094] FIG. 14 is a graph of a signal/noise ratio as a function of Butterworth filter cut off frequency ωc. At the low end of the curve shown in FIG. 14, there is not enough noise pushed out of the signal band and the signal/noise ratio is bad. At the high end of the curve, the noise is greatly reduced; however, stability of the modulator is reduced and only a small signal can be used, resulting in a poor signal to noise ratio. There is, thus, a maximum on the curve shown in FIG. 14 which is optimum from a signal to noise ratio perspective. This is where traditional design principles would suggest operating.

[0095] Contrary to the traditional approach, to conserve power in accordance with the invention, the modulator is run in the portion of the curve of FIG. 14 in which the stability is greatest, namely to the left side of the maximum S/N shown in the graph. This permits one to have the largest signal component compared to the feedback strength. The savings in power comes from two places. First, the larger signal overcomes the thermal noise of the front end. Secondly, the thermal noise of the feedback switched capacitor (or equivalent resistor) network is less relevant. In accordance with the invention, the 4th order modulator is run at higher than the oversampled rate required for a given S/N, so that a set of coefficients could be selected to the left of the maximum shown in FIG. 14. This technique is applicable to the other methods mentioned, including the random generation and evaluation of coefficients. In all cases, a curve similar to FIG. 14 could be produced.

[0096] FIG. 15 is a graph used in describing power savings achieved for a given signal to noise ratio as a result of selecting sampling rates in a unique manner. FIG. 15 compares the fourth order modulator of FIG. 10 run at two sample rates and compares the operating points that could have been used. As shown in FIG. 14, assuming that T is the minimum required signal to noise ratio, at a sampling rate Fs, the coefficient would have to be chosen near the optimum for signal to noise ratio, which is not good from a power consumption point of view. By running at a higher sample rate, in accordance with the invention, one can easily meet the signal to noise specification while simultaneously choosing coefficients near the optimum for power savings.

[0097] The modulator noise shaping equation used for the previous plots came from: 8$Y\left(z\right)\left[\frac{a_1}{Z-1}+\frac{a_2}{{\left(Z-1\right)}^2}+\frac{a_3}{{\left(Z-1\right)}^3}+\frac{a_4}{{\left(Z-1\right)}^4}\right]+E\left(z\right)=Y\left(z\right)$$Y\left(Z\right)\left[1+\frac{a_1}{Z-1}+\frac{a_2}{{\left(Z-1\right)}^2}+\frac{a_3}{{\left(Z-1\right)}^3}+\frac{a_4}{{\left(Z-1\right)}^4}\right]=E\left(z\right)$$\frac{Y\left(Z\right)}{E\left(Z\right)}=\frac{1}{1+\frac{a_1}{Z-1}+\frac{a_2}{{\left(Z-1\right)}^2}+\frac{a_3}{{\left(Z-1\right)}^3}+\frac{a_4}{{\left(Z-1\right)}^4}}$

[0098] This becomes: 9$\frac{1-4Z^{-1}+6Z^{-2}-4Z^{-3}+Z^{-4}}{\begin{array}{c}1+\left(a_1-4\right)Z^{-1}+\left(6-3a-1+4_2\right)Z^{-2}+\\ \left(3a_1-2a_2+a_3-4\right)Z^{-3}+\left(1-a_1+a_2-a_3+a_4\right)Z^{-4}\end{array}}$

[0099] Y(z)/E(z)=He(z) represents the quantization noise at the output and describes the noise shape function. The form of the denominator is in the same form as a Butterworth filter. A program called Matlab was used to generate Butterworth filters of different cutoffs (ωc). The coefficients of these filters (terms multiplying z−1, z−2, z−3 and z−4) were used to find the modulator coefficients, a1, a2, a3 and a4. For each set, the signal to noise ratio and the maximum input for stable operation was found, to select the modulator used.

[0100] The combination of techniques described herein can save a significant amount of power. The cross coupled input structure boosting the effective signal is estimated to result in a 30% power savings over that which would occur without the input structure. The use of power management is estimated to result in approximately a 35% savings in power over that which would be available if the power management were not implemented. Increasing the maximum integrator step size is estimated to achieve a 25% power savings over that which would occur if the size were not increased. Finally, selection of the modulator coefficients as discussed is estimated to result in a 20% power savings over that which would have been achieved if the selection were not done in a manner described.

[0101] In this manner, one can achieve significant power savings. This has great practical application in a variety of fields, but particular in the field of seismic sensing.

[0102] Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation. For example, a variable power source can be implemented as a current source or as a voltage source. The spirit and scope of the present invention being limited only by the terms of the appended claims and their equivalents.

Claims

1. An analog to digital converter, comprising: a. an analog input; b. a combination circuit connected to said analog input; c. an integrator receiving the output of the combination circuit, and having a plurality of stages with at least one stage having different power levels available during respective operational phases; d. a summing circuit receiving a weighted outputs from at least two of said stages and producing a summed output; and e. a comparator receiving said summed output and, when said summed output exceeds a certain threshold value, providing a digital output signal to an output and to said combination circuit.

2. The analog to digital converter of claim 1 in which said integrator comprises a plurality of series connected stages with at least one stage having said combination circuit as an input circuit and said combination circuit comprises: a switched capacitor input circuit; and a feedback input.

3. The analog to digital circuit of claim 2 in which at least one stage of said integrator comprises an amplifier circuit having a capacitor connected between an output and one input of said amplifier circuit.

4. The analog to digital circuit of claim 3 in which said switched capacitor input circuit and said feedback input are connected to said capacitor and said one input.

5. The analog to digital circuit of claim 3 in which said amplifier circuit comprises a power control circuit configured to provide high power to an active element during at least one portion of an amplifier's operational cycle and to provide low power otherwise.

6. The analog to digital circuit of claim 5 in which said power control circuit comprises two current mirrors in parallel.

7. The analog to digital circuit of claim 6 in which one of said current mirrors is larger in capacity than the other.

8. The analog to digital circuit of claim 5 in which one of said current mirrors is selectively activated only during said portion of an operational cycle.

9. The analog to digital circuit of claim 8 in which said portion of an operational cycle comprises at least part of a slewing phase.

10. The analog to digital circuit of claim 5 in which said amplifier circuit comprises an amplifier having an input receiving a digital signal; an active element receiving said signal from said input; and a power control circuit having two output levels connected to said active element and selectively providing one of said levels to said element only during a portion of its operating time.

11. The analog to digital circuit of claim 5 in which said amplifier circuit comprises two current sources and an active element, connected to said current sources so that only one current source is active during an operational phase when power requirements are relatively low and so that both current sources are active during an operational phase when power requirements are relatively high.

12. The analog to digital circuit of claim 5 in which said amplifier circuit includes a control circuit comprising: a. a first current source connected in series with a first active device and a second active device, with each active device having a gate terminal; b. a second constant current source connected in series with a third active device and a fourth active device, each active device having a gate terminal, with the gates of said third active device and said second active device connected together; and c. an output device having a gate terminal connected to the junction of said second current source and said third active device and controlled thereby.

13. The analog to digital circuit of claim 1 in which the step size of the digital output applied to said combination circuit is optimized to conserve power.

14. An analog to digital converter comprising: a. an analog signal input; b. a delta modulator receiving said analog signal input, said delta modulator sampling said analog signal input at a rate substantially in excess of the Nyquist rate, and c. a multistage integrator, in which weighted values of outputs of stages of said multistage integrator are combined to form a feedback signal, in which said feedback signal is combined with a signal from said analog signal input, in which power is provided to said delta modulator in a high power during slewing and in a low power mode at other times.

15. A method of operating an analog to digital converter, comprising the steps of: a. oversampling the analog input signal to produce an oversampled digital output signal, b. applying the oversampled digital output signal to a multistage integrator, c. weighing a signal output from each stage of said multistage integrator to form a feedback signal and combining the feedback signal with the analog input signal and controlling power to at least one stage of said multistage integrator to increase power during less than all of its operation cycle.

16. A method of providing power to a clocked analog to digital converter comprising the step of: providing different power levels to said analog to digital converter during at least two respective time intervals separated by one or more clock signals.

17. A method of controlling current to an analog to digital converter, comprising the step of: during an operational phase when slew is expected, increasing current available to the analog to digital converter irrespective of actual signal level applied to the analog to digital converter.

18. A method of controlling current to an integrator, comprising the step of: decreasing current available to the analog to digital converter during an operational phase when little activity is expected.

19. A method of providing power to an analog to digital converter comprising the steps of: using two current mirrors to provide power to at least one element of the analog to digital converter; and switching one current mirror in or out to control power to the analog to digital converter without adversely affecting the integrator.

20. A method for saving power in a delta sigma modulator, comprising the step of: running at a greater oversampling rate than required by signal to quantization noise requirements.

21. A method for saving power in a delta sigma modulator, comprising the step of: optimizing feedback coefficients from an integrating circuit for reduced power consumption.

22. A method for saving power in a delta sigma modulator, comprising the step of: controlling power to a switched capacitor circuit commensurate with activity expected during an operational phase.

23. A method for saving power in a delta sigma modulator, comprising the step of: maximizing the step size of the delta sigma modulator for power consumption savings.

24. An integrated circuit, comprising a delta sigma modulator having one or more of: a. at least one stage having different power levels available during respective operational phases; b. a greater oversampling rate than required by signal to quantization noise requirements; c. feedback coefficients from an integrating circuit optimized for reduced power consumption; and d. step size maximized for power consumption savings.