AND-gate clock

Abstract

An AND-gate clock having an input stage, an output stage, and an isolation stage. The input stage receives two signals, and gates them to produce a high signal. The output stage is used to drive a load typically having a large load capacitance when both signals are true. The isolation stage isolates the input stage from the output stage when only one signal is true, therefore preventing power dissipation by current flow through the output driver stage. The isolation stage provides an alternative current path through smaller transistors, thereby incurring lesser power dissipation and requiring less layout area. A small driver stage may then be used.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to metal oxide semiconductor technology and in particular to AND-gate clocks.

2. Description of the Prior Art

The AND-ing of two or more inputs in a dynamic MOS clock circuit has been a particularly difficult problem, primarily because of the large transistor sizes involved and the high power dissipated before the clock is triggered. Previously, signals were ANDed in a dynamic clock as shown in FIG. 1. In this circuit the transistors T.sub.10 and T.sub.11 form an output stage wherein T.sub.10 is the driving transistor. In this circuit, the output .phi..sub.3 is conditional upon both .phi..sub.1 and .phi..sub.2 being high. The problems occur when .phi..sub.1 occurs earlier than .phi..sub.2, since the node N.sub.5 goes high while the Node N.sub.2 remains high. In order to prevent .phi..sub.3 from rising during this time, transistor T.sub.11 is typically much larger than the transistor T.sub.10. However, the driving transistor, T.sub.10, must be very large in order to handle the capacitance C.sub.L. Thus, T.sub.11 becomes very large, as much as approximately 700 microns in channel length for T.sub.10 =100 microns. Also, during the time that .phi..sub.2 remains low, a large amount of current flows through T.sub.10 and T.sub.11.

SUMMARY OF THE INVENTION

The present invention allows .phi..sub.1 to occur earlier than .phi..sub.2. However, in this circuit, the gate of T.sub.10 remains low, holding T.sub.10 off. The additional power dissipated during this time is only the current flowing through an additional depletion transistor and a drain transistor. This can be kept small, since the capacitive load on the gate of T.sub.10 is only that associated with the driving transistor T.sub.10, typically a small fraction of C.sub.L. Also, the transistor T.sub.11 can now be made equal or even smaller than T.sub.10, since T.sub.10 is now turned off. Finally, when the second output does go high, a full bootstrap voltage will appear on the input to the driving transistor, since the drain transistor will be turned off and the gate of the depletion transistor will be at the supply voltage. Therefore, considerable savings in power dissipation and layout area are achieved.

DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a prior art AND-gate clock;

FIG. 2 is a schematic diagram of one embodiment of the invention; and

FIG. 3 is a clock diagram for use in connection with the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now to FIG. 2, a preferred embodiment of the invention, an AND-gate clock, is generally indicated by reference numeral 10. The AND-gate clock 10 is generally made up of stages shown by the broken blocks 12, 14 and 16. Block 12 includes an input stage, Block 14 includes an isolation stage, and Block 16 includes an output stage.

Looking to the input stage 12, a first transistor T.sub.1 is shown with its source grounded and its gate tied to a precharge signal. A second transistor, T.sub.2, has its source connected to the drain of the transistor T.sub.1, forming a node 1, N.sub.1. The transistor T.sub.2 receives a first signal, .phi..sub.1, at its gate, and a second signal, .phi..sub.2, at its drain. A third transistor, T.sub.3, has its source grounded and its gate tied to the node, N.sub.1. The drain of the transistor T.sub.3 is tied to the source of a transistor, T.sub.4, forming a node N.sub.2. The gate of the transistor T.sub.4 is tied to a precharge signal while the drain is connected to a supply voltage, V.sub.cc. A fifth transistor, T.sub.5, has its source tied to the node N.sub.2 and its gate connected to the supply voltage V.sub.cc. The drain of the transistor T.sub.5 is tied to the gate of a sixth transistor, T.sub.6. The sixth transistor, T.sub.6, has its drain tied to the input first signal, .phi..sub.1. A seventh transistor, T.sub.7, has its source grounded and its gate tied to the node N.sub.2. The drain of T.sub.7 is connected to the source of an eighth transistor, T.sub.8, whose gate is tied to the source of T.sub.6. The drain of the eighth transistor, T.sub.8, is tied to supply voltage V.sub.cc . Finally, a capacitance C.sub.1 is connected between the source of the transistor T.sub.8 at the node N.sub.4 and the gate of the transistor T.sub.8 at node N.sub.5.

The isolation stage 14 includes two transistors, T.sub.9 and D.sub.1. D.sub.1 is a depletion transistor. The transistor T.sub.9 has its source connected to the node N.sub.4 and its gate connected to the node N.sub.2. The drain of the transistor T.sub.9 is tied to node N.sub.6 to which the source of the transistor D.sub.1 is also tied. The drain of the transistor D.sub.1 is tied to the node N.sub.5 and its gate is tied to the node N.sub.4.

The output stage is a driver circuit composed of transistors T.sub.10 and T.sub.11. T.sub.10 is a driver transistor with its gate connected to the node N.sub.6 and its drain connected to supply voltage V.sub.cc. The source of the transistor T.sub.10 is tied to a node N.sub.7 which forms an output .phi..sub.3. The transistor T.sub.11 has its source grounded and its gate connected to the node N.sub.2. The drain of the transistor T.sub.11 is connected to the node N.sub.7. A load capacitance is represented by the capacitor C.sub.L connected at the output N.sub.7.

The operation of the AND-gate clock 10 may now be observed by referring to the timing diagram of FIG. 3. During precharge, .phi..sub.1 and .phi..sub.2 will be at zero volts and the precharge signal will be at a voltage level, typically V.sub.cc. In this manner the transistor T.sub.1 is turned on while T.sub.2 is off, bringing the node N.sub.1 to zero volts. This turns off the transistor T.sub.3 while the transistor T.sub.4 has been turned on by a precharge signal, bringing node N.sub.2 to V.sub.cc -V.sub.T, where V.sub.T is the threshold voltage. Transistor T.sub.5 is similarly turned on by the supply voltage V.sub.cc, which brings the node N.sub.3 to V.sub.cc -V.sub.T. In this manner, transistor T.sub.6 is turned on, but the source and drain will be at zero volts because of .phi..sub.1. The voltage at N.sub.2 turns on the transistor T.sub.7, bringing N.sub.4 to ground. As N.sub.4 and N.sub.5 are now at zero volts, the transistor T.sub.8 is off.

Because of the voltage at N.sub.2, the transistor T.sub.9 is turned on, bringing the node N.sub.6 to ground. Remembering that a transistor is on whenever V.sub.G -V.sub.S -V.sub.T is greater than 0, and that a depletion transistor has a negative threshold voltage, the zero volts at N.sub.4 will still turn on the transistor D.sub.1. Because of the small difference between V.sub.G and V.sub.S, depletion transistor D.sub.1 will operate somewhat as a resistance.

Transistor T.sub.10 will be turned off by the zero voltage at its gate while the transistor T.sub.11 is turned on by the voltage level at N.sub.2, thereby taking the node N.sub.7 to ground. Therefore, at this point, .phi..sub.3 is at zero output while both input signals are at zero input.

If .phi..sub.1 and .phi..sub.2 occur simultaneously, the circuit operates as a clock circuit and the invention serves to produce an output at .phi..sub.3. However, .phi..sub.1 and .phi..sub.2 do not always occur simultaneously, and, in many applications, .phi..sub.2 may well occur after .phi..sub.1. Note that one objective here is to keep .phi..sub.3 low until both .phi..sub.1 and .phi..sub.2 are high.

Referring to the prior art circuit in FIG. 1, if .phi..sub.1 occurs earlier than .phi..sub.2, N.sub.5 will be driven high while N.sub.2 will remain high. A large current flow then occurs through transistors T.sub.10 and T.sub.11, which can only be compensated for by making transistor T.sub.11 much larger than transistor T.sub.10. This is typically seven times as large. However, the transistor T.sub.10 must be very large in order to drive the load capacitance. Therefore, transistor T.sub.11 is larger than desirable.

Under the invention disclosed here, if only .phi..sub.1 goes high, while in the meantime .phi..sub.p has gone to a zero stage, transistor T.sub.1 is turned off while transistor T.sub.2 is turned on. However, node N.sub.1 remains at zero volts because of the input at .phi..sub.2. Therefore, T.sub.3 remains off, while T.sub.4 has similarly turned off. N.sub.2 will remain floating at about V.sub.cc -V.sub.T while N.sub.3, due to the inherent capacitance C.sub.i across the gate and drain of T.sub.6, will float up due to the rise of .phi..sub.1. Thus, a full signal .phi..sub.1 is transmitted across the transistor T.sub.6.

It should be noted that the node N.sub.4 has remained at ground and the full signal at N.sub.5 will now charge the capacitors C.sub.1. Transistor T.sub.8 has turned on, which will then raise the node N.sub.4 to a point between V.sub.cc and ground due to the current flow between T.sub.8 and T.sub.7. This rise in voltage at N.sub.4 will raise the node N.sub.5 even higher because of a bootstrap effect and will maintain D.sub.1 in an on state. The transistor D.sub.1 and the transistor T.sub.9 are ratioed to give approximately zero volts at N.sub.6. This is done by making T.sub.9 larger than D.sub.1. In a typical case, the channel W.sub.1 of D.sub.1 might be 8 microns, causing the channel of T.sub.9 to be approximately 56 microns. Finally, T.sub.10 is maintained off by the low voltage at N.sub.6, and T.sub.11 remains on, keeping N.sub.7 at zero.

Now as .phi..sub.2 rises to its voltage level, T.sub.2 is turned on, bringing N.sub.1 to a full V.sub.cc -V.sub.T, and turning on T.sub.3, bringing N.sub.2 to zero volts. N.sub.3 will now be brought toward zero volts, turning off T.sub.6, although N.sub.5 maintains its charge due to C.sub.1. T.sub.7 is now turned off as is T.sub.11, which brings N.sub.4 to V.sub.cc -V.sub.T. This turns on the transistor D.sub.1 hard with a full transmission of the charged N.sub.5 to the node N.sub.6, which turns on the transistor T.sub.10. Because of the bootstrap effect at N.sub.5 and N.sub.6, the node N.sub.7 will receive a full V.sub.cc. .phi..sub.3 now is an output at a V.sub.cc level.

In summary, the upper path through the transistor T.sub.6 has offered a faster path than the lower path through transistors T.sub.2, T.sub.3. While the prior art allowed a current flow through transistors T.sub.10 and T.sub.11, the AND-gate clock 10 provides an alternative current flow through D.sub.1 and T.sub.9. In this manner, T.sub.11 does not have to be made significantly larger than T.sub.11, as T.sub.9 and D.sub.1 have accomplished this purpose.

Claims

1. An AND-gate clock comprising:

an input stage adapted to receive a first and a second input signal for providing a plurality of interstage signals in response to the first and second input signals;

an output stage for driving a load having a large capacitance; and

an isolation stage means coupled between the input stage and the output stage for receiving the plurality of interstage signals and for enabling the output stage to provide a true level to the load only when the first and second input signals are at a true level.

2. The AND-gate clock of claim 1 wherein the isolation stage means provides a current path in alternative to current flow through the output stage when the second input signal is at a false level.

3. The AND-gate clock of claim 1 wherein the input stage comprises:

a first MOSFET having its source grounded and its gate connected to a precharge signal;

a second MOSFET having its source connected to the drain of the first MOSFET, its gate connected to a first input, and its drain connected to a second input;

a third MOSFET having its gate connected to the drain of the first MOSFET and its source grounded;

a fourth MOSFET having its source connected to the drain of the third MOSFET, its gage connected to a precharge signal, and its drain connected to a supply voltage;

a fifth MOSFET having its source connected to the drain of the third MOSFET and its gate connected to a supply voltage;

a sixth MOSFET having its drain connected to the first input and its gate connected to the drain of the fifth MOSFET;

a seventh MOSFET having its source grounded and its gate connected to the drain of the third MOSFET;

an eighth MOSFET having its source connected to the drain of the seventh MOSFET, its gate connected to the source of the sixth MOSFET, and its drain connected to a supply voltage;

a capacitance connected between the gate and source of the eighth MOSFET.

4. The AND-gate clock of claim 3 wherein the isolation stage comprises:

a ninth MOSFET having its source connected to the drain of the seventh MOSFET and its gate connected to the drain of the third MOSFET; and

a depletion channel MOSFET having its drain connected to the source of the sixth MOSFET, its gate connected to the drain of the seventh MOSFET, and its source connected to the drain of the ninth MOSFET.

5. The AND-gate clock of claim 1 wherein the output stage comprises:

a first MOSFET having its gate coupled to the isolation stage means and its drain connected to a supply voltage; and

a second MOSFET having its source grounded, its gate coupled to the input stage, and its drain connected to the source of the first MOSFET whereby an output capable of driving a large load capacitance is produced at the source of the first MOSFET when the first and second input signals are high.

6. The AND-gate clock of claim 1 wherein the input stage has three outputs and the isolation stage means comprises:

a first MOSFET having its gate connected to a first output of the input stage and its source connected to a second output of the input stage; and

a depletion channel MOSFET having its drain connected to a third output of the input stage, its gate connected to the source of the first MOSFET and its source connected to the drain of the first MOSFET.

7. A circuit for driving a large load capacitance when two input signals are high comprising:

a first input node;

a second input node;

circuit means for turning on a first MOSFET when the second input node is low and for turning the first MOSFET off when both the first input node and the second input node are high;

a driver stage for producing a high level output when the first MOSFET is turned off; and

an isolation stage coupled between the circuit means and the driver stage and containing a depletion channel MOSFET responsive to the first MOSFET for causing the driver stage to produce a high level output when the first MOSFET is turned off.

8. The AND-gate clock of claim 7 wherein the isolation stage provides a current path to divert current from the output stage when the first signal is high and the second signal is low.

9. An AND-gate clock comprising:

a first MOSFET having its source grounded and its gate connected to a precharge signal;

a second MOSFET having its source connected to the drain of the first MOSFET, its gate connected to a first input, and its drain connected to a second input;

a third MOSFET having its gate connected to the drain of the first MOSFET and its source grounded;

a fourth MOSFET having its source connected to the drain of the third MOSFET, its gage connected to a precharge signal, and its drain connected to a supply voltage;

a fifth MOSFET having its source connected to the drain of the third MOSFET and its gate connected to a supply voltage;

a sixth MOSFET having its drain connected to the first input and its gate connected to the drain of the fifth MOSFET;

a seventh MOSFET having its source grounded and its gate connected to the drain of the third MOSFET;

an eighth MOSFET having its source connected to the drain of the seventh MOSFET, its gate connected to the source of the sixth MOSFET, and its drain connected to a supply voltage;

a capacitance connected between the gate and source of the eighth MOSFET;

a ninth MOSFET having its source connected to the drain of the seventh MOSFET and its gate connected to the drain of the third MOSFET;

a depletion channel MOSFET having its drain connected to the source of the sixth MOSFET and its gate connected to the drain of the seventh MOSFET;

a tenth MOSFET having its gate connected to the source of the depletion MOSFET and its drain connected to a supply voltage; and

an eleventh MOSFET having its source grounded, its gate connected to the drain of the third MOSFET, and its drain connected to the source of the tenth MOSFET whereby an output capable of driving a large load capacitance is produced at the source of the tenth MOSFET when the first and second inputs are high.