This application claims the priority benefit of Japan application serial no. 2022-133799, filed on Aug. 25, 2022. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
The invention relates to a flash memory constructed by an AND type memory cell array.
(A) of
(B) of
In the existing AND type flash memory, during a programming operation, since the local source line LSL is floating, a problem of programming punch-through does not occur. However, in programming, it is necessary to implant hot electrons generated by channel current between the source and the drain into a floating gate, and in order to eliminate electrons from the floating gate FG towards the local bit line LBL for erasing, it is necessary to increase an overlapping area between the drain and the floating gate FG. Therefore, there is a problem that it is difficult to miniaturize a cell size.
The invention is directed to an AND type flash memory, seeking miniaturization of a memory cell size to achieve high integration.
The invention provides an AND type flash memory including a memory cell array, the memory cell array includes a plurality of memory cells electrically connected in parallel between a source line and a bit line. A plurality of parallel and elongated diffusion regions are formed in the memory cell array, and the plurality of memory cells connected in parallel respectively include a gate and a charge accumulation layer, and the gate is disposed between the diffusion regions opposite to each other, the charge accumulation layer serves as a gate insulating film, and is capable of storing charges, and the charge accumulation layer includes at least three or more insulating layers.
The invention provides a programming method, adapted to an AND type flash memory, wherein the AND type flash memory includes a memory cell array, the memory cell array includes a plurality of memory cells electrically connected in parallel between a source line and a bit line. A plurality of parallel and elongated diffusion regions are formed in the memory cell array, and the plurality of memory cells connected in parallel respectively include a gate and a charge accumulation layer, and the gate is disposed between the diffusion regions opposite to each other, the charge accumulation layer serves as a gate insulating film, and includes at least three or more insulating layers, and a program voltage is applied to the gate of a selected memory cell, and a reference voltage is applied to a channel, thereby accumulating charges tunneled from the channel in the charge accumulation layer.
The invention provides an erasing method, adapted to an AND type flash memory, wherein the AND type flash memory includes a memory cell array, the memory cell array includes a plurality of memory cells electrically connected in parallel between a source line and a bit line. A plurality of parallel and elongated diffusion regions are formed in the memory cell array, and the plurality of memory cells connected in parallel respectively include a gate and a charge accumulation layer, and the gate is disposed between the diffusion regions opposite to each other, and the charge accumulation layer serves as a gate insulating film, and includes at least three or more insulating layers, and a reference voltage is applied to the gate of a selected memory cell, and an erase voltage is applied to a well including a channel, and charges accumulated in the charge accumulation layer are released to the channel through tunneling. In a certain form, a block including a plurality of memory cells connected in parallel is selected, and the plurality of memory cells in the selected block are erased all at once.
According to the invention, in the AND type memory cell array, since the memory cell has a charge accumulation layer including at least three or more insulating layers and capable of storing charges, it is possible to realize miniaturization of the memory cell array and simplification of the manufacturing process.
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
(A) of
(B) of
The invention relates to a metal-oxide-nitride-oxide-semiconductor (MONOS) type or silicon-oxide-nitride-oxide-silicon (SONOS) type AND-type flash memory constructed by a memory cell array, which has a following structure: trapping charges from a channel to a silicon nitride (SiN) layer, or releasing charges from the SiN layer to the channel via Fowler-Nordheim (FN) tunneling. In this way, the problem of punch-through from a drain to a source of a memory cell is eliminated, and an overlapping area from the drain to a gate is suppressed to the minimum, so that the miniaturization of the memory cell and the simplification of the manufacturing process may be achieved.
As shown in
A plurality of memory cells MC electrically connected to the source line SL and the bit line BT in parallel are formed between the selection transistor SSEL1 of the source line side, the selection transistor BSEL1 of the bit line side and the selection transistor SSEL2 of the source line side, the selection transistor BSEL2 of the bit line side, and the memory cells connected in parallel form a block.
Gates of the selection transistor SSEL1 of the source line side and the selection transistor BSEL1 of the bit line side in the row direction are commonly connected to the corresponding selection control line SG1, and gates of the selection transistor SSEL2 of the source line side and the selection transistor BSEL2 of the bit line side in the row direction are commonly connected to the corresponding selection control line SG2. Moreover, gates of the memory cells in the row direction are connected to the corresponding word line WL.
A rectangular area represented by dotted lines in
One memory cell MC is composed of a diffusion region 12, a charge accumulation layer 14, a gate 16, and a WL wiring electrically connected to the gate 16. In order to electrically separate adjacent memory cells along the row direction, shallow trench isolations (STI) extending along the column direction are formed between the diffusion regions 12. Moreover, the shallow trench isolations STI also simultaneously separate the charge accumulation layer 14 of the adjacent memory cells along the row direction. However, as shown in
As the gate insulating film of the selection transistor, a thick insulating film 22 is added to the charge accumulation layer 14, which prevents charge accumulation in the charge accumulation layer of the selection transistor to cause variation of the threshold Vt of the selection transistor even if a high voltage is applied to the gate of the selection transistor. However, the thick insulating film 22 is not essential, which may be omitted as long as a high voltage such as charges accumulated in the charge accumulation layer 14 is not applied to the gate. Also, the selection transistor SSEL2 of the source line side and the selection transistor BSEL2 of the bit line side are constructed in the same manner.
An orientation of the selection transistor SSEL1 is 90 degrees different from an orientation of the memory cell MC, i.e., the selection transistor SSEL1 selectively connects/disconnects the diffusion region 12 of the source line side of the memory cell MC to the source line SL. The selection transistor SSEL1 is turned on when the selection control line SG1 is higher than the threshold Vt of the selection transistor SSEL1, and electrically connects the diffusion region 12 of the memory cell to the source line SL. The selection transistor SSEL2 is also configured in the same manner as the selection transistor SSEL1, and the selection transistor BSEL1 of the bit line side and the selection transistor BSEL2 of the bit line side that are not shown are also configured in the same manner.
In the embodiment, by adopting the AND type cell structure, different to the existing AND type flash memory, the selection control line SG1, the selection control line SG2 and the word line WL may be formed simultaneously. Moreover, as shown in
Referring to
It is assumed that the memory cell connected to CG11 of the block 1 is selected. Similar to a two-dimensional NAND flash memory, reading and programming are performed in units of word lines (page unit), and erasing is performed in units of blocks. Table 1 shows voltages applied to each part of the selected block 1 and the non-selected block 2 during reading, programming, and erasing.
[Reading Operation]
In the case of one bit per memory cell, about 2 V is applied to the CG of the selected memory cell, about 0.6 V is applied to the bit line BL, and the source line SL is grounded for reading. About −0.6-0 V is applied to other unselected CGs. A voltage higher than the threshold Vt of the selection transistor is applied to the selection control line SG11 and the selection control line SG12. When the threshold Vt of the memory cell connected to CG11 is lower than VCG11 (“1” cell), the cell current flows from the bit line BL to the source line SL. On the other hand, when the threshold Vt of the memory cell connected to CG11 is higher than VCG11 (“0” cell), the cell current does not flow from the bit line BL to the source line SL. In order to accurately read the data of the memory cell, the threshold Vt of the memory cell must be higher than a CG bias voltage of the non-selected memory cell.
[Programming Operation]
In programming, a high voltage (for example, ˜10 V) is applied to the selected CG11 and an intermediate voltage (for example, ˜5 V) is applied to the non-selected CGs. In the case of “0” programming (electrons are implanted into the charge accumulation layer), 0 V is applied to the bit line BL. The same voltage as that applied to the bit line BL is also applied to the source line SL. In the case of “1” programming (in the case of inhibited programming where electrons are not implanted into the charge accumulation layer), a positive voltage (for example, ˜1.6 V) is applied to the bit line BL. The same voltage as that applied to the bit line BL is also applied to the source line SL.
In “0” programming, the selection control line SG11 and the selection control line SG12 apply a voltage higher than the threshold Vt (for example, ˜1 V) of the selection transistors to turn on the selection transistors, and electrically connect the bit line BL to the diffusion region of the memory cell, and apply 0 V to the diffusion region. Thus, the electrons tunneled from the channel are implanted into the charge accumulation layer 14 of the selected memory cell, and the electrons are accumulated in the charge accumulation layer 14. Since the insufficient intermediate voltage not enough for tunneling through the channel is applied to the gates of the non-selected memory cells, “0” programming is not performed.
In “1” programming, since a positive voltage is applied to the bit line, the selection transistors are turned off by the high voltage of the selection control line SG11 and the selection control line SG12, i.e., the diffusion region of the memory cell becomes a floating state. If a high voltage is applied to CG11, potentials of the diffusion region and the channel are self-boosted due to coupling, and a potential difference between the channel and the charge accumulation layer does not become large enough for tunneling. Therefore, the selected memory cells or the non-selected memory cells are not programmed.
Moreover, 0 V is applied to the selection control line SG21 and the selection control line SG22 of the block 2 to turn off the selection transistors, so that the diffusion regions of the memory cells are separated from the source line SL/bit line BL.
In a certain embodiment, the charge accumulation layer 14 includes at least three insulating layers. The first layer is a lower insulating layer (such as an oxide layer) facing the silicon surface, the second layer is a SiN layer that accumulates charges for data identification, and the third layer is an upper insulating layer (for example, an oxide layer) facing the gate/word line WL. A thickness of effective oxide of the lower insulating layer is thinner than a thickness of effective oxide of the upper insulating layer. The opposite situation is also valid, and in this case, the flow of charges towards the SiN layer during programming is different from that during erasing. In the case that the thickness of the effective oxide film of the lower insulating layer is thin, charges flow between the silicon surface and the SiN layer during programming and erasing. On the other hand, in the case that the thicknesses of the two insulating layers are opposite, the charges flow between SiN and the gate/word line WL during programming and erasing.
As a representative example, the initial example (where the thickness of the lower insulating layer is thinner than the thickness of the upper insulating layer) is described. After the bit line BL is grounded, the memory cell connected to CG11 is subjected to “0” programming (electrons are implanted into SiN from the channel). After a positive voltage (˜1.6 V) is applied to the bit line BL, the two diffusion regions 12 of the source line side and the bit line side are separated from the bit line BL and the source line SL. Therefore, the diffusion region 12 and the channel region apply a high voltage and an intermediate voltage to CG11 and other CGs, thereby enabling self-boosting, a voltage difference between the diffusion region 12 and CG11 becomes smaller, and in the memory cell connected to CG11, electrons are not implanted into the SiN layer from the substrate.
[Erasing Operation]
In the case of erasing, the memory cells of the selected block (selected block 1) are simultaneously erased. The N well and P well formed in the substrate are electrically connected. During the erasing process, a high voltage (such as 8 V˜14 V) is applied to the P well, and all CGs in the selected block are grounded, so that the bit line BL and the source line SL are floating. Then, electrons are tunneled from the SiN layer to the P well, or holes are implanted from the P well into the SiN layer of the memory cell to recombine with the electrons. Thus, the threshold Vt of the memory cell is lower than a read voltage applied to the selected CG during the reading operation. On the other hand, in unselected blocks, all CGs are floating. If a high voltage is applied to the P well, the floating CGs are self-boosted, and the unselected blocks are not erased. In addition, erasing is preferably performed in units of blocks, but may also be performed in units of word lines.
As described above, in the existing AND type flash memory, the charge accumulation layer uses a floating gate (FG). In contrast, in the embodiment, a dielectric (SiN: silicon nitride layer) is used as the charge accumulation layer. In the embodiment, the floating gate is not used, so that the process of manufacturing the memory cells may be simplified.
During programming, the existing AND type flash memories use hot electron implantation to the floating gate, but in the embodiment, electrons tunneling from the channel and diffusion region to the charge accumulation layer by applying a high voltage to the gate are used. In order to avoid obstructing programming of cells that have not been implanted with electrons (“1” programming cells), the diffusion region is in a floating state, and an intermediate voltage is applied to the unselected word line WL, and then both of the channel and the diffusion region are self-boosted, and the voltage difference between the word line WL and the silicon surface is reduced, thereby avoiding implantation of electrons of the “1” programming cell to the charge accumulation layer.
Referring to
As shown in
After forming the two wells 32 and 34, an insulator 40 for the selection transistors (SSEL1, SSEL2, BSEL1, BSEL2) is formed on the P well 34. Then, as shown in (A) and (B) of
For example, the SiN layer and the charge accumulation layer 42 including the insulating films are deposited on the P-well 34. Then, as shown in (A)-(E) of
Then, other mask materials (such as silicon oxide film or silicon nitride film, etc., which are not shown) are deposited on the entire surface, and anisotropic etching of the other mask materials is performed, as shown in (A)-(C) of
After the side walls 50 are formed, as shown in
Then, the insulating layer 54 (such as silicon oxide film, etc.) is entirely deposited, and then as shown in
Then, as shown in (A) and (C) of
After forming the diffusion region 58, as shown in (A) to (C) of
Then, by using the same mask 62, P-type impurities are implanted into the region of the insulator 40 for the selection transistors to form a high-concentration P-type diffusion region 64. The mask may also be used to adjust the threshold Vt of the selection transistor.
After removing the mask 62, as shown in (A) to (C) of
Then, as shown in (A) to (G) of
Then, an interlayer insulating layer is deposited, and a contact hole is formed through the interlayer insulating layer. Finally, as shown in
As another example of fabricating the AND type flash memory of the SONOS type, the timing of forming the diffusion region 58 that provides the source/drain of the memory cell may be changed. Namely, the N-type impurities may be implanted just after patterning the first gate material 46 which may be used as a mask for ion implantation. Furthermore, as shown in
The row selection/driving circuit 130 selects the word line WL based on a row address, and drives the selected word line WL and the non-selected word line with a voltage corresponding to the operation. The row selection/driving circuit 130 applies the voltages shown in Table 1 to the word line WL (CG) and the selection control line (SG).
The column selection circuit 140 selects the bit line BL and the source line SL based on a column address, and applies a voltage corresponding to the operation to the selected bit line BL and the source line SL, or sets the same in a floating state.
The read/write control unit 160 controls reading, programming, and erasing operations according to commands received from an external host device. The read/write control unit 160 includes a read amplifier or a write amplifier, etc. The read amplifier reads a current or voltage flowing in the bit line BL and source line SL connected to the selected memory cell during the reading operation. The write amplifier applies a read voltage to the selected bit line during the reading operation, or applies a voltage to the selected bit line or non-selected bit line during the programming operation, thereby setting the bit line or source line to the floating state during the erasing operation.
Preferred embodiments of the invention have been described in detail, but the invention is not limited to the specific embodiments, and various modifications and changes may be made within the scope of the spirit of the invention described in the claims.
Number | Date | Country | Kind |
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2022-133799 | Aug 2022 | JP | national |