Patent Application
20060270229
This invention was made with support from the United States Department of Commerce, National Institute of Standards and Technology (NIST) Contract No. 70NANB2H3030
The present invention relates generally to nanoporous templates, and specifically to nanoporous templates of anodized aluminum oxide.
An aluminum (Al) thin film may be anodized in acid to produce nanoporous anodized aluminum oxide (AAO) templates, where such templates comprise nanopores and are useful in the formation of nanorods (Masuda et al., Science, 1995, 268, p. 1466; and Masuda et al., Appl. Phys. Lett., 1997, 71, p. 2770; Jessensky et al., Appl. Phys. Lett., 1998, 72(10), p. 1173; Yin et al., Appl. Phys. Lett., 2001, 79, p. 1039; Zheng et al., Chem. Mater., 2001, 13, p. 3859). A consequence of this anodization process, however, is the production of a layer of aluminum oxide at the bottom of each nanopore (i.e., an AAO “barrier layer”) that inhibits electrical contact between the nanopores and the silicon (Si) wafer or other material the aluminum thin film resides upon.
Efforts to electrodeposit nanorods in these AAO nanopore templates (i.e., to form a nanorod/AAO array) have proved challenging because the AAO barrier layer must generally be removed before metal nanorod electrodeposition may be performed with good a real and height uniformity.
Several different methods to remove the AAO barrier layer have been reported in the scientific and patent literature, but these procedures do not give optimal results. For example, phosphoric acid (H3PO4) may be used to dissolve the AAO barrier layer (Chu et al., Chem. Mater. 2002, 14, p. 4595; Crouse et al., Appl. Phys. Lett. 2000, 76 (1), p. 49), but the AAO nanopores are isotropically widened as a result. That is, because H3PO4 etching is isotropic; not only is the AAO barrier layer dissolved, but also the pore walls are dissolved, and hence pore diameter increases. Subsequent nanorod electrodeposition then produces larger diameter nanorods. Also, H3PO4 etching may decrease the adhesion of the AAO to the Si wafer to the point where liftoff of the AAO from the Si wafer may occur. For many applications, smaller rather than larger diameter nanorods are required, so that the concomitant pore diameter increase from H3PO4 etching is inimical to these applications. For situations where planarization of a nanorod structure is required through the application of chemical-mechanical planarization (CMP), then any decrease in the adhesion of the nanorod/AAO array to the Si-wafer is also undesirable.
When the anodization of an Al thin film is complete, the Al metal initially present is completely consumed and the anodization current drops. If the anodization voltage is reduced in a stepwise manner, small dendrite pores can form in the barrier layer and permit pulsed electrodeposition of nickel (Ni) and cobalt (Co) nanowire arrays (Nielsch et al., Appl. Phys. Lett. 2001, 79 (9), p. 1360; Nielsch et al., Adv. Mater. 2000, 12 (8), p. 582). Such anodization voltage reduction and other electrochemical methods to remove the barrier layer have also been described. See Govyadinov et al., J. Vac. Sci. Technol. B 1998, 16 (3), p. 1222; Yuan et al., Appl. Phys. Lett. 2001, 78 (20) p. 3127; Saito et al., Appl. Phys. Lett. 1989, 55, p. 607; Jeong et al., Chem. Mater. 2002, 14, p. 1859; Jeong et al., Chem. Mater. 2002, 14 (10) p. 4003; and Forrer et al., J. Appl. Electrochem. 2000, 30, p. 533. Such methods have a significant drawback, however, in that the nanopore diameter gets larger with each reduction in voltage. This can compromise substrate adhesion, which, as mentioned above, has implications for processing techniques such as CMP.
An interface layer of niobium (Nb) may be placed between the Si wafer and the Al. Nb is anodized to insulating Nb2O5 and reduced in hydrogen (H2) at 500° C. for 2 hours to yield partially conducting NbO2. See Iwasaki et al., Appl. Phys. Lett. 1999, 75 (14), p. 2044; Jeong et al., Appl. Phys. Lett. 2001, 78 (14), p. 2052. The partially conducting NbO2 interface, however, has a resistivity significantly higher than that of, for example, a Au interface layer. Subsequent nanowire electrodeposition on an NbO2 interface gives mixed results. For example, while Ni nanowires may be electrodeposited on NbO2, platinum (Pt) nanowire electrodeposition on an NbO2 interface layer is extremely difficult. Even in the case of Ni nanorods, the fill factor (i.e., the ratio of the number of filled nanopores to total number of nanopores, expressed as a percent) is only about 40-50%, likely due to the high NbO2 resistivity. Moreover, the high NbO2 resistivity contributes to undesirable contact resistance between the nanowires and the Si substrate, a critical consideration in most electronic device applications.
A thin (e.g., 20 nm) interface layer of gold (Au) may be used between a substrate and the Al layer. See Yang et al., Solid State Commun. 2002, 123, p. 279. However, during anodization, a distribution of nanopore lengths ensues due to slight variations in a) the Si wafer resistivity, b) differences in the contact resistance where the anodization power supply is connected to the Si-wafer, or c) temperature across the Si wafer, and the resulting nanoporous AAO template suffers from a lack of uniformity.
Recently, a group at Penn State has described a method to penetrate the AAO barrier layer and promote detachment of the AAO layer as a freestanding thin film, separate from the substrate. The method uses a thin layer of titanium (Ti) underneath the Al to be anodized, but does not rely on the improved conductivity that results between the AAO nanopore and any underlying metal conducting layer (e.g., Au) as a result of the presence of this Ti layer. See Tian et al., Nanoletters 2005; ASAP Article; DOI: 10.1021/n10501112.
As a result of the above-described limitations, a method of generating nanoporous AAO templates, with better size control and more uniformity, and which can be used to efficiently make nanorods (i.e., with high fill factor) via electrochemical deposition, would be very beneficial.
As mentioned in the background, anodization of an Al thin film in dilute acid produces a nanoporous anodized aluminum oxide (AAO) template, which may be used as a template for nanorod deposition and/or growth. At the bottom of each nanopore, however, an AAO barrier layer is produced which inhibits nanorod electrodeposition.
In some embodiments, the present invention is directed to methods that eliminate the AAO barrier layer, and which have significant advantages compared to previously reported methods. Such AAO barrier layer elimination results from the formation of a sacrificial barrier layer, the use of which, at least in some embodiments of the present invention, results in uniform Pt nanorod growth in a nanoporous anodized aluminum oxide template over large areas (e.g., 2.85 cm2) with a high fill factor (pores-filled/total-pores). Through control of the interface oxide layer thickness, the etch time, and the etch solution composition; the areal density of filled nanowires in the nanoporous anodized aluminum oxide template may be controlled. The height of, for example, Pt nanorods (aka nanowires) can also be controlled by the duration of the Pt electrodeposition.
The formation of uniform height, small diameter metal nanorods in a nanoporous AAO template on a conducting substrate and/or Si wafer is the starting point for the fabrication of nanorod field emitters, thermoelectric devices, field effect transistor (FET) devices, and other electronic devices through the integration of nanotechnology, electrochemical, and Si microfabrication techniques.
The foregoing has outlined rather broadly the features of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
In some embodiments, the present invention is directed to nanoporous anodized aluminum oxide templates of high uniformity and methods for making same, wherein such templates lack a AAO barrier layer. In some or other embodiments, the present invention is directed to methods of electrodepositing nanorods in the nanopores of these templates to form nanorod arrays. In still other embodiments, the present invention is directed to electrodepositing catalyst material in the nanopores of these templates and growing nanorods or other 1-dimensional nanostructures via chemical vapor deposition (CVD) or other techniques.
In the following description, specific details are set forth such as specific quantities, sizes, etc. so as to provide a thorough understanding of embodiments of the present invention. However, it will be obvious to those skilled in the art that the present invention may be practiced without such specific details. In many cases, details concerning such considerations and the like have been omitted inasmuch as such details are not necessary to obtain a complete understanding of the present invention and are within the skills of persons of ordinary skill in the relevant art.
Referring to the drawings in general, it will be understood that the illustrations are for the purpose of describing a particular embodiment of the invention and are not intended to limit the invention thereto.
In some embodiments of the present invention, methods for making a nanoporous AAO template first require providing a layered thin film material. Referring to
Referring to the layered thin film material above, the substrate can generally comprise any material. Exemplary materials include, but are not limited to, semiconductors, glasses, molecular solids, metals, ceramics, polymers, and combinations thereof. In some embodiments, the substrate is substantially smooth. “Substantially smooth” (aka “substantially flat”), as defined herein, is a surface smoothness sufficient to allow for reflection of visible light off the surface. In some embodiments, the substrate comprises a polished Si wafer.
In some embodiments, the substrate comprises an adhesion layer 101b. This optional adhesion layer can improve adhesion of the first metal layer 102 with the substrate. In some embodiments, the adhesion layer comprises Ti, but can generally be any thin layered material that adheres strongly to both the substrate base 101a and the first metal layer 102. In some embodiments, the thickness of this layer is important. In such embodiments, the thickness of this adhesion layer can be in the range of from at least about 5 nm to at most about several μm. In addition to Ti, a titanium-tungsten alloy (e.g., 10% Ti-90% W) or chromium (Cr) can be used.
Generally, the first metal layer 102 comprises any metal that is electrically-conductive and is not susceptible, or is only moderately susceptible, to anodization, i.e., it will not readily oxidize under the conditions of the anodization process—it is substantially immune to anodization. Suitable metals include, but are not limited to, gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), nickel (Ni), ruthenium (Ru), rhodium (Rh), iridium (Ir), osmium (Os), and combinations thereof. In some or other embodiments, when the first metal layer 102 is moderately susceptible to anodization, any oxide formed in this layer can be removed or reduced prior to subsequent steps of electrodeposition. In some embodiments, the thickness of this first metal layer is important. In such embodiments, the thickness of this layer can be in the range of from at least about 10 nm to at most about 100 μm. In some embodiments, the first metal layer may be of some material other than metal, provided that it is at least semiconducting (e.g., Si). In some embodiments, the first metal (conductive) layer is simply a homogeneous extension of the substrate (e.g., a Si wafer).
The second metal layer 103 generally comprises any electrically-conducting metal other than Al, which becomes insulating upon anodization. Suitable metals include, but are not limited to, titanium (Ti), magnesium (Mg), niobium (Nb), tantalum (Ta), tungsten (W), zirconium (Zr), zinc (Zn), and combinations thereof. In some embodiments, the thickness of this second metal layer is important. In such embodiments, the thickness of this layer can be in the range of from at least about 5 nm to at most about 20 nm. In some embodiments, it is advantageous that this metal, once oxidized by an anodization process, be etchable under conditions that do not etch, or only slightly etch, AAO.
In some embodiments, the aluminum thin film 104 has a thickness in the range of from at least about 10 nm to at most about 300 μm. Understandably, the thickness of this Al film can have significant implications on nanopore depth in the corresponding nanoporous AAO template.
Referring to
Techniques for anodizing Al metal to AAO are well-known in the scientific literature. See Keller et al., J. Electrochem. Soc., 1953, 100, p. 411; Kawai et al., J. Electrochem. Soc. 1975, 122, p. 32; Thompson et al., Nature, 1978, 272, p. 433; and Masuda et al., Science, 1995, 268, p. 1466. The step of anodizing generally comprises the sub-steps of: (a) contacting the layered thin film material with an electrolyte; (b) establishing an electrochemical cell, wherein the layered thin film material serves as an anode; and (c) applying a voltage to the electrochemical cell to electrochemically anodize anodizable layers of the layered thin film material and produce a nanoporous AAO template. Suitable electrolyte includes, but is not limited to, oxalic acid, sulfuric acid, phosphoric acid, citric acid, and combinations thereof.
The above-mentioned step of etching the sacrificial barrier layer (generated by the effect of the anodization process on the second metal layer) generally comprises immersing (or otherwise contacting) into an etching solution. Suitable etching solutions include any etching solution that can etch the insulating metal oxide (sacrificial barrier layer), but does not etch, or only slightly etches the AAO formed during the anodization process. Etching solutions found to be particularly useful for etching oxidized Ti (i.e., TiOx) comprise water (H2O), hydrofluoric acid (HF), and hydrogen peroxide (H2O2). Compositional ranges for these solutions are 5:1:1 to 1000:1:1 H2O: HF:H2O2 (where HF is 47-51% in water and H2O2 is 29-32% in water). In some embodiments, if wider nanopore diameters are desired, an etching step involving H3PO4 (or other suitable etchant) may be used before or after the forementioned TiO, etching step. Both NaOH and KOH also isotropically etch AAO and can also be used.
The resulting nanoporous AAO templates produced by the above-described methods typically have a high degree of uniformity in the nanopores. Depending upon the embodiment, the nanopore (channel) depth can be in a range from at least about 10 nm to at most about 300 nm, diameters (widths) of the nanopores can be in a range from at least about 10 nm to at most about 450 nm (after etching), and interpore spacing (i.e., the distance between nanopores) can be in the range of from at least about 20 nm to at most about 500 nm.
In some embodiments, nanorods are electrochemically-formed in the nanoporous AAO template (
In some embodiments, material is electrochemically deposited in the wells of the nanopores to serve as a catalyst for the CVD growth of other nanorods (aka “nanowires”) and/or other 1-dimensional nanostructures. “1-dimensional nanostructures,” as defined herein, are nanoscale in exactly two dimensions, typically resulting in structures with high aspect ratios (e.g., length-to-width ratios of at least about 10). These nanostructures include, but are not limited to, nanotubes of carbon and other materials (e.g., born nitride), metal nanorods, and nanorods of nitrides, oxides, and carbides of a variety of materials. In some embodiments, the nanoporous AAO template assists in aligning these nanostructures as well as minimizing the contact resistance to the substrate, both critical aspects in many device applications. Alternatively, if the first metal layer and the catalyst are of the same material (e.g., Fe, Co, Ni, Au, etc.), then the step of electrochemically depositing a metal catalyst in the wells may be skipped, and chemical vapor-deposited 1-dimensional nanostructures can be grown in the nanopores directly from the first metal layer.
In some embodiments, the nanoporous AAO template is at least partially etched after deposition of nanorods into the nanopores. Such etching can be done using either a wet etching solution (e.g., buffered oxide etch (BOE), H2O:HF:NH4F, etc.) or dry etching (e.g., reactive ion etching, inductively-coupled plasma, etc.). Such etching can produce an aligned array of nanorods, with the tops of the nanorods exposed.
In some embodiments, the nanorods or other 1-dimensional nanostructures made in accordance with either Step 205a or Step 205b of
The nanorods or other 1-dimensional nanostructures, made according to the above-described embodiments, are operable for a wide variety of applications depending on their compositional make-up, dimensions, density, etc. The formation of uniform height, small diameter metal nanorods in a nanoporous AAO template on a conducting substrate and/or Si wafer can provide a starting point for the fabrication of nanorod field emitters, thermoelectric devices, field effect transistors, nanowire electrochemical electrodes, and other electronic devices through the integration of nanotechnology, electrochemical, and Si microfabrication techniques. Generally, methods of the present invention are broadly applicable to the fabrication of any electronic device for which a high electrical conductivity of nanowires (with respect to an underlying substrate) is desired. Such electronic devices include future nanorod transistor arrays such as those described by Ng et al. in Nano Lett. 2004, 4(7), p. 1247.
The following examples are included to demonstrate particular embodiments of the present invention. It should be appreciated by those of skill in the art that the methods disclosed in the examples that follow merely represent exemplary embodiments of the present invention. However, those of skill in the art should, in light of the present disclosure, appreciate that many changes can be made in the specific embodiments described and still obtain a like or similar result without departing from the spirit and scope of the present invention.
This Example serves to illustrate the anodization of aluminum metal to AAO, in accordance with embodiments of the present invention.
In a typical anodization, a 1 micrometer thick layer of Al was deposited onto the substrate by either sputtering or electron-beam evaporation. The Al-coated substrate was used as the anode in an electrochemical cell machined from polycarbonate. Approximately 12 mm distant from the Al-coated substrate, a 25×25 mm Pt-wire gauze (Alfa) was used as the counterelectrode. The electrochemical cell was filled with a solution of 0.3 Molar oxalic acid (C2H2O4). Using a standard laboratory power supply (Agilent E3634A, 0-50 VDC, 0-4 A), the Al thin film was anodized at 25° C. for approximately 600 seconds with a constant voltage of 40 VDC and a current of about 8-12 mA/cm2. After the anodization was complete (i.e., Al completely converted to AAO), the current drops to <0.001 mA/cm . The nanoporosity may then be studied by scanning electron microscopy (SEM). With the above conditions, the nanoporosity appears to be in the 40-60 nm diameter range, as shown in the SEM-derived image of
Computer control of the anodization power supply and measurement of the anodization potential and current were implemented.
This Example serves to illustrate the anodization of layered thin film materials (i.e., several), along with their subsequent etching, to yield nanoporous AAO templates, in accordance with embodiments of the present invention.
Cleanroom produced wafers comprising a Si wafer base, a 20 nm Ti adhesion layer, a 50 nm Au (first metal) layer, a Ti (second metal) layer, and a 1000 nm Al layer. Wafers were produced having a Ti second metal layer thicknesses of 5, 10, 15, and 20 nm. Such wafers are denoted Si-wafer/20 nm Ti/50 nm Au/x nm Ti/1000 nm Al, where x is 5, 10, 15, and 20 nm. For each wafer, the Al was anodized until an insulating sacrificial barrier layer of TiOx was formed (the exact stoichiometry of the anodized Ti is unknown at present). As it is known that TiO2 is etched by a solution of 20 H2O:1 HF:1 H2O2 (by volume) at a rate of 880 nm/minute (Williams et al., J. MEMS 1996, 5 (4), p. 256; Williams et al., J. MEMS 2003, 12 (6), p. 761), the anodized wafers were subsequently dipped in etching solution (either 2:1 or 4:1 H2O:TiO, etch, i.e., 40 H2O:1 HF:1 H2O2 or 80 H2O:1 HF:1 H2O2, respectively). The procedure used to etch the sacrificial TiOx barrier layer was to first determine the etch time to AAO liftoff (typically 60-90 seconds), and then to etch 15-30 seconds short of the liftoff time to remove the TiOx barrier layer.
This Example serves to illustrate the subsequent electrodeposition of Pt into nanopores of a nanoporous AAO template to form Pt nanorods.
Cyclic voltammetry and Pt nanorod electrodeposition were used to characterize etched wafer samples and provide large area nanoporous AAO templates (0.75 inches in diameter), uniformly filled with Pt nanorods. The electrochemical procedures used a commercially-available 10 grams/gallon platinum plating solution (Technic, Inc., Cranston, R.I., product no. #240651); a layered thin film material denoted Si wafer/20 nm Ti/50 nm Au/10 nm TiOx/1200 nm AAO, and comprising a Si-wafer base (2.5 cm in diameter), a 20 nm Ti adhesion layer, a 50 nm Au (first metal layer), a 10 nm TiOx sacrificial barrier layer, and a 1200 nm AAO layer, wherein the layered thin film material serves as the working electrode; a 25×25 mm Pt wire gauze, 45 mesh, woven from 0.198 mm diameter wire (Alfa Aesar, stock #41814) serves as the counter electrode; and a Ag/AgCl (3M KCl) electrode serves as the reference electrode (CH Instruments, part no. CH111). A CH Instruments Model 660B electrochemical analyzer with CH Instruments electrochemical workstation version 4.05 software was used to control and record the electrochemical data.
Before the TiOx etch, the current measured at −0.6 V (the potential at which the Pt nanorod growth is performed), is less than 1×10−6 A. After 30 seconds of TiOx etch, the current measured at −0.6 V is about 3 mA, which enables unifonn Pt—NR growth over the entire 1.9 cm (¾ in.) diameter.
A cross section scanning electron microscope-secondary electron (SEM-SE) photomicrograph after electrodeposition showing essentially 100% fill factor for a Si-wafer/20 nm Ti/50 nm Au/10 nm Ti/AAO/1200 nm Pt nanorod sample is presented in
This Example serves to illustrate the effect that the thickness of the second metal layer can play in determining the eventual fill factor realized in electrodepositing nanorods in the nanopores.
A design-of-experiments was performed to study the effect of top Ti layer thickness (second metal layer) on Pt nanorod electrodeposition. Four top Ti layer (second metal layer) thicknesses (5 nm, 10 nm, 15 nm, and 20 nm) were used in the fabrication of 2 each of 100 mm diameter Si wafers coated with an adhesion layer of Ti (20 nm), a 50 nm Au (first metal) layer, a Ti (second metal) layer, and a 1000 nm Al layer. While the 5 nm top Ti layer wafers produced about a 100% Pt nanorod fill factor, the 20 nm top Ti layer wafers produced significantly lower Pt nanorod fill factors of about 1-5%. The top Ti-layer thickness, TiOx etch time, and TiOx etchant composition may all be used to control (i.e., tune) the Pt nanorod fill factor.
This Example serves to illustrate the effect of the composition of the first metal layer on the electrodeposition of Pt nanorods, in accordance with some embodiments of the present invention.
Wafers with a Cu conductive layer, i.e., Si-wafer/20 nm Ti/50 nm Cu/5 nm Ti/1000 nm Al, were fabricated. These wafers were then anodized, etched, and subjected to electrodeposition of Pt nanorods alongside similar wafers having a Au first metal layer. Preliminary results indicate that, at least in the production of Pt nanorods, a Cu first metal layer is better than Pt. Additionally, a Cu first metal layer is better than Au for two qualitative reasons. First, if the Pt-nanorod filled AAO samples are to be planarized, then Cu in the first metal layer is compatible with most cleanroom CMP tools, while Au is inimical to semiconductor performance and is typically disallowed in cleanroom CMP tools. Second, empirical observations in the FE-SEM suggest that in a sample with a Cu first metal layer, the Cu is in better electrical contact with the Pt-nanorods than a similarly produced sample with an Au first metal layer.
This Example serves to illustrate how the TiOx etch rate can be modulated via modifying the concentration of the etching solution, and how these etches can be used in combination with isotropic etching, in accordance with some embodiments of the present invention.
Etch experiments using several different compositions of TiOx etch were used to slow the TiOx etch to a manageable time (about 30 seconds to 1 minute). The TiOx etch composition (i.e., etching solution) was initially 20:1:1 H2O:BF:H2O2 (where HF is 47-51% (concentrated) and H2O2 is 29-32%). 40:1:1 and 80:1:1 TiOx etch compositions were also used. In several instances, isotropic pore widening, using 5% H3PO4, was applied to the anodized wafers before the TiOx etch was applied. The pore widening produced larger diameter nanopores, and hence larger diameter electrodeposited Pt nanorods.
This comparative example serves to illustrate the non-uniformity of the nanopores in nanoporous AAO templates produced without a second metal layer (i.e., methods currently used in the art).
As described in the background, a thin (e.g., 20 nm) interface layer of gold may be used between a substrate and the Al layer. See Yang et al., Solid State Commun. 2002, 123, p. 279. However, during anodization, a distribution of nanopore lengths results due to slight variations in a) the Si wafer resistivity, b) differences in the contact resistance where the anodization power supply is connected to the Si wafer, or c) temperature across the Si wafer. This is shown schematically in
It will be understood that certain of the above-described structures, functions, and operations of the above-described embodiments are not necessary to practice the present invention and are included in the description simply for completeness of an exemplary embodiment or embodiments. In addition, it will be understood that specific structures, functions, and operations set forth in the above-described referenced patents and publications can be practiced in conjunction with the present invention, but they are not essential to its practice. It is therefore to be understood that the invention may be practiced otherwise than as specifically described without actually departing from the spirit and scope of the present invention as defined by the appended claims.
