Patent Application
20060225007
The present invention relates generally to integrated circuit designs, and more particularly to methods for preventing antenna effect with model extraction in a circuit design for advanced processes.
As integrated circuit (IC) technologies continue to advance and circuit density becomes higher, antenna effect becomes one of the important reliability issues in today's very large scale integration (VLSI) systems, especially in the routing stage of VLSI design. The antenna problem is a side effect of various plasma-based manufacturing processes such as etching. These plasma-based processes are widely used to achieve the fine feature size of modern IC.
Plasma etchers or ion implanters can induce a voltage into isolated leads, thereby overstressing the thin gate oxides. The polysilicon or metal leads act like an antenna to collect charges and the accumulated charges may result in oxide breakdown. The induced charges on metal or via during manufacturing process can damage devices. These charges may also have a negative effect on hot-carrier devices aging lifetime. Since oxides of new devices are expected to become thinner as VLSI design continues to scale up, the antenna effect is expected to be a more serious problem.
In order to reduce or eliminate antenna effect, it is found that the ratio of the physical area of the conductors such as the metal or polysilicon interconnects making up the “antenna” to the total gate oxide area to with the antenna is electrically connected should be limited so that charges will not build up so much to create the antenna effect. The occurrences of the antennas can be predicted and their ratios calculated using design verification and layout software known as “design rule check” (“DRC”) programs.
One of commonly practiced conventional methods used for reducing antenna effect is to pre-determine the antenna effect based on a per-layer and gate area ratio. By knowing the ratio of antenna effect based on a certain area, the physical layout of the interconnects of the circuit designs such as System-on-Chip (SoC) designs can be adjusted to prevent antenna effects. Such conventional method can determine the antenna effect by each layer of metal and is good for 0.18 um or above aluminum processes. However, it may not be as efficient for other types of process such as copper processes of 0.13 um, 90 nm, and below where copper processes require more layers of metal than aluminum process. As the size of metal processes becomes even smaller, the number of layers of metal will also increase.
It is therefore desirable in the art to improve the methods for determining antenna ratio for all types of processes, and for eliminating antenna effect therewith.
In view of the foregoing, this invention provides antenna models for hierarchical or cell-based design for SoC design that uses cumulative metal ratio instead of per metal layer check to determine the antenna ratio.
A method is disclosed for determining an antenna ratio for an interconnect in a circuit. The interconnect may be routed through one or more connection layers and may be electrically coupled to one or more gate oxide areas. A cumulative antenna ratio for all components on each connection layer is determined by considering an antenna effect caused by each component on a predetermined connection layer with regard to the gate oxide areas coupled thereto and any components on one or more connection layers coupled between the component of the present connection layer and the gate oxide areas. In the same fashion, a top layer cumulative antenna ratio for the interconnect is determined based on the cumulative antenna ratios for the connection layers below the top layer.
Along with these embodiments and examples, an improved technique for determining antenna ratio is possible allowing antenna effect prevention for SoC designs that utilize copper processes of 0.13, 90 nm, and below.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
The present invention provides methods for preventing antenna effect with model extraction in a circuit design for advanced process. For circuit design layouts, a boundary information is needed with regard to a interconnect of a circuit block, which includes the information for the antenna ratio. By appropriately identifying the antenna ratio, the DRC tools can adjust the design and reduce possible defective designs. It is understood that the antenna effect is largely related to interconnects in the circuit design, and they largely include metal interconnects or metal structures or polysilicon interconnects at this point. The following discussion uses metal interconnects or metal structures as illustration examples, and it should be understood that the present invention applies to all other types of interconnects as long as they cause the antenna effect as the metal structures. As such, the metal layers illustrated below are only examples for the connection layers of the circuit.
The diagram 100 includes five separate gates 102, 104, 106, 108, and 110, each of which connects to one of the first layer metals 112, 114, 116, and 118. First layer metal 120 is connected to a diffusion region 122. Each of the first layer metals 112, 114, 116, 118, and 120 is then connected to one of the second layer metals 124, 126, and 128, each of which is further connected to one of the third layer metals 130, 132, and 134. The third layer metals 130 and 132 are tied directly to each other through a second layer metal 136. Both the third layer metals 132 and 134 are also connected to a fourth layer metal 138.
Since the number of metal layers for the copper process of 0.13 um, 90 nm, and below is high, the calculation of the antenna effect based on a per-layer and gate area ratio will not be efficient. According to the present invention, the antenna effect can be determined by calculating a cumulative antenna ratio for all metal layers involved.
When performing circuit design layout with antenna effect prevention, there are two models can be used according to the present invention. One is referred to as an interface antenna model and the other is abstract antenna model.
For the purpose of this invention, custom functional modules known as “soft blocks” will be treated as hard modules (also known as IPs) like SRAMs, flash ROMs, hard processor core for both the abstract antenna model and the interface antenna model. Information of the block such as the internal metal ratio for certain layers of metals will have to be extracted from GDSII files which are a standard layout format. Using the interface model, a top-level layout can be verified for the antenna effect in a rather early stage without verifying the whole chip layout down to each layer, thereby avoiding late surprise and saving layout iteration. If the verification produces any design rule violations, they can be fixed quickly.
The diagram 300 is similar to the diagram 100 in that it includes 5 separate gates 302, 304, 306, 308, and 310, each of which connects to one of the first layer metals 312, 314, 316, and 318. A first layer metal 320 is connected to a diffusion region 322. Each of the first layer metals 312, 314, 316, 318, and 320 is then connected to one of the second layer metals 324,326, and 328, each of which is further connected to one of the third layer metals 330, 332, 334, and 336. The third layer metals 332 and 334 are tied directly to each other through a second layer metal 338, while both the third layer metals 334 and 336 are also connected to a fourth layer metal 340. Since the interface model 200 is implemented at the analysis stage at the top level for the copper process, parts of the copper process will be hidden within a block 342. In other words, all metal layers, gates, and metal wires will be hidden by the block 342 during the SoC chip assembly and will not be seen by any auto-router. The top level of the copper process as embodied in the diagram 300 is represented in a block 344, meaning that the gate 302, the first metal layer 312, the second metal layer 324, and the third metal layer 330 can not be seen from outside. The third layer metals 330 and 332 are the same piece of metal, and they are separated into input section represented by the third layer metal 332 and output section, which is represented by the third layer metal 330.
As the copper process continues to shrink in size, model extraction algorithms will be more complicated, thereby making calculation of antenna effect more difficult. By implementing the interface model 200 at the analysis stage at the top level, a new improved and simplified method for calculating the cumulative antenna ratio is possible.
First, the antenna ratio for each metal layer is saved as an internal ratio, and then passed on to the next layer so equations for each layer remains around the same length and never gets too complicated. As shown in equation sets 348 and 350, top ratio calculations for both the third layer metals and fourth layer metals remain relatively short compared with the equation sets 146 and 148 of
In short, the accumulative antenna ratio is better than the per-layer antenna ratio for advanced metal processes with small dimensions. The abstract model in the diagram 346 allows antenna ratio calculation to be performed as one in a flatten chip. As for the hierarchical layout, the discrepancy in antenna report between place and route, and design rule check tools sign-off can be reduced resulting in reduction in layout iteration. With both abstract models in the diagram 346 and the interface model of
The above illustration provides many different embodiments or embodiments for implementing different features of the invention. Specific embodiments of components and processes are described to help clarify the invention. These are, of course, merely embodiments and are not intended to limit the invention from that described in the claims.
Although the invention is illustrated and described herein as embodied in one or more specific examples, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention, as set forth in the following claims.
