Claims
- 1. An apparatus having a KASUMI round for generating a fractional portion of the KASUMI cipher operably coupled to a calculation controller for sequencing eight rounds to produce a KASUMI output.
- 2. The apparatus of claim 1, further comprising a sub-key generator, connected to the calculation controller, for producing sub-keys each round for use by the KASUMI round.
- 3. An apparatus for performing KASUMI ciphering on a KASUMI input with a key to produce a KASUMI output, comprising:
a KASUMI round for generating a fractional portion of the KASUMI cipher, configurable for calculation of even and odd rounds, eight rounds being calculated to produce the KASUMI output; memory for storing the output of the KASUMI round; and a selector for providing the input to the KASUMI round, the KASUMI input being selected during the first round and the contents of the memory being selected during subsequent rounds.
- 4. The apparatus of claim 3, further comprising a sub-key generator for generating sub-keys for each round based on the key.
- 5. The apparatus of claim 3, wherein the apparatus is adapted to be operable in an access point.
- 6. The apparatus of claim 3, wherein the apparatus is adapted to be operable in an access terminal.
- 7. The apparatus of claim 3, wherein the apparatus is adapted to be operable in a W-CDMA system.
- 8. A KASUMI round for receiving an input and producing an output, operable with a partial round calculator from which the output is produced, comprising:
a memory for storing an intermediate value from the partial round calculator; and a selector for selecting between the input and the contents of the memory for delivery to the partial round calculator.
- 9. A KASUMI round for receiving a 64-bit input and producing a 64-bit output comprising:
an FO function; an FL function; an XOR gate; a first register; a second register for receiving the output of the XOR gate, the output being concatenated with the output of the first register to produce the 64-bit output; a first input mux for selecting between the upper half of the 64-bit input and the output of the second register under control of an input select signal, the output being received at the first register; a second input mux for selecting between the lower half of the 64-bit input and the output of the first register under control of the input select signal, the output being delivered as the second operand to the XOR gate; a first datapath mux, the output of which is delivered to the FL function, for selecting between the output of the first input mux and the output of the FO function under control of a data flow signal; a second datapath mux, the output of which is delivered to the FO function, for selecting between the output of the FL function and the output of the first register under control of the data flow signal; and a third datapath mux, the output of which is delivered as the first operand to the XOR gate, for selecting between the output of the FL function and the FO function under control of the data flow signal.
- 10. An FO function for receiving an input and producing an output, operable with a partial FO calculator from which the output is produced, comprising:
a memory for storing an intermediate value from the partial FO calculator; and a selector for selecting between the input and the contents of the memory for delivery to the partial FO calculator.
- 11. An FO function for receiving a 32-bit input and producing a 32-bit output, comprising:
a first XOR gate for receiving a KO sub-key as a first operand; an FI function for receiving the output of the first XOR gate; a second XOR gate for receiving the output of the FI function as a first operand; a first register for receiving the output of the second XOR gate; a second register; a first input mux, the output of which is delivered as a second operand to the first XOR gate, for selecting between the upper half of the 32-bit input and the output of the second register under control of an input select signal; and a second input mux, the output of which is delivered as the second operand to the second XOR gate and the input to the second register, for selecting between the lower half of the 32-bit input and the output of the first register under control of the input select signal, the output being concatenated with the output of the second XOR gate to produce the 32-bit output.
- 12. An FI function for receiving an input and producing an output, operable with a partial FI calculator from which an intermediate value and the output is produced, comprising:
a memory for storing the intermediate value from the partial FI calculator; and a selector for selecting between the input and the contents of the memory for delivery to the partial FI calculator.
- 13. An FI function for receiving a 16-bit input and producing a 16-bit output, comprising:
a first register; a second register; a first input mux for selecting between the output of the first register and the upper nine bits of the 16-bit input under control of an input select signal; a second input mux for selecting between the output of the second register and the lower seven bits of the 16-bit input under control of the input select signal; an S9 function for receiving the output of the first input mux; a first XOR for receiving as operands the output of the S9 function and the zero-extended output of the second input mux; an S7 function for receiving the output of the second input mux; a second XOR for receiving as operands the truncated output of the first XOR and the output of the S7 function, the output being concatenated with the output of the first XOR to produce the 16-bit output; a third XOR, the output of which is delivered to the first register, for receiving as operands a first KI sub-key and the output of the first XOR; and a fourth XOR, the output of which is delivered to the second register, for receiving as operands a second KI sub-key and the output of the second XOR.
- 14. A sub-key generator for receiving a key and, for each round, producing eight sub-keys, comprising:
a first shift register, loadable with the key, left rotatable by eight bits under control of a rotate signal, four of the eight sub-keys being derived from the output; and a second shift register, loadable with a masked version of the key, left rotatable by eight bits under control of the rotate signal, four of the eight sub-keys being derived from the output.
- 15. A sub-key generator for receiving a 128-bit key and, for each round, producing eight 16-bit sub-keys, comprising:
a first 128-bit shift register, loadable with the key; a second 128-bit shift register, loadable with a masked version of the key, the first sub-key being produced from the third highest 16 bits, the second sub-key being produced from the fourth highest 16 bits, the third sub-key being produced from the fifth highest 16 bits, the fourth sub-key being produced from the lowest 16 bits; a rotator for rotating left by one bit the contents of the first shift register located in highest 16 bits to produce the fifth sub-key; a rotator for rotating left by five bits the contents of the first shift register located in the second highest 16 bits to produce the sixth sub-key; a rotator for rotating left by eight bits the contents of the first shift register located in the third lowest 16 bits to produce the seventh sub-key; and a rotator for rotating left by 13 bits the contents of the first shift register located in the second lowest 16 bits to produce the eighth sub-key.
- 16. A method for performing KASUMI ciphering comprising:
for each of eight rounds:
selecting the input for use in the calculating step during the first round; selecting the stored result for use in the calculating step in subsequent rounds; calculating a partial result; and storing the partial result in a memory; and delivering the stored result as the output.
- 17. The method of claim 16, wherein the calculating step comprises:
when the round is odd:
performing the FL function on the upper half of the input or stored result, as selected in the selecting step; performing the FO function on the output of the FL function; and XORing the output of the FO function with the lower half of the input or stored result, as selected in the selecting step; when the round is even:
performing the FO function on the upper half of the stored result; performing the FL function on the output of the FO function; and XORing the output of the FL function with the lower half of the stored result; delivering as the partial result the output of the XORing step concatenated with the upper half of the input or stored result, as selected in the selecting step.
- 18. The method of claim 16, further comprising generating sub-keys for each round.
- 19. A method for performing the FO function comprising:
for each of three stages:
selecting the input for use in the calculating step in the first stage; selecting the stored result for use in the calculating step in subsequent stages; calculating a partial result; storing the partial result in memory; and delivering the partial result as the output;
- 20. The method of claim 19, wherein the calculating step comprises:
XORing the upper half of the input or stored result, as selected in the selecting step, with a sub-key; performing the FI function on the output of the XORing step; XORing the output of the FI function with the lower half of the input or stored result, as selected in the selecting step; and delivering as the partial result the upper half of the input or stored result, as selected in the selecting step, concatenated with the output of the second XORing step.
- 21. A method for performing the FI function comprising:
calculating a partial result using the input; XORing the partial result with a sub-key; storing the partial result in memory; calculating a second partial result using the stored result; and delivering the second partial result as the output;
- 22. The method of claim 21, wherein the calculating step comprises:
performing the S9 function on the upper nine bits of the input or stored result; zero extending the lower 7 bits of the input or stored result; XORing the zero-extended input or stored result with the output of the S9 function; perfoming the S7 function on the lower 7 bits of the input or stored result; truncating the output of the XORing step; XORing the truncated XOR output with the output of the S7 function; delivering as the partial result the output of the second XORing step concatenated with the output of the first XORing step.
- 23. A method for generating sub-keys comprising:
loading two sub-key shift registers; for each of eight rounds:
deriving the sub-keys from the sub-key shift registers; and rotating the two sub-key shift registers left by eight bits.
- 24. The method of claim 23, wherein the loading step comprises:
loading a key into the first sub-key shift register; masking the key; and loading the masked key into the second sub-key shift register.
- 25. The method of claim 24, wherein the deriving step comprises:
deriving the first sub-key from the third highest set of 16 bits of the second shift register; deriving the second sub-key from the fourth highest set of 16 bits of the second shift register; deriving the third sub-key from the fifth highest set of 16 bits of the second shift register; deriving the fourth sub-key from the lowest set of 16 bits of the second shift register; rotating the highest set of 16 bits of the first shift register by one bit to the left to produce the fifth sub-key; rotating the second highest set of 16 bits of the first shift register by five bits to the left to produce the sixth sub-key; rotating the third lowest set of 16 bits of the first shift register by eight bits to the left to produce the seventh sub-key; and rotating the second lowest set of 16 bits of the first shift register by thirteen bits to the left to produce the eighth sub-key.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims the benefit of U.S. Provisional Application Serial No. 60/294,958, filed May 31, 2001, the content of which is incorporated herein by reference in its entirety.
Provisional Applications (1)
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Number |
Date |
Country |
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60294958 |
May 2001 |
US |