Claims
- 1. An encoder interface module comprising:
an input unit for receiving input signals from an encoder unit; a counter unit coupled to the input unit for counting the input signals; a plurality of registers; and a compare unit, the compare unit coupled to the selected registers and the counter unit, the compare unit generating flag signals in response to first control signals when a value in the counter unit and a value in a register have predetermined relationship, the compare unit generating flag signals in response to second control signals when the value of the counter unit is zero.
- 2. The encoder interface module as recited in claim 1 further comprising;
a control register, the control register storing the flag signals.
- 3. The encoder interface module as recited in claim 2 wherein the input signals are a series of pulse streams, the pulse streams determining clock signals and direction signals.
- 4. The encoder interface module as recited in claim 3 wherein the input signals include an encoder index/reset pulse.
- 5. The encoder interface unit as recited in claim 3 further including a quadrature decode unit, the quadrature decode unit determining the frequency and direction of counter increment or decrement.
- 6. The encoder interface unit as recited in claim 1, the encoder interface unit being coupled to a device peripheral bus, wherein other modules are coupled to device peripheral bus, the encoder interface unit further comprising an output multiplexer, the output multiplexer applying control signals generated in the encoder interface to the modules.
- 7. The encoder interface unit as recited in claim 6, the encoder interface unit further comprising at least one input multiplexer unit for selecting a control signal from the modules to be distributed within the encoder interface unit.
- 8. The encoder interface unit as recited in claim 1 wherein the plurality of registers is selected from the group consisting of a period register, an initialization register, a sampling latch, a reset latch, and a compare register.
- 9. The encoder interface unit as recited in claim 1 wherein the signals applied to the encoder interface unit are derived from a rotating shaft.
- 10. The encoder interface unit as recited in claim 9 wherein the encoder interface unit derives a quantity related to the speed/frequency of the shaft rotation.
- 11. A method for providing an encoder interface unit between an encoder unit and a central processing unit, the method comprising:
in response to applied signals from an encoder unit, generating pulses derived from the applied signals; counting the number of pulses; comparing the number of pulses with a preselected value; and generating a flag signal when the number of pulses and the preselected value have predetermined relationship.
- 12. The method as recited in claim 11 wherein the preselected value is selected from the group of preselected values consisting of period value, a zero value, and a compare value.
- 13. The method as recited in claim 11 wherein the generated pulses includes determining a direction of rotation from the applied signals.
- 14. The method as recited in claim 11 further comprising selecting a control signal for distribution to other modules without the intervention of the central processing unit.
- 15. The method as recited in claim 11 further comprising selecting a control signal from the interface units for determining the use of the interface unit as a reset trigger and a sample latch trigger.
- 16. The method as recited in claim 11 wherein counting the number of pulses provides a quantity related to the speed/frequency of a rotating shaft.
- 17. A data processing unit comprising:
a central processing unit; a device peripheral bus; and a plurality of peripheral devices coupled to the device peripheral bus, wherein one of the peripheral devices is an encoder interface module; the encoder interface module including:
an input unit for receiving input signals from an encoder unit; a counter unit coupled to the input unit for counting the input signals; a plurality of registers; and a compare unit, the compare unit coupled to the selected registers and the counter unit, the compare unit generating flag signals when a value in the counter unit is zero or the value in the counter and a value in a register have a predetermined relationship.
- 18. The data processing system as recited in claim 17 wherein the encoder interface module further includes a control register, the control register storing the flag signals.
- 19. The data processing system as recited in claim 17 further comprising:
at least one additional peripheral device coupled to the device peripheral bus; an inter-module bus; and an inter-module control unit, wherein the encoder interface unit further includes
an input multiplexer for selectively transmitting signals from the inter-module bus to the encoder interface unit, and an output multiplexer for selectively transmitting signals from the encoder interface module to the inter-module control unit.
- 20. The data processing system as recited in claim 19 wherein the inter-module control unit and the inter-module bus transfer control signals between interface modules without intervention of the central processing unit.
- 21. The data processing system as recited in claim 20 wherein the additional peripheral device is selected from the group consisting of an analog to digital converter module, an encoder event manager module, and an event capture module.
- 22. The data processing system as recited in claim 17 wherein the counter unit and the registers of the encoder interface module are coupled to the device peripheral bus.
- 23. The data processing system as recited in claim 17 wherein the value in the counter unit is related to the speed/frequency of a shaft.
- 24. The data processing system as recited in claim 17 wherein the signals from the encoder unit include two pulse streams and an index reset/signal.
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application claims the benefit of U.S. Provisional Application No. 60/245,656 filed Nov, 2, 2000; U.S. Provisional Application No. 60/255,253 filed Dec. 13, 2000; and U.S. Provisional Application No. 60/267,589 filed Feb. 9, 2001.
[0002] U.S. patent application No. (Attorney Docket TI-32610) entitled “APPARATUS AND METHOD FOR PERIPHERAL INTER-MODULE EVENT COMMUNICATION SYSTEM”, invented by Zhenyu Yu, filed on even date herewith, and assigned to the assignee of the present application; and U.S. patent application No. (Attorney Docket TI-32332) entitled “APPARATUS AND METHOD FOR A SIGNAL TRANSISITON CAPTURE MOULE”, invented by Zhenyu Yu, filed on even date herewith, and assigned to the assignee of the present application are related applications.
Provisional Applications (3)
|
Number |
Date |
Country |
|
60245656 |
Nov 2000 |
US |
|
60255253 |
Dec 2000 |
US |
|
60267589 |
Feb 2001 |
US |