Patent Application
20180077587
Embodiments of the invention relate to the field of radio access networks (“RAN”), and more specifically, to an apparatus and method for optimizing assignment of cells (or sector carriers) to at least one coordination set (“C-Set”) associated with at least one baseband processing unit (“BBU”).
In a conventional radio base transceiver station (“BTS”), the radio head and baseband unit (“BBU”, also referred to as a digital unit (“DU”)) are combined in a single chassis or platform, such as in an eNodeB. A BTS can include media access control (MAC) and physical layer (PHY) processing elements such as MAC layer processor, a channel coder, a channel interleaver, a channel modulator, a multiple-input, multiple-output (“MIMO”) processor, a transmit power controller, a frame and slot signal generator, an inverse fast Fourier transform (IFFT) modulator a cyclic prefix (“CP”) adder, a channel filter, an analog-to-digital (“DAC”) converter, an up converter, a gain controller, a carrier multiplexer, a power amplifier and limiter, radio frequency filters and one or more antennas.
Functionally, a radio head contains the base station radio frequency (“RF”) circuitry plus analog-to-digital and digital-to-analog converters and up/down converters. The radio head may also include operation and management processing capabilities. The BBU provides radio functions of the digital baseband domain and thus is sometimes referred to as a digital unit (“DU”).
A coordinated radio access network is a cellular network design in which the radio head, referred to in a coordinated RAN as a radio remote unit (“RRU”) is physically separated from the baseband processing unit (“BBU”) so that the BBU can be centralized and/or distributed depending on the network planning and design constraints. Functionality found in the RRU includes decoding, de-interleaving and demodulation, using modules therefore. Often, the RRU is coupled to the BBU using an optical fiber with a common public radio interface (“CPRI”) defining an interface between the RRU and BBU. Each RRU typically serves a cell, the cell being a spatial expanse into which terminals, user equipment and/or transceiver units communicate with the RRU (collectively referred to as a “UE”), and hence the network to which the RRU is coupled via the BBU. Notwithstanding the foregoing, it is noted that an RRU may have multiple cells, and multiple cells may be comprised of multiple RRUs. Hence, reference to a cell assignment and/or RRU assignment herein shall not be considered a limitation, and reference to one shall be considered a reference to the other as the invention is broad enough to cover each context.
As seen in
Conventionally, RRUs are coupled to a specific BBU, such RRU (cell) is included in a BBU's C-Set. What is desired is an ability to dynamically coordinate cells among different BBUs to optimize the performance and efficiency of a network comprised of multiple RRUs and multiple BBUs. To perform such coordination, a method of assigning a cell to a C-Set of a BBU is necessary.
There are a number of benefits of dynamically coordinating RRUs to specific C-Sets of a BBU. In the uplink (“UL”) from a UE to a RRU in a coordinated multi-point ecosystem (“CoMP”) coordination increases UE UL throughput by taking advantage of spatial diversity and interference suppression, which can, in turn, reduce required UE transmit power in the UL.
In CoMP, the number of cells assigned to a C-Set is limited. This is due to the limited capacity and processing of a single BBU and time/delay constraints between BBUs. For example, in UL CoMP the BBU has to evaluate each cell for a given UE in a short period of time.
Presently, there is no efficient method to determine the best combination of cells to C-Set assignment. The problem is partially attributable to the current use of known algorithms for assignments of elements to a set or pairing assignments. Unlike the stable roommates problem (SRP), it is desired to assign up to N cells to the same C-Set, while taking into account that in a preferred solution the number of RRUs (cells) per C-Set is not constant and also the number of C-Sets can be variable.
Further, using a brute force mathematical program to optimally assign RRUs (cells) to C-Sets is not feasible due to the large number of cells and large number of C-Sets. Such methods, as proven NP-hard, are not efficient. What is desired are well-defined heuristic methods for finding good sub-optimal solutions in a reasonable amount of time using a reasonable amount of compute resources with the objective to optimally assign cells to coordinated BBUs to maximize coordination benefits.
An embodiment of the invention is an apparatus and method to perform assignment of a plurality of cells to a coordination set (“C-Set”) associated with at least one BBU, to optimize the overall performance of a network. The method, as implemented in an embodiment, is based on a greedy algorithm and uses (1) score variables, (2) cell_score function, and variations thereof and (3) the evaluation scores, and variations thereof to determine C-Set assignments for an overall improvement of network performance. In a further embodiment, evaluation scores are used to evaluate the overall cell to C-Set assignment and then compare such assignment with an alternative assignment. Exact search methods are not an option because this problem is NP-hard and does not scale for large size problems.
The claimed process is implementable in one or more software modules comprised of executable software code processed by a microprocessor. As used herein, the hardware and software module or modules used to implement the claimed process is referred to collectively as a C-Set assignment processing circuit or C-Set assignment module. Preferably, the C-Set assignment processing circuit or C-Set assignment module is resident on a platform within a BBU or a controller operable to control one or a plurality of BBUs and associated RRUs (cells). In an embodiment, the C-Set assignment module comprises a non-transitory machine-readable medium having computer code thereon, which when executed by a set of one or more processors of a network device communicatively coupled to a BBU, causes the BBU to control at least one RRU.
An embodiment of the invention further includes a tool operable to provide a visual rendering of the problem space and solution. The claimed process further uses cell score variables operable to capture the benefit of coordination at cell edges. Moreover, an embodiment is further operable to apply policy, optimization weights, and consideration of network capacity by artificially modifying the cell score variables.
A variety of criteria and factors can be used to assign cells to C-Sets. These include, but are not limited to, load, front-haul capacity and site density. Different weights and thresholds can be used to implement or effect a cell assignment strategy such as maximum number of cells assigned to a C-Set and/or max number of C-Sets.
The invention may best be understood by referring to the following description and accompanying drawings that are used to illustrate embodiments of the invention. In the drawings:
The following description describes apparatus and method for assigning a plurality of cells to one or more a C-Sets associated with one or more BBUs according to some embodiments of the invention. The apparatus and method are generally a C-Set assignment processing circuit or C-Set assignment module.
Abbreviations used herein shall mean as follows, unless the context requires otherwise:
3GPP: 3rd Generation Partnership Project
BBU: Baseband processing Unit
CA: Carrier Aggregation
CPRI: Common Public Radio Interface
DL: Downlink (eNodeB to UE)
DL CoMP: Downlink Coordinated MultiPoint
DU: Digital Unit
DUW: Digital Unit Wideband (UMTS, UTRAN)
EPC: Evolved Packet Core
LTE: Long Term Evolution
PCI: Physical-layer Cell Identity
RAN: Radio Access Network
RF: Radio Frequency
RRU: Remote Radio Unit
RSRP: Reference Signal Receive Power
RSSI: Received Signal Strength Indicator
SINR: Signal-to-Interference-plus-Noise Ratio
TTI: Transmission Time Interval
UE: User Equipment
UL: Uplink (UE to eNodeB)
UL CoMP: Uplink Coordinated Multipoint
In the following Figures and description, numerous details such as logic implementations, opcodes, means to specify operands, resource partitioning/sharing/duplication implementations, types and interrelationships of system components, and logic partitioning/integration choices are set forth in order to provide a more thorough understanding of the present invention. It will be appreciated, however, by one skilled in the art that the invention may be practiced without such details. In other instances, control structures, gate level circuits and full software instruction sequences have not been shown in detail in order not to obscure the invention. Those of ordinary skill in the art, with the included descriptions, can implement appropriate functionality without undue experimentation.
References in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” etc., indicate that the embodiment described may include a feature, structure, or characteristic, but every embodiment may not necessarily include the feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether explicitly described.
Bracketed text and blocks with dashed borders (e.g., large dashes, small dashes, dot-dash, and dots) may be used herein to illustrate optional operations that add additional features to embodiments of the invention. However, such notation should not be taken to mean that these are the only options or optional operations, and/or that blocks with solid borders are not optional in certain embodiments of the invention.
In the following description and claims, the terms “coupled” and “connected,” along with their derivatives, may be used. these terms are not intended as synonyms for each other. “Coupled” is used to indicate that two or more elements, which may or may not be in direct physical or electrical contact with each other, co-operate or interact with each other. “Connected” is used to indicate the establishment of communication between two or more elements that are coupled with each other.
The C-Set assignment processing circuit or C-Set assignment module can be embodied in an electronic device. An electronic device stores and transmits (internally and/or with other electronic devices over a network) code (which is composed of software instructions and which is sometimes referred to as computer program code or a computer program) and/or data using machine-readable media (also called computer-readable media), such as machine-readable storage media (e.g., magnetic disks, optical disks, read only memory (ROM), flash memory devices, phase change memory) and machine-readable transmission media (also called a carrier) (e.g., electrical, optical, radio, acoustical or other form of propagated signals—such as carrier waves, infrared signals). Thus, an electronic device (e.g., a computer) includes hardware and software, such as a set of one or more processors coupled to one or more machine-readable storage media to store code for execution on the set of processors and/or to store data. For instance, an electronic device may include non-volatile memory containing the code since the non-volatile memory can persist code/data even when the electronic device is turned off (when power is removed), and while the electronic device is turned on that part of the code that is to be executed by the processor(s) of that electronic device is typically copied from the slower non-volatile memory into volatile memory (e.g., dynamic random access memory (DRAM), static random access memory (SRAM)) of that electronic device. Typical electronic devices also include a set or one or more physical network interface(s) to establish network connections (to transmit and/or receive code and/or data using propagating signals) with other electronic devices. One or more parts of the embodiments described herein may be implemented using different combinations of software, firmware, and/or hardware.
The C-Set assignment processing circuit or C-Set assignment module can be embodied in a network device. A network device (ND) is an electronic device that communicatively interconnects other electronic devices on the network (e.g., other network devices, end-user devices) to provide inputs into the C-Set assignment processing circuit or C-Set assignment module. Some network devices are “multiple services network devices” that provide support for multiple networking functions (e.g., routing, bridging, switching, Layer 2 aggregation, session border control, Quality of Service, and/or subscriber management), and/or provide support for multiple application services (e.g., data, voice, and video).
The functionality performed by the C-Set assignment processing circuit or C-Set assignment module can be embodied in a cloud or virtualized environment or provided as a service to overlapping or shared operators or enterprises. Cloud computing provides on-demand access to a shared pool of hardware resources such as computing resources, storage resources, and networking resources. Cloud computing allows users to request additional hardware resources when they are needed, and release hardware resources when they are not needed. Cloud computing has become a highly demanded service due to its capability to offer hardware resources on-demand, relatively cheap costs, scalability, accessibility, and high availability.
In an embodiment, the invention is a method to determine the optimal assignment of a cell to a coordination set (“C-Set”) associated with at least one BBU. In such embodiment, the method is based on a greedy method that assigns cells one by one to C-Sets based on, inter alia, a cell score variable that indicates the benefit of placing particular cells in the same C-Set as further described herein.
A method of the invention used in
This value is computed for each cell with respect to each of its neighboring cells. For example, as shown in
The first step of the claimed method as implemented in a C-Set assignment processing circuit or C-Set assignment module is score computation. As seen in
Other inputs to the score computation of the claimed method as implemented in a C-Set assignment processing circuit or C-Set assignment module includes network capacity, policy, and weight. These could be applied after the initial computation to adjust the cell scores. For example, if the front-haul capacity is not available to have two cells connect to the same C-Set, the score is set to zero. However, available capacity could be used to determine what weight to apply to the cell score.
A further embodiment of the claimed method applies weights to increase or decrease the value of a cell score. This could be implemented to enhance or optimize network performance in certain areas having unusual or non-conventional traffic patterns such as access point hot spots, flash crowds and areas served mainly for non-mobile machine type communications (“MTC”).
A further embodiment of the claimed method applies policy to adjust certain cell scores. This is implemented to increase the performance for a spatial extent serving specific end users such as public safety employees and government employees. Similarly, lower requirement applications such as certain MTC applications in a given area may be given lower coordination weight based on policy.
As previously noted, cells can be grouped or assigned C-Sets in the claimed method as implemented in a C-Set assignment processing circuit or C-Set assignment module based on load, front-haul capacity, site density and other criteria. The C-Set assignments can be used to determine different weights, thresholds, or dictate the strategy to use for the C-Set assignments such as maximum number of cells assigned to a C-Set and max number of C-Sets.
The second step of the claimed method as implemented in a C-Set assignment processing circuit or C-Set assignment module is initialization. As seen in
The third step of the claimed method as implemented in a C-Set assignment processing circuit or C-Set assignment module is assignment of each cell to a C-Set. This comprises assigning a cell (C_1 to C_n) to the first element (e1.1 to em.1) position of each C-Set (Set_1 to Set_m) as shown in
For C-set element e1.1 to em.1 assignment (called Root cell 1): the greedy algorithm will assign the cells that have the lowest score with respect to each other.
This cell_score( ) function is used throughout the algorithm to determine which unassigned cell to assign to a given C-Set.
Most steps of the algorithm will use the cell_score( ) function before adding a cell and call the function again with the to be added cell to determine if the cell score was decreased, increased, left the same and by how much.
In other embodiments, the cell_score( ) function could consider the last parameter as the one being evaluated and return as result the effect on the output as described below.
In a step function cell_score(list), the cell_score( ) function is called with a list of cells as input.
In a step //Input: list of cells, all input parameters to the function have been assigned cells. Thereafter, the function is called again with the additional cell and the function will determine the new cell_score value.
In a step //Output: score value, a value v is returned which is the root mean square (RMS) of the S_PCI values of all the cells given as input.
As shown in
The fourth step of the claimed method as implemented in a C-Set assignment processing circuit or C-Set assignment module is to further select and assign cells to C-Sets comprising assigning remaining cells in a C-set to the second element (e1.2 to em.2) position of each C-Set (Set_1 to Set_m).
For C-Set element e1.2 to em.2 assignment (called Root cell 2) the greedy algorithm will assign the cells that have the highest score with respect to the cell that previously was assigned in Root cell 1.
For position e1.2 to em.2, the cells from set C that have the highest score with the cell already assigned in e1.1 to e.m.1 respectively are selected, by using function cell_score( ) again.
The score of a set using function cell_score( ) is computed. For each C-Set, the function cell_score( ) is called with two parameters: the cell assigned in Root cell 1 and each of the remaining cells in C-Set (n-m cells remaining initially). For example, for Set_1, seen in the example above, example C_1 was assigned to position e1.1. The function is called as v1=cell_score(C_1, C_?) . . . vn-m=cell_score(C_1, C_?). The value v with the highest score will determine which cell will be assigned to position e1.2. The same steps are repeated for each of the remaining C-Sets (Set_2 to Set_m). While the foregoing example of how the cell_score( ) function is used to determine the subsequent cells for each C-Set, it should be realized that extensions and alternatives may use variations of this heuristic, for example to look for a global optimal (rather than greedy approach) on how to assign the Root cell 2.
The fifth step of the claimed method as implemented in a C-Set assignment processing circuit or C-Set assignment module is to further assign a C-set element comprising filling C-Set element e_.3 to e_.P assignment for Set_1 to Set_m.
For each subsequent element of the C-Sets, the cell_score( ) is computed before and after adding a new unassigned cell. A cell is assigned to a C-Set when it increases the average score the most or that reduces it the least. Once the element e_.3 of each C-Set is assigned, the process continues with element e_.4 of each C-Set and so on.
An optional sub-step of the fifth step is that if the max number of set is < than max number of BBUs available, a new Set_m+1 can be added when a given cell only diminishes the score of all current Sets (by a given threshold λ). In this case a new Set_m+1 is added to the solution and the respective cell is assigned to it.
The sixth step of the claimed method as implemented in a C-Set assignment processing circuit or C-Set assignment module is to compute and evaluate the final result of the foregoing steps. The result of the foregoing steps is evaluated with two different evaluation scores, or combination of them. The cost or value of a given result is compared to another value such as another heuristic or with an optimal solution such as that obtained with a linear program solver. The evaluation score can be used for various purposes. First, it could be used to determine how the current cell assignment compares to another one such as one obtained using manual configuration, another heuristic, or a solver. Since this is an NP-hard problem, the comparison with an exact solution obtained from a mathematical program solver (e.g. CPLEX) will only work for small size problems. The other alternative is to use the heuristic with certain variations, such as starting the algorithm with another randomly selected cell and then selecting the assignment with the best evaluation score. It could also be used to explore the solution space as further described herein.
The result can be evaluated (E_Score_1) by using the UL path loss matrix. That is, path loss is equated to the loss between UE and antenna in dB. With UL CoMP, the receive power is increased, hence path loss is decreased. The average decrease in path loss of all UEs from the input RF data can be computed before the C-Set cell assignment and after the C-Set cell assignment method described above. Hence, E_Score_1 is the average decrease in path loss of all UEs. This value will determine the overall effectiveness of the cell assignment to coordination sets with respect to its impact on the actual effectiveness of coordination. This value will indicate how effective the UL CoMP has become with the given cell to C-Set assignment.
Alternatively, the result can be evaluated (E_Score_2) with the DL CoMP. If muting is assumed, receive power can be calculated for a source RRU (cell). ((energy (RSRP) received in 1st cell and 2nd cell of the C-Set)/RSRP of interferer cells not in C-Set). The E_Score_2 is the ratio of source cell(s)/interferers (geometric factor) and determines if the cell assignment to C-Sets has been efficient in reducing the DL interference by coordinating the right cells in the same C-Set. A further embodiment takes a combination of both E_Score_1 and E_Score_2 or a weighted combination of the two. These are two example evaluation score parameters and other similar parameters can be derived from other performance metrics.
Referring to the flow chart of
In step 701, the algorithm identifies a set of cells in a set C to be assigned to elements (em.P) in a C-Set in Set S. In step 702, a cell_score value is computed between each pair of such cells that are neighbors using a cell_score function. In step 703, for the first element in the C_Set, e1.1, a first cell is placed therein based on a random selection, seeding or other selection basis. In step 704, for each of the remaining first elements of each C-Set in set S, using a greedy algorithm, a cell is assigned from Set C that has the lowest cell_score with respect to cells placed as a first element of other C-Sets in S. In step 705, the assigned cell is removed from set C. In step 706, for each of the second elements of each C-Set in set S and using a greedy algorithm, a further cell is assigned from set C that has the highest cell_score with respect to the previously assigned cell placed as first element in the same C-Set in S, and removing the further cell from set C. In step 707, for each of the third elements of each C-Set in set S, a greedy algorithm is used to assign, one of the remaining cells from set C that increases the most or decreases the least the cell_score with respect to the cells already placed in the same C-Set in S, and removing it from set C. In step 708, the foregoing step are repeated for each next element in each C-Set until all cells from set C are placed.
The cost or value of a given result can also be used for search space heuristics based on meta-heuristics such as Tabu search. Tabu search is a metaheuristic search method employing local search methods used for mathematical optimization. Local (neighborhood) searches take a potential solution to a problem and check its immediate neighbors in the hope of finding an improved solution. Local search methods tend to become stuck in suboptimal regions or on plateaus where many solutions are equally fit. Tabu search enhances the performance of local search by relaxing its basic rule. First, at each step worsening moves can be accepted if no improving move is available such as when the search is stuck at a strict local minimum. In addition, prohibitions are introduced to discourage the search from coming back to previously-visited solutions. The implementation of Tabu search uses memory structures that describe the visited solutions or user-provided sets of rules. If a potential solution has been previously visited within a certain short-term period or if it has violated a rule, it is marked as forbidden so that the algorithm does not consider that possibility repeatedly.
The claimed method as implemented in a C-Set assignment processing circuit or C-Set assignment module use at least one cell score variable and C-Set score functions to determine the cells that should be assigned to same C-Set to optimize network coordination.
Disclosed herein is one non-limiting method (heuristic) to assign a cell to C-Set, using evaluation scores. The evaluation scores are based on, inter alia, weights, thresholds and policy adjustments. Variants of the method can be used to further optimize C-Set assignments. In an embodiment, such C-Set assignments are rendered using a visualization tool.
The C-Set assignment processing circuit or C-Set assignment module can be embodied in a node comprising an electronic device or network device that includes hardware resources such as computing hardware (e.g., processors), storage hardware (e.g., Random Access Memory (RAM) and hard disks), and networking hardware (e.g., a network interface card (NIC)), or can be distributed across a plurality of nodes. The inputs into the C-Set assignment processing circuit or C-Set assignment module can come from a plurality of nodes communicatively coupled to the C-Set assignment processing circuit or C-Set assignment module.
The C-Set assignment processing circuit or C-Set assignment module can be embodied in an application running in a virtualized environment on a node or platform that executes a hypervisor (also known as a Virtual Machine Monitor (VMM)) that allows Virtual Machines (VMs) or other virtual appliances (e.g., unikernel) executing on such node to share the hardware resources of the node. Each VM running on hypervisor may execute its own operating system (OS) (e.g., a guest OS) and one or more applications. The OS and the applications may not know that they are running on a VM as opposed to running on a “bare metal” host device.
The C-Set assignment processing circuit or C-Set assignment module can be executed on a network device that is communicatively coupled to at least one BBU and is responsible for managing the resources of a plurality of RRUs. In one embodiment, such network device includes a cloud orchestration component. In one embodiment, the cloud orchestration component includes cloud management software. In one embodiment, the cloud orchestration component is responsible for managing the lifecycle of VMs and other virtual appliances. For example, network device may initiate deployment of new VMs in the datacenter, initiate migration of VMs, and initiate the decommissioning of existing VMs.
In one embodiment, the C-Set assignment processing circuit or C-Set assignment module is implemented as a unikernel. A unikernel is specialized virtual appliance that that can execute natively on a hypervisor without the need for a full-blown OS (e.g., Linux). A unikernel typically includes an application and a bare-minimum set of libraries that are needed to support that application. This is in contrast to a traditional VM that typically includes a complete guest OS, many of the features of which are not used by the application. Since unikernels typically have less code than traditional VMs, they have a smaller attack surface, which provides improved security properties. Further unikernels typically have reduced memory footprint and lower boot times compared to traditional VMs. It should be understood, however, that the C-Set assignment processing circuit or C-Set assignment module may be implemented using other types of virtualization techniques (e.g., as a VM) or even as a bare-metal deployment.
In one embodiment, the cloud orchestration component may generate an image of the C-Set assignment processing circuit or C-Set assignment module. The image of the C-Set assignment processing circuit or C-Set assignment module can be used as a template to initiate deployment of the C-Set assignment processing circuit or C-Set assignment module on one or more nodes. The cloud orchestration component may initiate deployment of a virtual C-Set assignment processing circuit or C-Set assignment module by transmitting the image of the virtual C-Set assignment processing circuit or C-Set assignment module to the BBU or controller node, along with instructions to execute the image. In one embodiment, the image of the virtual C-Set assignment processing circuit or C-Set assignment module is stored in an image repository or other storage location. In this case, the cloud orchestration component may initiate deployment of the virtual C-Set assignment processing circuit or C-Set assignment module on a node by transmitting, to the node, an indication of the location of the image along with instructions to execute that image. Once deployed on a node, the virtual C-Set assignment processing circuit or C-Set assignment module may perform the above referenced steps of the invention.
Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of transactions on data bits within a computer memory. These algorithmic descriptions and representations are the ways used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of transactions leading to a desired result. The transactions are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.
It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the above discussion, it is appreciated that throughout the description, discussions utilizing terms such as “processing” or “computing” or “calculating” or “determining” or “displaying” or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.
The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general-purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the required method transactions. The required structure for a variety of these systems will appear from the description above. In addition, embodiments of the present invention are not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of embodiments of the invention as described herein.
An embodiment of the invention may be an article of manufacture in which a non-transitory machine-readable medium (such as microelectronic memory) has stored thereon instructions which program one or more data processing components (generically referred to here as a “processor”) to perform the operations described above. In other embodiments, some of these operations might be performed by specific hardware components that contain hardwired logic (e.g., dedicated digital filter blocks and state machines). Those operations might alternatively be performed by any combination of programmed data processing components and fixed hardwired circuit components.
In the foregoing specification, embodiments of the invention have been described with reference to specific exemplary embodiments thereof. It will be evident that various modifications may be made thereto without departing from the broader spirit and scope of the invention as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.
Throughout the description, embodiments of the present invention have been presented through flow diagrams. It will be appreciated that the order of transactions and transactions described in these flow diagrams are only intended for illustrative purposes and not intended as a limitation of the present invention. One having ordinary skill in the art would recognize that variations can be made to the flow diagrams without departing from the broader spirit and scope of the invention as set forth in the following claims.
This application claims the benefit of priority to U.S. Provisional Application Ser. No. 62/393,495, filed on Sep. 12, 2016, the entire contents of which are hereby incorporated herein by reference for all purposes.
| Number | Date | Country | |
|---|---|---|---|
| 62393495 | Sep 2016 | US |
