The present invention is related to commonly assigned and co-pending U.S. patent application Ser. No. 09/671,876 entitled “APPARATUS AND METHODS FOR IMPROVED DEVIRTUALIZATION OF METHOD CALLS”, Ser. No. 09/671,770 entitled “APPARATUS AND METHOD FOR AVOIDING DEADLOCKS IN A MULTITHREADED ENVIRONMENT”, Ser. No. 09/671,773 entitled “APPARATUS AND METHOD FOR IMPLEMENTING SWITCH INSTRUCTIONS IN AN IA64 ARCHITECTURE”, Ser. No. 09/671,877 entitled “APPARATUS AND METHOD FOR DETECTING AND HANDLING EXCEPTIONS”, Ser. No. 09/671,771 entitled “APPARATUS AND METHOD FOR VIRTUAL REGISTER MANAGEMENT USING PARTIAL DATA FLOW ANALYSIS FOR JUST-IN-TIME COMPILATION”, Ser. No. 09/671,873 entitled “APPARATUS AND METHOD FOR AN ENHANCED INTEGER DIVIDE IN AN IA64 ARCHITECTURE”, Ser. No. 09/671,875 entitled “APPARATUS AND METHOD FOR CREATING INSTRUCTION BUNDLES IN AN EXPLICITLY PARALLEL ARCHITECTURE”, filed on even date herewith and hereby incorporated by reference.
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