Claims
- 1. A combination for detecting errors and providing correction information comprising:
- memory means for storing a codeword, including data symbols and parity symbols each of said symbols having multiple bits, into a location of said memory means and reading said codeword from said memory means in accordance with a control signal and an address of said codeword location;
- means for generating said parity symbols of each codeword based on said data symbols and corresponding address symbols of said codeword in accordance with a modified Reed-Solomon code, a first of said parity symbols determines an error value in said data symbols and corresponding address symbols, a second of said parity symbols provides for locating said error value in one of said data symbols and said corresponding address symbols, and a third of said parity symbols provides for detecting at least two symbol errors; and
- means coupled to said parity symbol generating means and said parity symbol outputs of said memory means for generating syndromes, said syndromes providing information to perform error detection and correction of said codeword.
- 2. The combination as recited in claim 1 wherein:
- said control signal causes said memory means to perform a write mode for storing said codeword or a read mode for reading said codeword.
- 3. The combination as recited in claim 2 wherein:
- said parity symbols generating means generates said parity symbols for said data symbols and corresponding address symbols when said memory means is performing said write mode and when said memory means is performing said read mode.
- 4. The combination as recited in claim 1 wherein:
- said parity symbol outputs from said memory means to said syndrome generating means when reading said codeword are compared to a second set of parity symbols, generated by said parity symbol generator means based on said data symbols being read and said corresponding address symbols, for determining a difference pattern for said error detection and correction of said codeword.
- 5. The combination as recited in claim 1 wherein:
- said syndrome generating means comprises means for generating a plurality of syndrome signals; and
- means coupled to said syndrome signals for interpreting said syndrome signals to identify a data symbol error and whether said data symbol error is correctable.
- 6. The combination as recited in claim 5 wherein:
- said interpreting means further comprises means for generating select signals to enable correction of said data symbol error.
- 7. The combination as recited in claim 5 wherein:
- said combination comprises means coupled to data symbols read from said memory means and one of said syndrome signals for performing symbol error correction in accordance with a select signal from said interpreting means.
- 8. The combination as recited in claim 1 wherein:
- said combination performs single data symbol error correction, double data symbol error detection, single address symbol error detection, double address symbol error detection, and single and double error detection in said parity symbols.
- 9. The combination as recited in claim 8 wherein:
- said apparatus further performs detection of any combination of two errors from said data symbols, address symbols and parity symbols.
- 10. An error detection and correction apparatus comprising:
- memory means for storing a codeword including data symbols and parity symbols into a location of said memory means and reading said codeword from said memory means in accordance with a control signal and an address of said codeword location, said address includes a plurality of symbols;
- means for generating a first (P.sub.A) of said parity symbols based on said data symbols and said corresponding address symbols of said codeword in accordance with a modified Reed-Solomon code for determining an error value in said data symbols and corresponding address symbols, where ##EQU7## N.sub.i being said data symbols and corresponding address symbols; means for generating a second (P.sub.B) of said parity symbols, where ##EQU8## .alpha. being a primitive element in a Galois Field (2.sup.m) where m is the number of bits in said symbols, said P.sub.B providing for locating a single symbol error of said data symbols and symbols of said address;
- means for generating a third (P.sub.C) of said parity symbols, where ##EQU9## for detecting at least two symbol errors of said data symbols and corresponding address symbols;
- means coupled to said data symbols and address symbols for generating said N.sub.i, .alpha..sub.i N.sub.i and .alpha..sup.2i N.sub.i product terms to produce said P.sub.A, P.sub.B and P.sub.C parity symbols in accordance with said Galois Field of 2.sup.m elements;
- means coupled to said parity symbol generating means and said parity symbol outputs of said memory means for generating syndromes; and
- means coupled to said syndromes generating means for performing error correction.
- 11. The error detection and correction apparatus as recited in claim 10 wherein:
- said control signal causes said memory means to perform a write mode for storing said codeword or a read mode for reading said codeword.
- 12. The error detection and correction apparatus as recited in claim 11 wherein:
- said parity symbols generating means generates said P.sub.A, P.sub.B and P.sub.C parity symbols for said data symbols and corresponding address symbols when said memory means is performing said write mode and when said memory means is performing said read mode generates P.sub.A ', P.sub.B ' and P.sub.C ' parity symbols.
- 13. The error detection and correction apparatus as recited in claim 12 wherein:
- said parity symbol outputs P.sub.A, P.sub.B and P.sub.C from said memory means to said syndrome generating means when reading said codeword are compared to said parity symbols P.sub.A ', P.sub.B ' and P.sub.C ', generated by said parity symbol generator means based on said data symbols being read and said corresponding address symbols, for determining a difference pattern for said error detection and correction.
- 14. The error detection and correction apparatus as recited in claim 10 wherein:
- said product terms generating means comprises means for adding a padded bit to a data symbol input and an address symbol input for matching the number of symbol bits to the bit width of a memory ship in said memory means.
- 15. The error detection and correction apparatus as recited in claim 10 wherein:
- said syndrome generating means comprises means for generating a plurality of syndrome signals; and
- said error correction means comprises means coupled to said syndrome signals for interpreting said syndrome signals to identify a data symbol error and whether said data symbol error is correctable.
- 16. The error detection and correction apparatus as recited in claim 15 wherein:
- said interpreting means further comprises means for generating select signals to enable correction of said data symbol error.
- 17. The error detection and correction apparatus as recited in claim 15 wherein:
- said apparatus comprises means coupled to data symbols read from said memory means and one of said syndrome signals for performing symbol error correction in accordance with a select signal from said interpreting means.
- 18. The error detection and correction apparatus as recited in claim 10 wherein:
- said error detection and correction apparatus performs single data symbol error correction, double data symbol error detection, single address symbol error detection, double address symbol error detection, and single and double error detection in said parity symbols.
- 19. The error detection and correction apparatus as recited in claim 18 wherein:
- said apparatus further performs detection of any combination of two errors from said data symbols, address symbols and parity symbols.
- 20. A method of detecting errors and providing correcting information comprising the steps of:
- storing a codeword, including data symbols and parity symbols each of said symbols having multiple bits, into a location of a memory means and reading said codeword from said memory means in accordance with a control signal and an address of said codeword location;
- generating said parity symbols of each codeword based on said data symbols and corresponding address symbols of said codeword in accordance with a modified Reed-Solomon code, a first of said parity symbols provides for determining an error in said data symbols and corresponding address symbols, a second of said parity symbols provides for locating said error in one of said data symbols or corresponding address symbols, and a third of said parity symbols provides for detecting at least two symbol errors; and
- generating syndromes with means coupled to said parity symbol generating means and said parity symbol outputs of said memory means, said syndromes providing information to perform error detection and correction of said codeword.
- 21. The method as recited in claim 20 wherein:
- said step of generating syndromes to perform error detection and correction of said codeword includes single data symbol error correction, double data symbol error detection, single address symbol error detection and double address symbol error detection.
- 22. A method of error detection and correction comprising the steps of:
- storing a codeword including data symbols and parity symbols into a location of a memory means and reading said codeword from said memory means in accordance with a control signal and an address of said codeword location, said address includes a plurality of symbols;
- generating a first (P.sub.A) of said parity symbols based on said data symbols and said corresponding address symbols of said codeword in accordance with a modified Reed-Solomon code for determining an error value in said data symbols and corresponding address symbols, where ##EQU10## N.sub.i being said data symbols and corresponding address symbols; generating a second (P.sub.B) of said parity symbols, where ##EQU11## .alpha. being a primitive element in a Galois Field (2.sup.m) where m is the number of bits in said symbols, said P.sub.B providing for locating a single symbol error of said data symbols and symbols of said address;
- generating a third (P.sub.C) of said parity symbols where ##EQU12## for detecting at least two symbol errors of said data symbols and corresponding address symbols;
- generating said N.sub.i, .alpha..sub.i N.sub.i and .alpha..sup.2i N.sub.i product terms which produce said P.sub.A, P.sub.B and P.sub.C parity symbols in accordance with said Galois Field of 2.sup.m elements with means coupled to said data symbols and address symbols;
- generating syndromes with means coupled to said parity symbol generator means and said parity symbol outputs of said memory means, said syndromes providing information to perform error detection and correction of said codeword; and
- performing error correction with means coupled to said syndromes generating means.
- 23. The method as recited in claim 22 wherein:
- said step of generating syndromes to perform error detection and correction of said codeword includes single data symbol error correction, double data symbol error detection, single address symbol error detection, double address symbol error detection and single and double parity symbol error detection.
- 24. The method as recited in claim 23 wherein
- said error detection and correction of said codeword further includes the step of performing detection of any combination of two errors from said data symbols, address symbols and parity symbols.
- 25. The method as recited in claim 22 wherein:
- said step of generating said product terms further comprises the step of adding a padded bit to a data symbol input and an address symbol input for matching the number of symbol bits to the bit width of a memory chip in said memory means.
- 26. A memory system comprising:
- memory means for storing a codeword including data symbols and parity symbols into a location of said memory means and reading said codeword from said emory means in accordance with a control signal and an address of said codeword location;
- means for generating said parity symbols m bits wide for each codeword in accordance with a Reed-Solomon code using q bit symbols for said data symbols and address symbols when m bit symbols are required for said Reed-Solomon code where m is equal to q +1; and
- means for padding said data symbols and address symbols with a logic zero in said parity symbol generating means to obtain said q +1 bits of said m bit symbols.
- 27. A method of detecting errors in a memory system comprising the steps of:
- storing a codeword including data symbols and parity symbols into a location of a memory means and reading said codeword from said memory means in accordance with a control signal and an address of said codeword location;
- generating said parity symbols of m bits wide for each codeword in accordance with a Reed-Solomon code using q bit symbols for said data symbols and address symbols when m bit symbols are required for said Reed-Solomon code where m is equal to x +1; and
- padding said data symbols and address symbols with a logic zero in said parity symbol generating means to obtain said q +1 bits of said m bit symbols.
Government Interests
The Government has rights in this invention pursuant to Contract No. F04701-87-C-0023, awarded by the Department of the Air Force.
US Referenced Citations (12)
Non-Patent Literature Citations (1)
Entry |
"Error-Correcting Codes for Semiconductor Memory Applications: A State-of-the-Art Review," C. L. Chen, M. Y. Hsiao, IBM J. Res. Develop--vol. 28, No. 2, Mar. 1984. |