Patent Application
20090231170
The present invention relates to an apparatus and a method for digital frequency down-conversion, and more particularly to an apparatus and a method for separating analog Intermediate Frequency (IF) signals from a composite analog IF signal including at least two frequencies according to each frequency, down-converting separated analog IF signals respectively, and then outputting at least two digital IF signals in a communication system.
As illustrated in
First, a 3FA BPF 110 filters a composite analog IF signal to which three Frequencies, e.g., fO1=66 [MHz], fO2=75 [MHz], and fO3=84 [MHz] are Allocated (hereinafter, referred to as “3FA”) with a center frequency fOA=75 [MHz] and band width (BW)=30 [MHz], and provides a filtered composite analog IF signal to first, second, and third BPFs.
The first, second, and third BPFs 121, 122, and 123 respectively separates, according to frequencies, analog IF signals from the 3FA composite analog IF signal that has passed through the 3FA BPF. Namely, the first BPF 121 filters the 3FA composite analog IF signal with fO1=66 [MHz] and BW=10 [MHz], and separates a first analog IF signal from the 3FA composite analog IF signal. The second BPF 122 filters the 3FA composite analog IF signal with fO2=75 [MHz] and BW=10 [MHz], and separates a second analog IF signal from the 3FA composite analog IF signal. The third BPF 123 filters the 3FA composite analog IF signal with fO3=84 [MHz] and BW=10 [MHz], and separates a third analog IF signal from the 3FA composite analog IF signal.
Meanwhile, each of the local oscillators 131, 132, and 133 generates the local frequency for down-conversion, and provides the generated local frequency to the relevant mixer. Namely, the first local oscillator 131 generates a first local frequency fL1, and provides the first local frequency fL1 to the first mixer 141. The second local oscillator 132 generates a second local frequency fL2, and provides the second local frequency fL2 to the second mixer 142. The third local oscillator 133 generates a third local frequency fL3, and provides the third local frequency fL3 to the third mixer 143. The first, second, and third local frequencies respectively correspond to the minimum frequency limits (or magnitudes) related to the first, second, and third analog IF signals. To cite an instance, in a case where the down-conversion to an IF signal of the center frequency fO=15 [MHz] is performed, then fL1=51 [MHz], fL21=60 [MHz], and fL3=69 [MHz]. Also, the local oscillator is embodied including a Phase-Locked Loop (PLL) in order to provide a stable frequency without being affected by the ambient environment (i.e., ambient circuits, ambient devices, temperature, weather, etc.).
Each of the mixers 141, 142, and 143 mixes the analog IF signal of fO=15 [MHz] provided after being separated from the 3FA composite analog IF signal according to each frequency and the local frequency fL provided from the local oscillator. Namely, the first mixer mixes the first analog IF signal provided from the first BPF and the first local frequency provided from the first local oscillator, and generates a first analog IF signal (i.e., fO=fO1−fL1=15 [MHz]) whose frequency is down-converted into the frequency corresponding to a difference (i.e., fO1−fL1) therebetween. The second mixer mixes the second analog IF signal provided from the second BPF and the second local frequency provided from the second local oscillator, and generates a second analog IF signal (i.e., fO=fO2−fL2=15 [MHz]) whose frequency is down-converted into the frequency corresponding to a difference (i.e., fO2−fL2) therebetween. The third mixer mixes the third analog IF signal provided from the third BPF and the third local frequency provided from the third local oscillator, and generates a third analog IF signal (i.e., fO=fO3−fL3=15 [MHz]) whose frequency is down-converted into the frequency corresponding to a difference (i.e., fO3−fL3) therebetween.
Each of the ADCs 151, 152, and 153 converts the analog signal of fO=15 [MHz] into a digital IF signal of n bits (n is a natural number) by using a sampling clock of, e.g., 60 [MHz]. Namely, the first, second, and third ADCs respectively convert the first, second, and third analog IF signals, all having fO=15 [MHz] provided from the first, second, and third mixers, into the first, second, and third digital IF signals, all having n bits and fO=15 [MHz], and respectively transmit the first, second, and third digital IF signals to the first, second, and third SerDeres.
The SerDeses 161, 162, and 163 converts parallel digital IF signals transmitted from the ADCs into serial signals, transmits converted digital IF signals to, e.g., channel cards, etc. Namely, the first SerDes 161 converts the first parallel digital IF signal (fO=15 [MHz]) transmitted from the first ADC into the serial signal, and transmits the converted first digital IF signal to the first channel card. The second SerDes 162 converts the second parallel digital IF signal (fO=15 [MHz]) transmitted from the second ADC into the serial signal, and transmits the converted second digital IF signal to the second channel card. The third SerDes 163 converts the third parallel digital IF signal (fO=15 [MHz]) transmitted from the third ADC into the serial signal, and transmits the converted third digital IF signal to the third channel card.
Still, as the number of down-conversion paths and local oscillators (i.e., PLL) increases by allocation of frequencies in the apparatus and the method for analog IF down-conversion according to the prior art, problems appear in that the apparatus becomes complex, and that it needs much time to debugging. Moreover, harmonic components by modulation can affect other frequencies, and, it is problematic that a group delay and the degradation of phase characteristics are caused in a case where a band-pass filter having excellent cut-off characteristics is utilized. Besides, in a case where control is performed by allocation of frequencies (e.g., in the case of a change to 1FA, 2FA, and 3FA), problems appear in that it is difficult to implement the control since a local output of a PLL can be generated.
In the meantime, owing to the rapid growth of technological development in a field of semiconductors, recently, an Analog-to-Digital Converter (ADC) and a DAC whose sampling rates are nearly 100 [Msps] have been developed, and accordingly, the direct digital conversion between an IF band signal and a baseband signal can be implemented. In addition, as the performances of digital signal processing devices such as a general-purpose Digital Signal Processor (DSP) and a Field Programmable Gate Array (FPGA) become excellent, it is possible to embody both a baseband modem that can be reconfigured in a form of software and an improved signal processing module.
However, despite the progress of digital signal processing technology, in a case where the apparatus for analog IF down-conversion according to the aforementioned prior art is directly embodied by an apparatus for digital IF conversion, as a system clock of high-frequency should be used in order to actualize a digital IF having high-frequency approaching 100 [MHz], there still exist problems such that the configuration and design of the apparatus are complex, and an embodiment thereof is difficult.
Accordingly, the present invention has been made to solve the above problems occurring in the prior art, and it is an aspect of the present invention to provide an apparatus and a method for digital frequency down-conversion, which separate digital IF signals from a composite digital IF signal including at least two frequencies according to each frequency, down-convert the digital IF signals into baseband signals respectively, up-convert the down-converted signals into signals having the predetermined reference frequencies coinciding with protocol, and output at least two digital IF signals.
Furthermore, it is another aspect of the present invention to provide an apparatus and a method for digital frequency down-conversion whose configuration and design are simple, and whose debugging is easy.
In accordance with one aspect of the present invention, there is provided an apparatus for digital frequency down-conversion according to an embodiment of the present invention, including: a first down-converter for receiving a composite digital signal having the center frequencies fO1 and fO2, which includes a first digital signal of the center frequency fO1 and a second digital signal of the center frequency fO2, and converting the first digital signal of the center frequency fO1 into a first baseband digital signal; a second down-converter for receiving the composite digital signal having the center frequencies fO1 and fO2, and converting the second digital signal of the center frequency fO2 into a second baseband digital signal; a first up-converter for receiving the first baseband digital signal from the first down-converter, and converting the received first baseband digital signal into a first digital signal of the reference center frequency fOU lower than the mean of the center frequencies fO1 and fO2; and a second up-converter for receiving the second baseband digital signal from the second down-converter, and converting the received second baseband digital signal into a second digital signal of the reference center frequency fOU lower than the mean of the center frequencies fO1 and fO2.
In accordance with another aspect of the present invention, there is provided an apparatus for digital frequency down-conversion according to an embodiment of the present invention, including: an Analog-to-Digital Converter (ADC) for converting a composite analog signal having at least two center frequencies into a composite digital signal having at least two center frequencies; a Field Programmable Gate Array (FPGA) for receiving the composite digital signal from the ADC, respectively down-converting at least two digital signals having each center frequency included in the composite digital signal into baseband digital signals, and respectively up-converting the baseband digital signals into digital signals having the reference center frequency; and a Serializer/Deserializer (SerDes) for converting the parallel digital signals of the reference center frequency provided from the FPGA into the serial digital signals of the reference center frequency.
In accordance with another aspect of the present invention, there is provided a method for digital frequency down-conversion according to an embodiment of the present invention, including the steps of: (a) separating first and second digital signals respectively having the center frequencies fO1 and fO2 from a composite digital signal having the center frequencies fO1 and fO2, and down-converting the composite digital signal having the center frequencies fO1 and fO2 into first and second baseband digital signals; and (b) up-converting the first and second baseband digital signals into first and second digital signals having the reference center frequency fOU lower than the center frequencies fO1 and fO2, respectively.
An apparatus and a method for digital frequency down-conversion according to the present invention, which separate digital IF signals from a composite digital IF signal including at least two frequencies according to each frequency, down-convert the digital IF signals into baseband signals, up-convert down-converted signals into signals having the predetermined frequencies, and output at least two digital IF signals. Accordingly, as the frequency of a system clock is lowered, power consumption and expenses can be reduced.
Also, the apparatus and the method for digital frequency down-conversion according to the present invention can prevent the deterioration of signal characteristics caused by harmonic components generated in the prior analog signal processing scheme by using the technology of digital signal processing, and therefore, can improve the quality of an output signal.
Moreover, it is simple to configure and design the apparatus for digital frequency down-conversion according to the present invention by using a Field-Programmable Gate Array (FPGA) that can be reconfigured, and accordingly, it is easy to debug the apparatus.
The above and other exemplary features, aspects, and advantages of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:
a to 3c are views illustrating a process for performing the digital frequency down-conversion by each frequency;
a and 7b are detailed flowcharts illustrating the method for digital frequency down-conversion illustrated in
Hereinafter, an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings. Well known functions and constructions are not described in detail since they would obscure the invention in unnecessary detail.
As illustrated in
For starters, the BPF 210 filters the 3FA composite analog signal of fO1=66 [MHz], fO2=75 [MHz], and fO3=84 [MHz] with fOA=75 [MHz] and BW=30 [MHz], and provides a filtered 3FA composite analog signal to the ADC 220.
Then, the ADC 220 converts the filtered 3FA composite analog signal into an n-bit (n is a natural number) 3FA (fO1=66 [MHz], fO2=75 [MHz], and fO3=84 [MHz]) composite digital signal having a data rate of about 120 [Mbps] by using a sampling clock of, e.g., 120 [MHz], and transmits a converted 3FA composite digital signal to the down-converters (refer to
The down-converters 231, 232, and 233 down-convert the 3FA composite digital signal provided from the ADC according to each FA (refer to
For this, each down-converter includes a down-conversion Numerically Controlled Oscillator (NCO), a down-conversion multiplier, and a Finite Impulse Response (FIR) filter.
Specifically, the first down-conversion NCO generates a local digital signal of a local frequency fLD1=66 [MHz], and provides the local digital signal of the local frequency fLD1 to the first down-conversion multiplier. The first down-conversion multiplier multiplies the 3FA composite digital signal of the center frequencies fO1, fO2, and fO3 by the local digital signal of the local frequency fLD1=66 [MHz], and generates a 3FA composite digital signal of the center frequencies 0 [Hz] (fO1−fLD1), 9 [MHz] (fO2−fLD1), and 18 [MHz] (fO3−fLD1). Then, the 3FA composite digital signal generated in this way passes through the first FIR filter with the center frequency of 0 [Hz] and BW=9 [MHz], which removes an FA2 component, an FA3 component, and harmonic components from the 3FA composite digital signal, and which generates a first baseband digital signal.
In the manner similar to this, the second down-conversion NCO generates a local digital signal of a local frequency fLD2=75 [MHz], and provides the local digital signal of the local frequency fLD2 to the second down-conversion multiplier. The second down-conversion multiplier multiplies the 3FA composite digital signal of the center frequencies fO1, fO2, and fO3 by the local digital signal of the local frequency fLD2=75 [MHz], and generates a 3FA composite digital signal of the center frequencies −9 [MHz] (fO1−fLD2), 0 [Hz] (fO2−fLD2), and 9 [MHz] (fO3−fLD2). Then, the 3FA composite digital signal generated in this way passes through the second FIR filter with the center frequency of 0 [Hz] and BW=9 [MHz], which removes an FAI component, an FA3 component, and harmonic components from the 3FA composite digital signal, and which generates a second baseband digital signal.
In addition, the third down-conversion NCO generates a local digital signal of a local frequency fLD3=84 [MHz], and provides the local digital signal of the local frequency fLD3 to the third down-conversion multiplier. The third down-conversion multiplier multiplies the 3FA composite digital signal of the center frequencies fO1, fO2, and fO3 by the local digital signal of the local frequency fLD3=84 [MHz], and generates a 3FA composite digital signal of the center frequencies −18 [MHz] (fO1−fLD3), −9 [MHz] (fO2−fLD3), and 0 [Hz] (fO3−fLD3). Then, the 3FA composite digital signal generated in this way passes through the third FIR filter with the center frequency of 0 [Hz] and BW=9 [MHz], which removes an FA1 component, an FA2 component, and harmonic components from the 3FA composite digital signal, and which generates a third baseband digital signal.
In the meantime, the up-converters 241, 242, and 243 up-convert the digital signals provided from the down-converters (refer to
For this, each up-converter includes an up-conversion NCO and an up-conversion multiplier. In detail, the first up-conversion NCO generates a local digital signal of a local frequency fLU1=15 [MHz], and provides the local digital signal of the local frequency fLU1 to the first up-conversion multiplier. The first up-conversion multiplier multiplies the first digital signal of the center frequency fOD1=0 [Hz] by the local digital signal of the local frequency fLU1=15 [MHz], and generates a first digital signal of the center frequency fOU1=fOD1+fLU1=15 [MHz]. Likewise, the second up-conversion NCO generates a local digital signal of a local frequency fLU2=15 [MHz], and provides the local digital signal of the local frequency fLU2 to the second up-conversion multiplier. The second up-conversion multiplier multiplies the second digital signal of the center frequency fOD2=0 [Hz] by the local digital signal of the local frequency fLU2=15 [MHz], and generates a second digital signal of the center frequency fOU2=fOD2+fLU2=15 [MHz]. The third up-conversion NCO generates a local digital signal of a local frequency fLU3=15 [MHz], and provides the local digital signal of the local frequency fLU3 to the third up-conversion multiplier. The third up-conversion multiplier multiplies the third digital signal of the center frequency fOD3=0 [Hz] by the local digital signal of the local frequency fLU3=15 [MHz], and generates a third digital signal of the center frequency fOU3=fOD3+fLU3=15 [MHz]. For reference, in the present embodiment, fOU=fOU1=fOU2=fOU3=15 [MHz] is applied to the reference center frequency that meets standard requirements.
Meanwhile, in a case where a digital signal corresponds to a complex signal, an In-phase (I) component and a Quadature-phase (Q) component are processed following the separation of the I and Q components from the complex signal, and following the performance of a required operation, the digital sum is performed by an I/Q adder. In
Lastly, the SerDeses 251, 252, and 253 convert digital IF signals provided in parallel from the up-converters into serial IF signals, and transmit converted digital IF signals to channel cards. Namely, the first, second, and third SerDeses convert the first, second, and third digital signals respectively having the center frequencies fOU1, fOU2, and fOU3 respectively provided from the first, second, and third up-converters in parallel into serial signals, and transmit converted first, second, and third digital signals to the channel cards, respectively.
As illustrated in
Herein, the BPF, the ADC, and the SerDeses are formed in the same manner as seen in the aforementioned description, and hereinafter, only the FPGA 430 will be described in detail.
The FPGA corresponds to an Integrated Circuit (IC) having a feature such that the FPGA can be used to be programmed as a user's requirement arises, and in the present invention, is configured to include down-converting modules, and up-converting modules.
The down-converting modules 431, 432, and 433 correspond to the down-converters illustrated in
ADC, according to each frequency, down-convert the IF digital signals into digital signals having the frequencies in the baseband. Namely, the first, second, and third down-converting modules 431, 432, 433 all receive the 3FA composite digital signal having the center frequencies fO1, fO2, and fO3, and respectively down-convert the received 3FA composite digital signal having the center frequencies fO1, fO2, and fO3 into first, second, and third digital signals respectively having the center frequencies fOD1, fOD2, and fOD3. For this, each down-converting module is configured to include a NCO function for down-conversion, a multiplying function for down-conversion, and a function of FIR filter.
The up-converting modules 441, 442, and 443 correspond to the up-converters illustrated in
An FPGA according to the present invention can be implemented by using Very high speed integrated circuit Hardware Description Language (VHDL), etc., and can be desirably accomplished by using a system generator of the MATLAB.
For starters, ‘Part (1)’ illustrated in
For reference, in the above embodiments, the description thereof has been made with setting the reference center frequency and the data rate of a digital signal provided to the outside (e.g., channel cards) to 15 [MHz] and 60 [Mbps], respectively, and the reference center frequency and the data rate corresponds to values that can be varied according to interface specifications.
Hereinafter, a method for digital frequency down-conversion according to the present invention will be described. As a specific process or the principles of a detailed operation can be understood with reference to the aforementioned description of the apparatus for digital frequency down-conversion, a detailed description of overlapping contents will be avoided, and a brief description will be made on the basis of steps generated in time series in the following.
First, in step S610, the BPF filters a 3FA composite analog signal having the center frequencies of fO1=66 [MHz] (FA1), fO2=75 [MHz] (FA2), and fO3=84 [MHz] (FA3) with fOA=75 [MHz] and BW=30 [MHz].
In step S620, the ADC converts the 3FA composite analog signal of 66 [MHz], 75 [MHz] and 84 [MHz] into a 3FA composite digital signal of 66 [MHz], 75 [MHz] and 84 [MHz].
In step S630, the first, second, and third down-converters down-convert the 3FA composite digital signal of 66 [MHz], 75 [MHz] and 84 [MHz] into first, second, and third baseband digital signals, respectively. Particularly, the first, second, and third down-conversion NCOs respectively generate first, second, and third local signals for down-conversion respectively having local frequencies fLD1=66 [MHz], fLD2=75 [MHz], and fLD3=84 [MHz] (S631). Then, the first, second, and third down-conversion multipliers respectively multiply the 3FA composite digital signal of 66 [MHz], 75 [MHz], and 84 [MHz] by the first, second, and third local signals for down-conversion respectively having the local frequencies fLD1=66 [MHz], fLD2=75 [MHz], and fLD3=84 [MHz] (S632). Multiplied signals are respectively filtered by the first, second, and third FIR filters, all having the center frequency of 0 [Hz] and BW=9 [MHZ], and then, first, second, and third baseband digital signals, all having the center frequency fOD1=fOD2=fOD3=0 [Hz], are produced.
Finally, in step S640, the first, second, and third up-converters respectively up-convert the first, second, and third baseband digital signals into first, second, and third digital signals, all having the center frequency fOU1=fOU2=fOU3=15 [MHz] (the reference center frequency: fOU). Particularly, the first, second, and third up-conversion NCOs respectively generate first, second, and third local signals for up-conversion, all having a local frequency fLU1=fLU2=fLU3=15 [MHz] (fLU) (S641). Then, the first, second, and third up-conversion multipliers respectively multiply the first, second, and third baseband digital signals, all having the center frequency fOD1=fOD2=fOD3=0 [Hz], by the first, second, and third local signals for up-conversion, all having the local frequency fLU1=fLU2=fLU3=15 [MHz] (fLU), and respectively generate first, second, and third digital signals, all having the center frequency fOU1=fOU2=fOU3=15 [MHz] (fOU) (S642).
While this invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiment and the drawings, but, on the contrary, it is intended to cover various modifications and variations within the spirit and scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10 2006 0029197 | Mar 2006 | KR | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/KR2007/001570 | 3/30/2007 | WO | 00 | 9/23/2008 |
