Patent Application
20090058475
The present invention relates to an apparatus and a method for digital frequency up-conversion, and more particularly to an apparatus and a method for up-converting respectively frequencies of digital Intermediate Frequency (IF) signals input through at least two paths, and then outputting IF signals to which at least two frequencies are allocated in a communication system.
As illustrated in
First, the SerDeses 111, 112, and 113 convert digital IF signals transmitted in series from channel cards into parallel signals, and transmit the converted digital IF signals to the DACs. Namely, the first SerDes 111 converts the first series digital IF signal transmitted from the first channel card into the parallel signal, and transmits the converted first digital IF signal to the first DAC 121. The second SerDes 112 converts the second series digital IF signal transmitted from the second channel card into the parallel signal, and transmits the converted second digital IF signal to the second DAC 122. The third SerDes 113 converts the third series digital IF signal transmitted from the third channel card into the parallel signal, and transmits the converted third digital IF signal to the third DAC 123.
Each of the first, second, and third digital IF signals correspond to a digital signal of n (n is a natural number) bits to which one Frequency is Allocated (hereinafter, referred to as “1 FA”). Hereinafter, to facilitate the following description, let the center frequency fO equal 15 [MHz].
The DAC 121, 122, and 123 converts digital IF signals of n bits, transmitted from SerDeses, into analog IF signals having fO=15 [MHz]. Namely, the first, second, and third DAC 121, 122, and 123 convert the first, second, and third digital IF signals provided from the first, second, and third SerDeses into the first, second, and third analog IF signals which respectively have the center frequencies of fO=15 [MHz], and provide the first, second, and third analog IF signals to the first, second, and third mixers.
Meanwhile, each of the local oscillators 131, 132, and 133 generate a local frequency for up-conversion, and provide the generated local frequency to the relevant mixer. Namely, the first local oscillator 131 generates a first local frequency fL1, and provides the first local frequency fL1 to the first mixer 141. The second local oscillator 132 generates a second local frequency fL2, and provides the second local frequency fL2 to the second mixer 142. The third local oscillator 133 generates a third local frequency fL3, and provides the third local frequency fL3 to the third mixer 143. The first, second, and third local frequencies correspond to maximum frequency limits (or magnitudes) related to the first, second, and third analog IF signals, respectively and in order to finally produce a composite analog IF signal to which three Frequencies are Allocated (hereinafter, referred to as “3 FA”), the first, second, and third local frequencies are set to different values. In the same manner, to facilitate the following description, let fL1, fL2, and fL3 equal 101 [MHz], 110 [MHz], and 119 [MHz], respectively. Also, the local oscillator is embodied including a Phase-Locked Loop (PLL) in order to provide the stable frequency without being affected by the ambient environment (i.e., ambient circuits, ambient devices, temperature, weather, etc.).
Each of the mixers 141, 142, and 143 mixes the analog IF signal of fO=15 [MHz] provided from the DAC and the local frequency fL provided from the local oscillator. Namely, the first mixer mixes the first analog IF signal from the first DAC and the first local frequency from the first local oscillator, and produces a first analog IF signal up-converted into the frequency corresponding to the sum (i.e., fO1=fO+fL1). The second mixer mixes the second analog IF signal from the second DAC and the second local frequency from the second local oscillator, and produces a second analog IF signal up-converted into the frequency corresponding to the sum (i.e., fO2=fO+fL2). The third mixer mixes the third analog IF signal from the third DAC and the third local frequency from the third local oscillator, and produces a third analog IF signal up-converted into the frequency corresponding to the sum (i.e., fO3=fO+fL3).
The analog IF signals provided from the mixers pass through band-pass filters 151, 152, and 153, which have excellent cut-off characteristics, and accordingly, harmonic components thereof are eliminated from the analog IF signals. Based on the above-stated assumption, e.g., the first band-pass filter 151 can be embodied to be fO1=116 [MHz] and Band Width (BW)=10 [MHz], the second band-pass filter 152 to be fO2=125 [MHz] and BW=10 [MHz], and the third band-filter 153 to be fO3=134 [MHz] and BW=10 [MHz].
The first, second, and third analog IF signals, which pass through the first, second, and third band-pass filters, are summed (i.e., analog summing) by the coupler 160, pass through a tail-end (e.g., a 3 FA band-pass filter 170 embodied with fOA=125 [MHz] and BW=30 [MHz]), and finally, a up-converted 3 FA composite analog IF signal is output.
Still, as the number of up-conversion paths and local oscillators (i.e., PLL) increases by allocation of frequencies FA in the apparatus and the method for analog IF up-conversion according to prior art, problems appear in that the apparatus becomes complex, and that it needs much time to perform debugging. Moreover, harmonic components by modulation can affect other frequencies, and, it is problematic that a group delay and the degradation of phase characteristics is caused in a case where a band-pass filter having excellent cut-off characteristics is utilized. Besides, in a case where control is performed by allocation of frequencies (e.g., in the case of a change to 1 FA, 2 FA, and 3 FA), problems appear in that it is difficult to implement the control since a local output of a PLL can be generated.
In the meantime, owing to the rapid growth of technological development in a field of semiconductors, recently, an Analog-to-Digital Converter (ADC) and a Digital-to-Analog Converter (DAC) whose sampling rates are nearly 100 [Msps] have been developed, and accordingly, the direct digital conversion between an IF band signal and a baseband signal can be implemented. In addition, as the performances of digital signal processing devices such as a general-purpose Digital Signal Processor (DSP) and a Field Programmable Gate Array (FPGA) become further improved, it is possible to embody both a baseband modem that can be reconfigured in a form of software and an improved signal processing module.
However, despite the progress of digital signal processing technology, in a case where the apparatus for analog IF up-conversion according to the aforementioned prior art is directly embodied by an apparatus for digital IF conversion, as a system clock of high-frequency should be used in order to actualize a digital IF having high-frequency approaching 100 [MHz], there still exist problems such that the configuration and design of the apparatus are complex, and an embodiment thereof is difficult.
Accordingly, the present invention has been made to solve the above problems occurring in the prior art, and it is an aspect of the present invention to provide an apparatus and a method for digital frequency up-conversion, which up-convert digital IF signals respectively input through at least two paths into digital signals respectively having relatively low frequencies, sum up up-converted digital signals, and output a composite IF signal to which at least two frequencies are allocated.
It is another aspect of the present invention to provide an apparatus and a method for digital frequency up-conversion, which down-convert digital IF signals respectively input through at least two paths into baseband signals, up-convert the baseband signals into signals having predetermined frequencies, sum up up-converted baseband signals, and output a composite IF signal to which at least two frequencies are allocated.
Furthermore, it is another aspect of the present invention to provide an apparatus and a method for digital frequency up-conversion whose configuration and design are simple, and whose debugging is easy.
In accordance with one aspect of the present invention, there is provided an apparatus for digital frequency up-conversion according to an embodiment of the present invention, including: a first down-converter for receiving a first digital signal of the center frequency fO1 and converting the received first digital signal into a first digital signal of the center frequency fOD1 lower than fO1; a second down-converter for receiving a second digital signal of the center frequency fO2 and converting the received second digital signal into a second digital signal of the center frequency fOD2 lower than fO2; a first up-converter for receiving a first digital signal of the center frequency fOD1 and converting the received first digital signal into a first digital signal of the center frequency fOU1 higher than fO1; a second up-converter for receiving a second digital signal of the center frequency fOD2 and converting the received second digital signal into a second digital signal of the center frequency fOU2 higher than fO2; and an signal adder for summing up the first digital signal of the center frequency fOU1 and the second digital signal of the center frequency fOU2, and outputting a composite digital signal having the center frequencies fOU1 and fOU2.
In accordance with another aspect of the present invention, there is provided an apparatus for digital frequency up-conversion according to an embodiment of the present invention, including: a Serializer/Deserializer (SerDes) for receiving at least two digital signals having a first center frequency fO in series and converting the received digital signals into parallel digital signals; a Field Programmable Gate Array (FPGA) for receiving at least two digital signals provided from the SerDes, respectively converting the received at least two digital signals into at least two digital signals having the second center frequency fOD lower than the first center frequency, respectively converting at least two digital signals having the second center frequency fOD into at least two digital signals respectively having the center frequencies higher than the first center frequency and different from each other, summing up at least two digital signals respectively having the center frequencies higher than the first center frequency and different from each other, and outputting a composite digital signal having the at least two center frequencies; a Digital-to-Analog Converter (DAC) for converting the composite digital signal having at least two center frequencies provided from the FPGA into a composite analog signal having at least two center frequencies higher than the center frequencies of the composite digital signal, and outputting the composite analog signal; and a band-pass filter for filtering the composite analog signal.
In accordance with another aspect of the present invention, there is provided an method for digital frequency up-conversion according to an embodiment of the present invention, including the steps of: (a) converting a first digital signal of the center frequency fO1 into a first digital signal of the center frequency fOD1 lower than fO1, and converting a second digital signal of the center frequency fO2 into a second digital signal of the center frequency fOD2 lower than fO2; (b) converting the first digital signal of the center frequency fOD1 into a first digital signal of the center frequency fOU1 higher than fO1, and converting the second digital signal of the center frequency fO2 into a second digital signal of the center frequency fOU2 higher than fO2; and (c) summing up the first digital signal of the center frequency fOU1 and the second digital signal of the center frequency fOU2, and generating a composite digital signal having the center frequencies fOU1 and fOU2.
An apparatus and a method for digital frequency up-conversion according to the present invention, first, down-convert the digital IF signals, up-convert down-converted digital IF signals into signals having relatively low frequencies, and sum up up-converted signals, in case of up-converting digital IF signals respectively input through at least two paths, and then, summing up up-converted digital signals. Accordingly, as the frequency of a system clock is lowered, power consumption and expenses can be reduced.
Also, the apparatus and a method for digital frequency up-conversion according to the present invention can prevent the deterioration of signal characteristics caused by harmonic components generated in the prior analog signal processing scheme by using the technology of digital signal processing, and therefore, can improve the quality of an output signal.
Moreover, it is simple to configure and design the apparatus for digital frequency up-conversion according to the present invention by using a Field-Programmable Gate Array (FPGA) that can be reconfigured, and accordingly, it is easy to debug the apparatus.
The above and other exemplary features, aspects, and advantages of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:
a to 3c are views illustrating a process for performing the digital frequency up-conversion by each frequency;
a and 5b are views illustrating examples in which the apparatus for digital frequency up-conversion illustrated in
a and 7b are detailed flowcharts illustrating the method for digital frequency up-conversion illustrated in
Hereinafter, an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings. Well known functions and constructions are not described in detail since they would obscure the invention in unnecessary detail.
As illustrated in
The SerDeses 211, 212 and 213 converts respectively a digital IF signal transmitted in series into a parallel signal, and a converted digital IF signal is provided to each down-converter. Namely, the first SerDes 211 converts a first digital signal of the center frequency fO1 transmitted in series into a parallel signal, and provides a converted first digital signal to the first down-converter. The second SerDes 212 converts a second digital signal of the center frequency fO2 transmitted in series into a parallel signal, and provides a converted second digital signal to the second down-converter. The third SerDes 213 converts a third digital signal of the center frequency fO3 transmitted in series into a parallel signal, and provides a converted third digital signal to the third down-converter. The first, second, and third digital signals can be provided from, e.g., first, second, and third channel cards, and correspond to digital signals of n (n is natural number) bits, having the center frequencies fO1, fO2, and fO3, respectively. Even though the center frequencies fO1, fO2, and fO3 are not necessarily set to the same value, the center frequencies fO1, fO2, and fO3 are usually set and use to the same value, and to facilitate a description to follow, in the present embodiment, the center frequencies fO1, fO2, and fO3 are all set to 15 [MHz] (the first center frequency: fO).
The down-converters 221, 222, and 223 down-converts respectively a frequency of digital signal provided from the SerDeses 211, 212 and 213 into a down-converted frequency (refer to
For this, each down-converter includes a down-conversion Numerically Controlled Oscillator (NCO), a down-conversion multiplier, and a Finite Impulse Response (FIR) filter. Specifically, the first down-conversion NCO generates a local digital signal of a local frequency fLD1, and provides the local digital signal of the local frequency fLD1 to the first down-conversion multiplier. The first down-conversion multiplier multiplies the first digital signal of the center frequency fO1 by the local digital signal of the local frequency fLD1, and generates a first digital signal of the center frequency fOD1=fO1−fLD1. Then, the first digital signal of the center frequency fOD1 generated in this way passes through the first FIR filter, which removes harmonic components from the first digital signal of the center frequency fOD1, and output characteristics of the first digital signal are matched. Similarly, the second down-conversion NCO generates a local digital signal of a local frequency fLD2 and provides the local digital signal of the local frequency fLD2 to the second down-conversion multiplier. The second down-conversion multiplier multiplies the second digital signal of the center frequency fO2 by the local digital signal of the local frequency fLD2, and generates a second digital signal of the center frequency fOD2=fO2−fLD2. Then, the second digital signal of the center frequency fOD2 generated in this way passes through the second FIR filter. The third down-conversion NCO generates a local digital signal of a local frequency fLD3, and provides the local digital signal of the local frequency fLD3 to the third down-conversion multiplier. The third down-conversion multiplier multiplies the third digital signal of the center frequency fO3 by the local digital signal of the local frequency fLD3, and generates a third digital signal of the center frequency fOD3=fO3−fLD3. Then, the third digital signal of the center frequency fOD3 generated in this way passes through the third FIR filter. Herein, in a case where fO1=fLD1, fO2=fLD2 and fO3=fLD3, each of fOD1, fOD2 and fOD3 becomes 0 [Hz], and the first, second, and third digital signals are down-converted into baseband signals. To facilitate a description to follow, in the present invention, fLD1, fLD2, and fLD3 are all set to 15 [MHz]. Therefore, fOD1=fOD2=fOD3=0 [Hz] (the second center frequency: fOD), the first, second, and third digital signals are down-converted into baseband signals.
The up-converters 231, 232, and 233 up-converts respectively the digital signals provided from the down-converters into up-converted signals (refer to
For this, each up-converter includes an up-conversion NCO and a up-conversion multiplier. In detail, the first up-conversion NCO generates a local digital signal of a local frequency fLU1, and provides the local digital signal of the local frequency fLU1 to the first up-conversion multiplier. The first up-conversion multiplier multiplies the first digital signal of the center frequency fOD1 by the local digital signal of the local frequency fLU1, and generates a first digital signal of the center frequency fOU1=fOD1+fLU1. Likewise, the second up-conversion NCO generates a local digital signal of a local frequency fLU2, and provides the local digital signal of the local frequency fLU2 to the second up-conversion multiplier. The second up-conversion multiplier multiplies the second digital signal of the center frequency fOD2 by the local digital signal of the local frequency fLU2, and generates a second digital signal of the center frequency fOU2=fOD2+fLU2. The third up-conversion NCO generates a local digital signal of a local frequency fLU3, and provides the local digital signal of the local frequency fLU3 to the third up-conversion multiplier. The third up-conversion multiplier multiplies the third digital signal of the center frequency fOD3 by the local digital signal of the local frequency fLU3, and generates a third digital signal of the center frequency fOU3=fOD3+fLU3. The local frequencies fLU1, fLU2, and fLU3 are respectively set to different values so as to finally generate a signal to which the three frequencies are allocated, and are desirably set so that fLU1, fLU2, and fLU3 may form an arithmetic progression. In the present invention, fLU1, fLU2, and fLU3 are respectively set to about 16 [MHz], 25 [MHz] and 34 [MHz], and because fOD1=fOD2=fOD3=0 [Hz], fOU1, fOU2 and fOU3 are respectively set to about 16 [MHz], 25 [MHz], and 34 [MHz]. Still, it will be apparent the center frequency of a signal generated in an embodiment of the present invention can be allowed in a certain error range according to ambient conditions or circumstances.
Meanwhile, in a case where a digital signal corresponds to a complex signal, an In-phase (I) component and a Quadrature-phase (Q) component are processed following the separation of the I and Q components from the complex signal, and following the performance of a required operation, the digital sum is performed by an I/Q adder. In
The signal adder 240 sums up the first digital signal of the center frequency fOU1 from the first up-converter, the second digital signal of the center frequency fOU2 from the second up-converter, and the third digital signal of the center frequency fOU3 from the third up-converter, and produces a 3 FA composite digital signal having the center frequencies fOU1, fOU2, and fOU3 (refer to
The 3FA composite digital signal having the center frequencies fOU1, fOU2, and fOU3 is transmitted to the DAC 250, and the DAC 250 converts the received 3FA composite digital signal into a 3FA composite analog signal having the center frequencies fOA1, fOA2, and fOA3. Specifically, the received 3FA composite digital signal is converted into an analog signal of a desired frequency bandwidth by adjusting sampling clock being used during digital-to-analog conversion, and through this, the secondary frequency up-conversion (fOA>fOU) can be performed. To cite an instance, in a case where a sampling clock of about fS=400 [MHz] is used, and where the up-conversion of about 100 [MHZ] is necessary, as a carrier of 100 [MHZ] is generated by dividing the sampling clock by 4 (i.e., fS/4 modulation), a 3FA composite analog signal (fOA1=116 [MHz], fOA2=125 [MHz], and fOA3=134 [MHz]) having the center frequencies (100 [MHz]+16 [MHz], (100[MHz]+25 [MHz]), and (100 [MHz]+34 [MHz]) can be generated.
The 3FA composite analog signal having the center frequencies fOA1, fOA2, and fOA3 is transmitted to the band-pass filter 260 (e.g., a Surface Acoustic wave (SAW) filter). The band-pass filter filters the transmitted 3FA composite analog signal, eliminates the carrier, and can obtain a desired 3FA analog signal having 116 [MHz] (FA1), 125 [MHz] (FA2), and 134 [MHz] (FA3).
As illustrated in
The FPGA corresponds to an Integrated Circuit (IC) having a feature such that the FPGA can be used to be programmed as a user's requirement arises, and in the present invention, is configured to include down-converting modules, up-converting modules, and a signal adding module.
The down-converting modules 421, 422, and 423 correspond to the down-converters illustrated in
The up-converting modules 431, 432, and 433 correspond to the up-converters illustrated in
Lastly, the signal adding module 440 corresponds to the signal adder illustrated in
A circuit configuration based on the FPGA can be implemented by using Very high speed integrated circuit Hardware Description Language (VHDL), etc., and can be desirably accomplished by using a system generator of the MATLAB.
For starters, ‘part (1)’ illustrated in
‘Part (2)’ illustrated in
Meanwhile, ‘part (1)’ illustrated in
For reference, in the above embodiments, the center frequency and the data rate of a digital signal inputted from the outside (e.g., channel cards) correspond to values that can be set according to interface specifications. In the case of the present embodiments, in order to process the digital signal having the center frequency of 15 [MHz] and the data rate of 60 [Mbps], the down-converter (i.e., down-converting module) uses a sampling clock of 240 [MHz]. However, since the data rate becomes 120 [Mbps] if the up-converter (i.e., up-converting module) uses the sampling clock of 240 [MHz], in a case where I/Q modulation is performed by the DAC, a carrier component of 120 [MHz] is generated in the final output. The carrier component of 120 [MHz] is in band of a 3FA frequency, and cannot be removed by a band-pass filter having the center frequency of 125 [MHz] and BW=30 [MHz]. So as to settle this, the present invention uses a method for varying system clocks of the down-converter (i.e., down-converting module) and the up-converter (i.e., up-converting module), and for changing the data rate. In particular, as previously mentioned, the down-converter (i.e., down-converting module) down-samples the digital signal having the data rate of 60 [Mbps] by three times, and changes the digital signal of 60 [Mbps] into the digital signal having the data rate of 20 [Mbps]. The up-converter (i.e., up-converting module) down-samples 100 [Mbps] by five times, and interfaces with the digital signal having the data rate of 20 [Mbps]. Therefore, if an output data rate of the up-converter (i.e., up-converting module) is set to 100 [Mbps], a carrier component of 100 [MHZ] is generated out-band of the 3FA frequency in the final output of the DAC, and this carrier component of 100 [MHZ] is eliminated by a band-pass filter.
Hereinafter, a method for digital frequency up-conversion according to the present invention will be described. As a specific process or the principles of a detailed operation can be understood with reference to the aforementioned description of the apparatus for digital frequency up-conversion, a detailed description of overlapping contents will be avoided, and a brief description will be made on the basis of steps generated in time series in the following.
First, in step S610, the first, second, and third down-converters respectively down-convert first, second, and third digital signals respectively having the center frequencies fO1, fO2, and fO3 into first, second, and third digital signals respectively having the center frequencies fOD1, fOD2, and fOD3. Particularly, the first, second, and third NCOs for down-conversion respectively generate first, second, and third local signals for down-conversion respectively having local frequencies fLD1, fLD2, and fLD3 (S611). Then, the first, second, and third multipliers for down-conversion respectively multiply the first, second, and third digital signals respectively having the center frequencies fO1, fO2, and fO3 by the first, second, and third local signals for down-conversion respectively having the local frequencies fLD1, fLD2, and fLD3 (S612). Multiplied signals are respectively filtered by the first, second, and third FIR filters, and then, first, second, and third digital signals respectively having the center frequencies fOD1, fOD2, and fOD3 are produced. In this case, if fOD1=fOD2=fOD3=0 Hz, the first, second, and third digital signals becomes baseband signals.
Furthermore, in step 620, the first, second, and third up-converters respectively up-convert the first, second, and third digital signals respectively having the center frequencies fOD1, fOD2, and fOD3 into first, second, and third digital signals respectively having the center frequencies fOU1, fOU2, and fOU3. Particularly, the first, second, and third NCOs for up-conversion respectively generate first, second, and third local signals for up-conversion respectively having local frequencies fLU1, fLU2, and fLU3 (S621). Then, the first, second, and third multipliers for up-conversion respectively multiply the first, second, and third digital signals respectively having the center frequencies fOD1, fOD2, and fOD3 by the first, second, and third local signals for up-conversion respectively having the local frequencies fLU1, fLU2, and fLU3, and respectively generate first, second, and third digital signals respectively having the center frequencies fOD1, fOD2, and fOD3 (S622).
In step S630, the signal adder sums up the first, second, and third digital signals respectively having the center frequencies fOD1, fOD2, and fOD3, generates a 3FA composite digital signal having the center frequencies fOU1, fOU2, and fOU3, and provides the 3FA composite digital signal to the DAC.
In step S640, the DAC converts the 3FA composite digital signal having the center frequencies fOU1, fOU2, and fOU3 into a 3FA composite analog signal having the center frequencies fOA1, fOA2, and fOA3, and at this time, performs the secondary up-conversion.
Lastly, in step S650, the band-pass filter filters the 3FA composite analog signal having the center frequencies fOA1, fOA2, and fOA3, eliminates a carrier from the 3FA composite analog signal, and obtains a 3FA (i.e., 116 [MHz], 125 [MHz], and 134 [MHz]) analog signal.
While this invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiment and the drawings, but, on the contrary, it is intended to cover various modifications and variations within the spirit and scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2006-0029196 | Mar 2006 | KR | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/KR2007/001566 | 3/30/2007 | WO | 00 | 9/23/2008 |
