Patent Application
20080192031
This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 2007-14644, filed on Feb. 13, 2007 in the Korean Intellectual Property Office (KIPO), the contents of which are herein incorporated by reference in their entirety.
1. Field of the Invention
The present disclosure is directed to an apparatus for driving a display panel. More particularly, the present disclosure is directed to an apparatus and a method for driving a display panel having a central processing unit (CPU) interface mode.
2. Description of the Related Art
Compact liquid crystal display (LCD) apparatuses have become widely used in various fields, so that various conditions and functions of the LCD apparatuses have also become necessary. For example, a compact LCD apparatus, such as a digital camera, a digital multimedia broadcasting (DMB) device, etc., requires high display resolution and high display quality.
However, since the compact LCD apparatus is primarily manufactured to display a still image, the response speed of liquid crystal is slow and the response speed of a gray scale is much slower. An overdriving technology is applied to maintain the response speed through the entire gray scale range to easily display the video image. In the overdriving technology, the present inputted frame image signal is compensated by comparing the present inputted frame image with an image signal in a frame unit. For example, an image signal of an (n-1)-th frame is compared with an image signal of an n-th frame next to the (n-1)-th frame, to output a compensated image signal of the (n-1)-th frame. Thus, the inputted image signal is synchronized with the outputted compensated image signal in the overdriving technology.
The current compact LCD apparatus stores the image signal that is synchronized with an externally provided clock signal received from an external system in a frame memory inside of the LCD apparatus via a central processing unit (CPU) interface process, and outputs the image signal that is synchronized with an internal clock signal generated inside of the LCD apparatus and is stored in the frame memory to a display panel.
Thus, the image signal is not transmitted from the external system in real time, so that the image signal received from the external system is not synchronized with the image signal applied to the display panel. Accordingly, the overdriving technology is not easily used in the compact LCD apparatus using the CPU interface process.
Embodiments of the present invention provide an apparatus for driving a display panel enhancing display quality of a moving image in a central processing unit (CPU) interface mode.
Embodiments of the present invention also provide a method for driving the display panel.
In an example apparatus for driving a display panel according to an embodiment of the present invention, the apparatus includes a timing control part, a line memory part, a frame memory part and an image compensation part. The timing control part receives an external horizontal synchronizing signal from an external system via a CPU interface process. The line memory part stores an image signal of an n-th frame transmitted from the external system in a line unit, based on the external horizontal synchronizing signal. The frame memory part stores an image signal of an (n-1)-th frame based on the external horizontal synchronizing signal. The image compensation part generates a compensated image signal of the n-th frame using the image signals of the n-th and (n-1)-th frames, which are respectively outputted from the line memory part and the frame memory part based on the external horizontal synchronizing signal. The number n is a natural number.
In another example apparatus for driving a display panel according to an embodiment of the present invention, the apparatus includes a clock generating part, a timing control part, a line memory part, a frame memory part and an image compensation part. The clock generating part generates an internal horizontal synchronizing signal and an internal vertical synchronizing signal. The timing control part transmits the internal horizontal synchronizing signal and the internal vertical synchronizing signal to an external system via a central processing unit (CPU) interface process. The line memory part stores an image signal of an n-th frame in a line unit, and the image signal of the n-th frame is synchronized with the internal horizontal synchronizing signal and is received from the external system. The frame memory part stores an image signal of an (n-1)-th frame based on the internal horizontal synchronizing signal. The image compensation part generates a compensated image signal of the n-th frame using the image signals of the n-th and (n-1)-th frames, which are respectively outputted from the line memory part and the frame memory part based on the internal horizontal synchronizing signal. The number n is a natural number.
In an example method for driving a display panel according to an embodiment of the present invention, an external horizontal synchronizing signal and an image signal of an n-th frame are received from an external system via a CPU interface process. The image signal of the n-th frame is stored in a line unit, based on the external horizontal synchronizing signal. The stored image signals of the (n-1)-th and the n-th frames are outputted based on the external horizontal synchronizing signal. A compensated image signal of the n-th frame is generated using the image signals of the n-th and (n-1)-th frames. The compensated image signal of the n-th frame is converted into an analog-type compensated image signal. The analog-type compensated image signal is outputted. The number n is a natural number.
In another example method for driving a display panel according to an embodiment of the present invention, an internal horizontal synchronizing signal and an internal vertical synchronizing signal are generated. The internal horizontal synchronizing signal and the internal vertical synchronizing signal are transmitted to an external system via a CPU interface process. An image signal of an n-th frame is stored in a line unit, and the image signal of the n-th frame is synchronized with the internal horizontal synchronizing signal and is received from the external system. The stored image signals of the (n-1)-th and n-th frames are outputted based on the internal horizontal synchronizing signal. A compensated image signal of the n-th frame is generated using the image signals of the n-th and (n-1)-th frames. The compensated image signal of the n-th frame is converted into an analog-type compensated image signal. The analog-type compensated image signal is outputted. The number n is a natural number.
According to an embodiment of the present invention, a compact display apparatus using a CPU interface process includes a line memory part storing an image signal in a line unit, so that the image signals of the (n-1)-th and n-th frames are synchronized with each other to generate a compensated image signal of the n-th frame.
The above and other features of the present invention will become more apparent by describing in detail example embodiments thereof with reference to the accompanying drawings.
Embodiments of the invention is described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. It will be understood that when an element or layer is referred to as being “on,” “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. Like numbers refer to like elements throughout.
Hereinafter, exemplary embodiments of the present invention will be explained in detail with reference to the accompanying drawings.
Referring to
The FPC electrically connects an external system (not shown) with the apparatus 200 for driving the display panel 100. The external system is connected to the apparatus 200 via a central processing unit (CPU) interface process, to receive and transmit an image signal and a control signal.
The display panel 100 includes a display area DA having a plurality of pixel portions and a peripheral area PA enclosing the display area DA. Each of the pixel portions P includes a switching element TFT electrically connected to a gate line GL and a source line DL, a liquid capacitor CLC electrically connected to the switching element TFT and a storage capacitor CST electrically connected to the liquid capacitor CLC.
The apparatus 200 and a gate driving part 110 are disposed in the peripheral area PA. The apparatus 200 is mounted on the peripheral area PA corresponding to an end portion of the source line DL in a chip shape. The gate driving part 110 is integrated in the peripheral area PA corresponding to an end portion of the gate line GL, or is mounted on the peripheral area PA in the chip shape.
The apparatus 200 generates a compensated image signal of an n-th frame using an image signal of the n-th frame transmitted via the CPU interface process and a stored image signal of an (n-1)-th frame, and outputs the compensated image signal of the n-th frame to the source line. The number n is a natural number.
The gate driving part 110 outputs a gate signal to each of the gate lines, based on a gate control signal provided from the apparatus 200.
Referring to
The timing control part 210 outputs a control signal controlling the apparatus 200a, based on an external clock signal ECK and an external horizontal synchronizing signal EHS transmitted from the external system via the CPU interface process. The control signal includes a source control signal 210d controlling the line memory part 230, the frame memory part 240, the image compensation part 250 and the source driving part 260, and a gate control signal 210g controlling the gate control part 270.
The resistor 213 records a start point of a frame image signal using the external horizontal synchronizing signal EHS. The clock generating part 215 generates an internal vertical synchronizing signal IVS based on the start point of the frame image recorded in the resistor 213, and transmits the internal vertical synchronizing signal IVS to the timing control part 210. Thus, the timing control part 210 generates the source control signal 210d and the gate control signal 210g, based on the external clock signal ECK, the external horizontal synchronizing signal EHS and the internal vertical synchronizing signal IVS.
The voltage generating part 220 generates driving voltages depending on a control of the timing control part 210. The driving voltages includes a gate voltage VL and VH applied to the gate control part 270, a reference gamma voltage VREF applied to the source driving part 260 and a common voltage VCOM applied to the display panel 100.
The line memory part 230 stores the image signal Fn_DATA of the n-th frame Fn, which is transmitted from the external system, in a line unit, based on the source control signal 210d synchronized with the external horizontal synchronizing signal EHS, and outputs the image signal of the n-th frame Fn to the image compensation part 250 in the line unit and the frame memory part 240. The line memory part 230 may be a line latch or a line memory, and may store at least more than two lines of the image signal.
The frame memory part 240 outputs the stored image signal of the (n-1)-th frame Fn-1 to the image compensation part 250 in the line unit, based on the source control signal 210d synchronized with the external horizontal synchronizing signal EHS, and stores the image signal of the n-th frame Fn outputted from the line memory part 230.
For example, when a k-th line image signal of the n-th frame Fn is stored in the line memory part 230, the line memory part 230 outputs the k-th line image signal of the n-th frame to the image compensation part 250 and stores the k-th line image signal of the n-th frame in the frame memory part 240. The frame memory part 240 outputs the k-th line image signal of the (n-1)-th frame Fn-1 to the image compensation part 250.
The k-th line image signal 230L of the n-th frame Fn and the k-th line image signal 240L of the (n-1)-th frame Fn-1 are inputted to image compensation part 250. The image compensation part 250 includes a look-up table (LUT) in which a compensated image signal or an operation parameter is mapped corresponding to the image signal of the (n-1)-th frame and the image signal of the n-th frame. The image compensation part 250 generates the k-th line compensated image signal Fn′ of the n-th frame using the LUT, and outputs the compensated image signal Fn′ to the source driving part 260.
The source driving part 260 converts the compensated image signal in the line unit into an analog-type compensated image signal D1, D2, . . . , Dk, and outputs the analog-type compensated image signal to the source lines of the display panel 100. The number k is a natural number.
The gate control part 270 shifts levels of the gate control signal 210g provided from the timing control part 210 and the gate voltage VL and VH provided from the voltage generating part 220, to apply the gate control signal 210g and the gate voltage VL and VH to the gate driving part 110. For example, a vertical start signal STV, a first clock signal CK, a second clock signal CKB, a gate on voltage VDD and a gate off voltage VSS are applied to the gate driving part 110.
Referring to
The timing control part 210 generates a control signal synchronized with an external clock signal ECK, an external vertical synchronizing signal EHS and an external vertical synchronizing signal EVS transmitted from an external system via the CPU interface process, to control the apparatus 200b.
For example, the apparatus 200b further receives the external vertical synchronizing signal EVS from the external system. Thus, the apparatus 200b does not need to generate an internal vertical synchronizing signal IVS using a resistor 213, as in the apparatus 200a according to the previous example embodiment.
The voltage generating part 220, the line memory part 230, the frame memory part 240, the image compensation part 250, the source driving part 260 and the gate control part 270 according to the present example embodiment operate in substantially the same manner as in the first example embodiment. Thus, any further repetitive explanation concerning the above elements will be omitted.
Referring to
When the k-th line image signal of the n-th frame Fn is stored in the line memory part 230, a k-th line image signal 230L of the n-th frame Fn is outputted to an image compensation part 250 (step S420).
A frame memory part 240 outputs the stored k-th line image signal 240L of the (n-1)-th frame Fn-1, which is synchronized with an external vertical synchronizing signal EHS, to the image compensation part 250 (step S420).
The image compensation part 250 outputs a k-th line compensated image signal Fn′ of the n-th frame using the k-th line image signal 230L of the n-th frame Fn and a k-th line image signal 240L of an (n-1)-th frame Fn-1 (step S430).
A source driving part 260 converts the k-th line compensated image signal Fn′ of the n-th frame into an analog-type compensated image signal D1, D2, . . . , Dk, using a reference gamma voltage VREF (step S440).
The source driving part 260 outputs the analog-type k-th line compensated image signal D1, D2, . . . , Dk of the n-th frame to the source lines (step S450).
A gate driving part 110 outputs a gate signal to gate lines of a display panel 100, based on a control of a timing control part 210. When the k-th line compensated image signal Fn′ is outputted to the source lines, the gate signal is applied to the gate line GLk corresponding to the k-th line. Thus, a compensated image is displayed on the display panel 100 based on the compensated image signal (step S460).
Referring to
The timing control part 210 generates a control signal synchronized with an external clock signal ECK and an external vertical synchronizing signal EHS transmitted from an external system via the CPU interface process, to control the apparatus 200c. The control signal includes a source control signal 210d controlling the line memory part 230, the frame memory part 240, the image compensation part 250 and the source driving part 260, and a gate control signal 210g controlling a gate control part 270.
A resistor 213 records a start point of the frame image signal using the external vertical synchronizing signal EHS.
The clock generating part 215 generates an internal vertical synchronizing signal IVS using the start point of the frame image signal recorded in the resistor 213. The clock generating part 215 divides the external vertical synchronizing signal EHS to generate a pixel clock signal PCK.
The clock generating part 215 applies the internal vertical synchronizing signal IVS and the pixel clock signal PCK to the timing control part 210. Accordingly, the timing control part 210 generates a source control signal 210d and a gate control signal 210g based on the external clock signal ECK, the external horizontal synchronizing signal EHS, the internal vertical synchronizing signal IVS and the pixel clock signal PCK.
The voltage generating part 220 generates driving voltages based on a control of the timing control part 210. The driving voltages includes gate voltages VL and VH applied to the gate control part 270, a reference gamma voltage VREF applied to the source driving part 260, a common voltage VCOM applied to the display panel 100.
The line memory part 230 stores the Fn image signal Fn_DATA of the n-th frame in the line unit transmitted from the external system based on the source control signal 210d synchronized with the external horizontal synchronizing signal EHS and the pixel clock signal PCK, and outputs the image signal of the n-th frame Fn to the image compensation part 250 in a pixel unit and the frame memory part 240.
The frame memory part 240 outputs the stored image signal of the (n-1)-th frame Fn-1 based on the source control signal 210d synchronized with the external horizontal synchronizing signal EHS and the pixel clock signal PCK to the image compensation part 250 in the pixel unit. In addition, the frame memory part 240 stores the image signal of the n-th frame Fn outputted from the line memory part 230.
For example, after the k-th line image signal of the n-th frame Fn is stored in the line memory part 230, the line memory part 230 outputs an k-th line pixel image signal 230P of the n-th frame to the image compensation part 250. The frame memory part 240 outputs a k-th line pixel image signal 240P of the (n-1)-th frame Fn-1 to the image compensation part 250.
The pixel image signal 230P of the n-th frame Fn and the pixel image signal 240P of the (n-1)-th frame Fn-1 are inputted to the image compensation part 250. The image compensation part 250 outputs a pixel compensated image signal Fn′ of the n-th frame, which corresponds to the pixel image signal 230P of the n-th frame, and the pixel image signal 240P of the (n-1)-th frame to the source driving part 260.
The source driving part 260 groups the compensated image signal in the pixel unit into the compensated image signal in the line unit, and converts the compensated image signal in the line unit into the analog-type compensated image signal D1, D2, . . . , Dk, to output the analog-type compensated image signal to the source lines of the display panel 100.
The gate control part 270 shifts levels of a gate control signal 210g provided from the timing control part 210 and the gate voltage VL and VH provided from the voltage generating part 220, to apply the gate control signal 210g and the gate voltage VL and VH to the gate driving part 110. For example, a vertical start signal STV, a first clock signal CK, a second clock signal CKB, a gate on voltage VDD and a gate off voltage VSS are applied to the gate driving part 110.
Referring to
The timing control part 210 generates an external clock signal ECK received from an external system, and a control signal synchronized with an external horizontal synchronizing signal EHS and an external vertical synchronizing signal EVS, to control the apparatus 200d.
For example, the apparatus 200d further receives the external vertical synchronizing signal EVS from the external system in comparison with the apparatus 200b according to a previous example embodiment. Thus, the apparatus 200d does not need to generate the internal vertical synchronizing signal IVS using the resistor 213, as in the apparatus 200c according to another previous example embodiment.
The clock generating part 215 generating a pixel clock signal PCK, the voltage generating part 220, the line memory part 230, the frame memory part 240, the image compensation part 250, the source driving part 260 and the gate control part 270 according to the present example embodiment operate in substantially the same manner as in the example embodiment of
The image signal is compensated in the line unit in the example embodiments of
Referring to
When the k-th line image signal of the n-th frame Fn is stored in the line memory part 230, the k-th line image signal of the n-th frame Fn, which is synchronized with a pixel clock signal PCK generated by dividing an external horizontal synchronizing signal EHS, is outputted in the pixel unit. For example, the line memory part 230 outputs a pixel image signal 230P of the n-th frame Fn to an image compensation part 250 (step S520).
A frame memory part 240 outputs the stored k-th line image signal of an (n-1)-th frame Fn-1, which is synchronized with the pixel clock signal PCK in the pixel unit. For example, the frame memory part 240 outputs the pixel image signal 240P of the (n-1)-th frame Fn-1 to the image compensation part 250 (step S520).
The image compensation part 250 outputs the pixel compensated image signal Fn′ of the n-th frame using the pixel image signal 230P of the n-th frame Fn and the Fn-1 pixel image signal 240P of the (n-1)-th frame (step S530).
The source driving part 260 groups the pixel compensated image signal Fn′ of the n-th frame in a line unit, and converts a compensated image signal Fn′ of the n-th frame into an analog-type compensated image signal D1, D2, . . . , Dk using a reference gamma voltage VREF (step S540).
A source driving part 260 outputs the analog-type k-th line compensated image signal D1, D2, . . . , Dk of the n-th frame to the source lines (step S550).
A gate driving part 110 outputs a gate signal to gate lines of a display panel 100 based on a control of the timing control part 210. When the k-th line compensated image signal Fn′ is outputted to source lines, the gate signal is applied to the gate line GLk corresponding to the k-th line. Thus, a compensated image is displayed on the display panel 100 based on the compensated image signal (step S560).
Referring to
The timing control part 210 transmits an internal horizontal synchronizing signal IHS and an internal vertical synchronizing signal IVS generated from the clock generating part 215 to an external system. The external system transmits an image signal Fn_DATA synchronized with the internal horizontal synchronizing signal IHS and the internal vertical synchronizing signal IVS to the apparatus 200e.
The timing control part 210 generates a control signal synchronized with the internal horizontal synchronizing signal IHS and the internal vertical synchronizing signal IVS, to control the apparatus 200e. The control signal includes a source control signal 210d controlling the line memory part 230, the frame memory part 240, the image compensation part 250 and the source driving part 260, and a gate control signal 210g controlling the gate control part 270.
The voltage generating part 220 generates driving voltages based on the control of the timing control part 210. The driving voltages includes gate voltages VL and VH applied to the gate control part 270, a reference gamma voltage VREF applied to the source driving part 260 and a common voltage VCOM applied to the display panel 100.
The line memory part 230 stores the image signal of the n-th frame Fn, which is synchronized with the internal horizontal synchronizing signal IHS and the internal vertical synchronizing signal IVS and is received from the external system, in a line unit. The line memory part 230 outputs the Fn image signal of the n-th frame to the image compensation part 250 in the line unit and the frame memory part 240.
The frame memory part 240 outputs the stored image signal of an (n-1)-th frame Fn-1 to the image compensation part 250 in the line unit, based on a source control signal 210d synchronized with the internal horizontal synchronizing signal IHS and the internal vertical synchronizing signal IVS. In addition, the image signal of the n-th frame Fn outputted from the line memory part 230 is stored in the frame memory part 240.
For example, after the k-th line image signal of the n-th frame Fn is stored in the line memory part 230, the line memory part 230 outputs the k-th line image signal of the n-th frame to the image compensation part 250, and the k-th line image signal of the n-th frame is stored in the frame memory part 240. The frame memory part 240 outputs the k-th line image signal of the (n-1)-th frame Fn-1 to the image compensation part 250.
The k-th line image signal 230L of the n-th frame Fn and the k-th line image signal 240L of the (n-1)-th frame Fn-1 are inputted to the image compensation part 250. The image compensation part 250 includes an LUT in which the compensated image signal or the operating parameter is mapped corresponding to the image signal of the (n-1)-th frame and the image signal of the n-th frame. The image compensation part 250 outputs the k-th line compensated image signal Fn′ of the n-th frame to the source driving part 260 using the LUT.
The source driving part 260 converts the compensated image signal in the line unit into an analog-type compensated image signal D1, D2, . . . , Dk, to output the analog-type compensated image signal to the source lines of a display panel 100. The number k is a natural number.
The gate control part 270 shifts a level of a gate control signal 210g provided from the timing control part 210 and the gate voltage VL and VH provided from the voltage generating part 220, to apply the gate control signal 210g and the gate voltage VL and VH to the gate driving part 110. For example, a vertical start signal STV, a first clock signal CK, a second clock signal CKB, a gate on signal VDD and a gate off signal VSS are applied to the gate driving part 110.
Referring to
In the apparatus 200e, a line memory part 230 stores a k-th line image signal of an n-th frame Fn, which is synchronized with the internal horizontal synchronizing signal IHS and the internal vertical synchronizing signal IVS and is received from an external system via the CPU interface process (step S620).
When the k-th line image signal of the n-th frame Fn is stored in the line memory part 230, the k-th line image signal 230L of the n-th frame Fn, which is synchronized with the internal horizontal synchronizing signal IHS, is outputted to the image compensation part 250 (step S630).
A frame memory part 240 outputs the stored k-th line image signal 240L of the (n-1)-th frame Fn-1, which is synchronized with the internal horizontal synchronizing signal IHS, to an image compensation part 250 (step S630).
The image compensation part 250 outputs the k-th line compensated image signal Fn′ of the n-th frame using a k-th line image signal 230L of the n-th frame Fn and the k-th line image signal 240L of the (n-1)-th frame Fn-1 (step S640).
A source driving part 260 converts the k-th line compensated image signal Fn′ of the n-th frame into an analog-type compensated image signal D1, D2, . . . , Dk using a reference gamma voltage VREF (step S650).
The source driving part 260 outputs the analog-type n-th frame k-th line compensated image signal D1, D2, . . . , Dk to the source lines (step S660).
A gate driving part 110 applies a gate signal to the gate line corresponding to the k-th line, when the k-th line compensated image signal Fn′ is outputted to source lines. Thus, a compensated image is displayed on a display panel 100 based on the compensated image signal (step S670).
Referring to
The timing control part 210 transmits an internal horizontal synchronizing signal IHS, an internal vertical synchronizing signal IVS and a pixel clock signal PCK generated from the clock generating part 215, to an external system.
The external system transmits an image signal Fn_DATA synchronized with the internal horizontal synchronizing signal IHS, the internal vertical synchronizing signal IVS and the pixel clock signal PCK to the apparatus 200e. For example, in the present example embodiment, the pixel clock signal PCK is further transmitted to the external system, so that the image signal transmitted from the external system is synchronized in the pixel unit.
The timing control part 210 generates the control signal synchronized with the internal horizontal synchronizing signal IHS, the internal vertical synchronizing signal IVS and the pixel clock signal PCK, to control the apparatus 200f. The control signal includes a source control signal 210d controlling the line memory part 230, the frame memory part 240, the image compensation part 250 and the source driving part 260 processing the image signal, and a gate control signal 210g controlling the gate control part 270.
The voltage generating part 220 generates the driving voltages based on the control of the timing control part 210. The driving voltages includes gate voltages VL and VH applied to the gate control part 270, a reference gamma voltage VREF applied to the source driving part 260, and a common voltage VCOM applied to the display panel 100.
The line memory part 230 stores the image signal of the n-th frame Fn, which is synchronized with the internal horizontal synchronizing signal IHS, the internal vertical synchronizing signal IVS and the pixel clock signal PCK and is received from the external system, in the line unit. The line memory part 230 outputs the image signal of the n-th frame Fn to the image compensation part 250 in the pixel unit and the frame memory part 240.
The frame memory part 240 outputs the stored image signal of the (n-1)-th frame Fn-1 to the image compensation part 250 in the pixel unit, based on the source control signal 210d synchronized with the pixel clock signal PCK, and stores the image signal of the n-th frame Fn, which is outputted from the line memory part 230.
For example, after the k-th line image signal of the n-th frame Fn is stored in the line memory part 230, the line memory part 230 outputs the k-th line pixel image signal 230P of the n-th frame to the image compensation part 250. The frame memory part 240 outputs the k-th line pixel image signal 240P of the (n-1)-th frame Fn-1 to the image compensation part 250.
The n-th frame Fn pixel image signal 230P and the pixel image signal 240P of the (n-1)-th frame Fn-1 are inputted to the image compensation part 250. The image compensation part 250 includes an LUT in which the compensated image signal or the operating parameter is mapped corresponding to the image signal of the (n-1)-th frame and the image signal of the n-th frame. The image compensation part 250 outputs the pixel compensated image signal Fn′ of the n-th frame to the source driving part 260 corresponding to the pixel image signal 230P of the n-th frame and the pixel image signal 240P of the (n-1)-th frame using the LUT.
The source driving part 260 groups the compensated image signal Fn′ in the pixel unit into the compensated image signal in the line unit, and converts the compensated image signal in the line unit into an analog-type compensated image signal D1, D2, . . . , Dk, to output the compensated image signal in the line unit to the source lines of the display panel 100.
The gate control part 270 shifts the level of the gate control signal 210g provided from the timing control part 210 and the gate voltage VL and VH provided from the voltage generating part 220, to apply the gate control signal 210g and the gate voltage VL and VH to the gate driving part 110. For example, a vertical start signal STV, a first clock signal CK, a second clock signal CKB, a gate on voltage VDD and a gate off voltage VSS are inputted to the gate driving part 110.
Referring to
In the apparatus 200f, a line memory part 230 stores a k-th line image signal of an n-th frame Fn that is synchronized with the internal horizontal synchronizing signal IHS, the internal vertical synchronizing signal IVS and the pixel clock signal PCK and is received from an external system via the CPU interface process (step S720).
When the k-th line image signal of n-th frame Fn is applied to the line memory part 230, the k-th line image signal of the n-th frame Fn, which is synchronized with the pixel clock signal PCK, is outputted in the pixel unit. For example, the line memory part 230 outputs a pixel image signal 230P of the n-th frame Fn to an image compensation part 250 (step S730).
A frame memory part 240 outputs the stored k-th line image signal of the (n-1)-th frame Fn-1, which is synchronized with the pixel clock signal PCK in the pixel unit. For example, the frame memory part 240 outputs the pixel image signal 240P of the (n-1)-th frame Fn-1 to the image compensation part 250 (step S730).
The image compensation part 250 outputs a pixel compensated image signal Fn′ of the n-th frame using the pixel image signal 230P of the n-th frame Fn and the pixel image signal 240P of the (n-1)-the frame Fn-1 (step S740).
A source driving part 260 groups the pixel compensated image signal Fn′ of the n-th frame into the line unit, and converts the compensated image signal Fn′ of the n-th frame in the line unit into an analog-type compensated image signal D1, D2, . . . , Dk using a reference gamma voltage VREF (step S750).
The source driving part 260 outputs the analog-type k-th line compensated image signal D1, D2, . . . , Dk of the n-th frame to source lines (step S760).
The gate driving part 110 outputs a gate signal to gate lines of a display panel 100 based on a control of timing control part 210. When the k-th line compensated image signal Fn′ is outputted to the source lines, the gate signal is applied to the gate line GLk corresponding to the k-th line. Thus, a compensated image is displayed on the display panel 100 based on the compensated image signal (step S770).
According to embodiments of the present invention, a compact display apparatus using a CPU interface process includes a line memory part storing an image signal in a line unit, so that an image signal of an (n-1)-th frame is synchronized with an image signal of an n-th frame to generate a compensated image signal of the n-th frame. Thus, video display quality may be enhanced in the compact display apparatus using the CPU interface process.
Having described example embodiments of the present invention and their features, it is noted that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2007-14644 | Feb 2007 | KR | national |
