Patent Grant
9111476
This application claims the benefit of the Korean Patent Application No. 10-2011-0120526, filed on Nov. 17, 2011, which is hereby incorporated by reference as if fully set forth herein.
1. Field of the Disclosure
The present disclosure relates to an image display device, and more particularly, to an apparatus and method for driving an image display device, which are capable of achieving synchronous driving of driving integrated circuits for driving an image display panel, through internal generation of drive control signals, thereby preventing a degradation in picture quality caused by erroneous driving timing and achieving an enhancement in product reliability.
2. Discussion of the Related Art
Recently, image display devices of various types have been proposed as a means for displaying digital content. Of the proposed image display devices, flat display devices are most generally used. Flat display devices include, for example, a liquid crystal display device, an organic light emitting display device, a field emission display device, a plasma display panel.
In a general image display device, in which a plurality of pixels is arranged on a display panel, an image is displayed through adjustment of light transmittance or light emission amount of each pixel. To this end, the pixels are arranged in a matrix array in the display panel, and driving circuits are provided in the image display device, to drive the display panel.
In such an image display device, for example, data integrated circuits, which are included in the driving circuits of the image display device, to constitute a data driver, may be attached to at least one source printed circuit board, printed circuit film or the like or may be directly mounted on the display panel. Also, gate integrated circuits may be separately attached to one side of the display panel or may be directly formed on the display panel. Meanwhile, in the case of a timing controller to control the above-mentioned driving integrated circuits or a graphic system, the timing controller is separately provided at a separate control printed circuit board, system board or the like, to supply driving control signals required in the gate and data integrated circuits.
Recently, a proposal to integrate a timing controller and a data driving integrated circuit in the form of a single chip has been made, for application of a one-chip-integrated driving integrated circuit. However, for application of plural one-chip-integrated driving integrated circuits, there is a problem in that the plural driving integrated circuits should be synchronously driven, even though they internally generate driving control signals for driving thereof. In other words, synchronous driving of the driving integrated circuits is possible when the same synchronizing signals are externally supplied to the plural driving integrated circuits, which, in turn, generate driving control signals for driving thereof, respectively. When the driving integrated circuits internally generate driving control signals without external synchronizing signals, it is difficult to achieve synchronization of the driving integrated circuits. For this reason, in conventional cases, there may be a degradation in picture quality caused by erroneous driving timing and a degradation in product reliability caused by a degradation in picture quality.
An apparatus for driving an image display device includes a display panel, which includes a plurality of pixel regions, to display an image, a plurality of data integrated circuits, which share at least one of synchronizing signals internally generated therefrom, generate gate and data control signals in accordance with the shared synchronizing signal, and drive data lines of the display panel, using the internally-generated data control signals, and a gate driver for driving gate lines of the display panel in accordance with the gate control signal generated from one of the plural data integrated circuits.
In another aspect of the present invention, a method for driving an image display device includes sharing, by a plurality of data integrated circuits, at least one of synchronizing signals internally generated from the plural data integrated circuits, internally generating gate and data control signals from the plural data integrated circuits in accordance with the shared synchronizing signal, and driving data lines of a display panel, using the internally-generated data control signals, and driving gate lines of the display panel in accordance with the gate control signal of one of the plural data integrated circuits.
It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and along with the description serve to explain the principle of the invention. In the drawings:
Reference will now be made in detail to the preferred embodiments of the present invention relating to an apparatus and method for driving an image display device, examples of which are illustrated in the accompanying drawings. The image display device may be a liquid crystal display device, an organic light emitting display device, a field emission display device, a plasma display panel, or the like. For convenience of description, however, the following description will be given only in conjunction with a liquid crystal display device.
The driving apparatus shown in
The liquid crystal panel 2 is divided into an image display area, on which pixel regions defined by the gate lines GL1 to GLn and data lines DL1 to DLm are formed in the form of a matrix array, to display an image, and an image non-display area, on which no image is displayed. The liquid crystal panel 2 includes a thin film transistor (TFT) formed on each pixel region on the image display area, and a liquid crystal capacitor Clc connected to the TFT. The liquid crystal capacitor Clc includes a pixel electrode connected to the TFT, and a common electrode facing the pixel electrode such that a liquid crystal layer is interposed between the pixel electrode and the common electrode. The TFT supplies, to the pixel electrode, an image signal from a corresponding one of the data lines DL1 to DLm in response to a scan pulse from a corresponding one of the gate lines GL1 to GLn. The liquid crystal capacitor Clc is charged with a difference voltage between the image signal supplied to the pixel electrode and a common voltage supplied to the common electrode. The alignment of liquid crystal molecules is varied in accordance with the difference voltage and, as such, light transmittance of the pixel region is adjusted. Thus, a desired grayscale is obtained. A storage capacitor Cst is connected to the liquid crystal capacitor Clc in parallel, to allow the voltage charged in the liquid crystal capacitor Clc to be maintained until a next data signal is supplied. The storage capacitor Cst is formed in accordance with overlap of the pixel electrode and the gate line preceding the gate line corresponding to the pixel electrode under the condition that an insulating film is interposed between the pixel electrode and the preceding gate line. Alternatively, the storage capacitor Cst may be formed in accordance with overlap of the pixel electrode with a storage line under the condition that an insulating film is interposed between the pixel electrode and the storage line.
The liquid crystal panel 2 may be divided into a plurality of display regions in accordance with a plurality of data line driving regions where respective data integrated circuits 4a to 4c are driven. The data integrated circuits 4a to 4c are mounted on the image non-display area of the liquid crystal panel 2 such that they correspond to respective data line driving regions. Similarly, the gate driver 3 is formed or mounted on the image non-display area in accordance with an arrangement direction of the gate lines, to drive the plural gate lines GL1 to GLn.
Each of the plural data integrated circuits 4a to 4c is constituted by integrating a conventional timing controller and a conventional data driving circuit in the form of a single chip. Upon externally receiving a plurality of synchronizing signals, the one-chip data integrated circuits 4a to 4c align image data externally supplied thereto such that the image data is suitable for driving the liquid crystal panel 2, using the received synchronizing signals, to latch the image data by the unit of at least one horizontal line. Using other externally-input synchronizing signals, for example, a dot clock, a data enable signal, and horizontal and vertical synchronizing signals, each of the data integrated circuits 40a to 4c generates gate and data control signals. On the other hand, when the data integrated circuits 4a to 4c are driven under the condition that there is no externally-input synchronizing signal, they internally generate synchronizing signals, align image data externally input thereto such that the image data is suitable for driving the liquid crystal panel 2, and latch the aligned image data by the unit of at least one horizontal line. Also, each of the data integrated circuits 4a to 4c internally generates gate and data control signals, using other synchronizing signals internally generated therein. The data integrated circuits 4a to 4c share one of the synchronizing signals internally generated therein, to control generation timing of the gate and data control signals in accordance with the shared synchronizing signal.
The gate driver 3 may be formed on the image non-display area of the liquid crystal panel 2, to be integrated with the liquid crystal panel 2. Alternatively, the gate driver 3 may be mounted on the image non-display area of the liquid crystal panel 2, in the form of an integrated circuit. The gate driver 3 sequentially drives the plural gate lines GL1 to GLn. In detail, the gate driver 3 sequentially supplies a scan pulse to the gate lines GL1 to GLn in accordance with gate control signals from at least one of the data integrated circuits, for example, a gate start pulse, a gate shift clock and a gate output enable signal from the data integrated circuit 4a. The gate driver 3 supplies a gate low voltage to the gate lines GL1 to GLn during a period, for which no scan pulse is supplied.
The plural driving integrated circuits shown in
The data integrated circuit of
The signal repeater 11 sequentially supplies the externally-input image data Data to the image processor 12. When external synchronizing signals E_SC are input, the signal repeater 11 supplies the input external synchronizing signals E_SC to the synchronizing signal generator 13.
The image processor 12 aligns the image data Data supplied from the signal repeater 11 by the unit of at least one horizontal line such that the image data Data is suitable for driving the liquid crystal panel 2. That is, the image processor 12 detects image data Data sequentially input thereto in accordance with a data line driving position of the data integrated circuit, in which the image processor 12 is included, and then aligns the detected image data Data by the unit of at least one horizontal line in accordance with the corresponding image display region. In other words, since each of the data integrated circuits 4a to 4c only drives the data lines in a corresponding one of the image display regions of the liquid crystal panel 2, the image processor 12 of each data integrated circuit detects and aligns only a part of the image data corresponding to the overall horizontal lines in accordance with the data line driving position of the data integrated circuit, in which the image processor 12 is included. The image processor 12 then sequentially supplies the aligned image data RGB to the data driver 17.
The clock generator 14 includes at least one clock oscillator, to continuously generate a main clock MCLK in accordance with a predetermined frequency and to supply the main clock MCLK to the synchronizing signal generator 13 in real time.
Upon receiving the external synchronizing signals E_SC from the signal repeater 11, the synchronizing signal generator 13 supplies the external synchronizing signals E_SC to the control signal generator 15. When there is no externally-input synchronizing signal E_SC, the synchronizing signal generator 13 internally generates the horizontal synchronizing signal Hsync, to share the horizontal synchronizing signal Hsync with the remaining driving integrated circuits. The synchronizing signal generator 13 generates a vertical synchronizing signal, using a highest-frequency one of the internally-generated horizontal synchronizing signal Hsync and externally-input horizontal synchronizing signals E_Hsync.
Upon receiving the external synchronizing signals E_SC from the synchronizing signal generator 13, the control signal generator 15 generates gate and data control signals GCS and DCS, using the received external synchronizing signals E_SC. However, when the synchronizing signal generator 13 supplies the vertical synchronizing signal generated therefrom, together with the highest-frequency horizontal synchronizing signal, the control signal generator 15 generates gate and data signals GCS and DCS, using the supplied horizontal synchronizing signal and vertical synchronizing signal. The generated gate control signal GCS is supplied to the gate driver 3 via the boosting circuit 16. The data control signal DCS is supplied to the data driver 17. The gate control signal GCS includes a gate start pulse, a gate shift clock and a gate output enable signal to control the gate driver 3. The data control signal DSC includes a data start pulse, a data shift clock, a data output enable signal and a data polarity signal to control the data driver 17.
The boosting circuit 16 boosts the voltage level of at least one of the above-described gate control signals GCS, and supplies the boosted gate control signal CGSC to the gate driver 3.
The data driver 17 converts the aligned image data RGB supplied from the image processor 12 into analog voltages, namely, image signal AData, using the above-described data control signals GCS, namely, the source start pulse, source shift clock, source output enable signal, etc. In detail, the data driver 17 latches the aligned image data RGB in accordance with the source shift clock, and then supplies, to the data lines DL1 to DLm, the image signal AData for one horizontal line in every horizontal period, in which a scan pulse is supplied to one of the gate lines GL1 to GLn, in response to the source output enable signal.
Each of the data integrated circuits 4a to 4c may further include a gradation voltage generator for generating gradation voltages in accordance with a plurality of gamma voltage levels. The gradation voltage generator divides first and second reference voltages having positive and negative polarities, to generate a plurality of gradation voltages. In this case, the gradation voltage generator supplies the generated gradation voltages to the data driver 17. When the image data Data consists of N bits, the gradation voltage generator generates 2N positive (+) and negative (−) gradation voltages.
The synchronizing signal generator 13 of
The first counter 21 counts one or more external horizontal synchronizing signals E_Hsync input from the remaining data integrated circuits, and generates a first count signal CS1 corresponding to a highest-frequency one of the counted horizontal synchronizing signals E_Hsync. The highest-frequency external horizontal synchronizing signal E_Hsync may be selected by counting clock pulses of the external horizontal synchronizing signals E_Hsync, and selecting the external horizontal synchronizing signal E_Hsync, the counted value of which most early reaches a predetermined count value, from among the external horizontal synchronizing signals E_Hsync. Even when the clock generators 14 of respective data integrated circuits 4a to 4c are set to have the same frequency, they have different frequency tolerances. For this reason, the horizontal synchronizing signals internally generated from respective data integrated circuits 4a to 4c have different frequency tolerances. To this end, the first counter 21 counts the external horizontal synchronizing signals E_Hsync, and generates the first count signal CS1, which corresponds to a highest-frequency one of the counted horizontal synchronizing signals E_Hsync. The first counter 21 supplies the first count signal CS1 to the horizontal synchronizing signal generator 23. Thus, the external horizontal synchronizing signal E_Hsync generated at a highest frequency can be supplied, as the first count signal CS1, to the horizontal synchronizing signal generator 23 because the first count signal CS1 is identical to the highest-frequency external horizontal synchronizing signal E_Hsync.
The second counter 22 counts the main clock MCLK or the horizontal synchronizing signal Hsync internally generated from the synchronizing signal generator 13, thereby generating a second clock signal CS2. The horizontal synchronizing signal Hsync internally generated from the horizontal synchronizing signal generator 13 may have the same clock waveform as the main clock MCLK. Accordingly, the second counter 22 achieves counting of the internally-generated horizontal synchronizing signal Hsync by counting the main clock MCLK.
The horizontal synchronizing signal generator 23 supplies the horizontal synchronizing signal Hsync corresponding to the second count signal CS2 to the first counters 21 of the remaining data integrated circuits. Also, the horizontal synchronizing signal generator 23 compares the first count signal CS1 and second count signal CS2, thereby internally generating a horizontal synchronizing signal Hsync corresponding to a higher-frequency one of the first and second count signals CS1 and CS2. The horizontal synchronizing signal generator 23 then compares the internally-generated horizontal synchronizing signal Hsync with external horizontal synchronizing signals respectively input from the remaining driving integrated circuits, thereby selecting a highest-frequency one of the horizontal synchronizing signals. Accordingly, the data drivers 17 of the driving integrated circuits 4a to 4c can be driven in sync with the selected horizontal synchronizing signal. Since the data drivers 17 of the driving integrated circuits 4a to 4c are driven in sync with the highest-frequency horizontal synchronizing signal, all driving integrated circuits 4a to 4c can be synchronously driven.
The reset signal generator 24 supplies a reset signal RS to the second counter 22 in response to outputting of the horizontal synchronizing signal Hsync from the horizontal synchronizing signal generator 23, to reset the second counter 22. Thus, it is possible not only to employ an internally-generated horizontal synchronizing signal when the internally-generated horizontal synchronizing signal has a highest frequency, but also to employ an externally-input horizontal synchronizing signal when the externally-input horizontal synchronizing signal has a higher frequency than the internally-generated horizontal synchronizing signal.
Referring to
It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. Thus, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2011-0120526 | Nov 2011 | KR | national |
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| Office Action issued in Chinese Patent Application No. 201210466944.9, mailed Jul. 3, 2014, 11 pages. |
| Number | Date | Country | |
|---|---|---|---|
| 20130141404 A1 | Jun 2013 | US |
