This application claims the benefit of Korean Patent Application No. P98-38119, filed on Sep. 15, 1998, which is hereby incorporated by reference.
1. Field of the Art
This invention relates to a liquid crystal display device displaying an image employing a light transmissivity of liquid crystal, and more particularly to a residual image eliminating apparatus and method that is adaptive for eliminating a residual image emerging on a screen due to a residual electric charge accumulated in a picture element (or pixel) cell after a power source was turned off.
2. Description of the Related Art
Recently, there has been an accelerated development of a flat panel display device of an active matrix driving system, for example, a liquid crystal display device using thin film transistors (TFTs) as switching devices. Since such a liquid crystal display apparatus can have a smaller dimension in comparison to the existing cathode ray tube (or brown tube), it has been commercially available for a display device of a portable television, a lap-top personal computer, and so on.
Referring to
When a power source of the liquid crystal display panel is turned on, a gate low voltage Vg1 having a voltage level less than the gate threshold voltage Vth is supplied to gate lines 11, excluding the gate line coupled with the image signal Vd. This gate low voltage Vg1 is set to have a value lower than the minimum value of the image signal Vd. On the other hand, when a power source of the liquid crystal display panel is turned off, the gate low voltage Vg1, the image signal Vd and the common voltage Vcom are converged into a specific level (i.e., a voltage level corresponding to a ground voltage supplied during operation of the liquid crystal display panel, hereinafter referred to as “ground level” GND). At this time, the gate low voltage Vg1 changes as shown in
As shown in
When a power source of the liquid crystal panel is turned off, the ground voltage GND is developed on each of the negative voltage line NVL and the positive voltage line PVL. At the same time, the capacitor C1 applies a negative polarity voltage—VDD to the base of the transistor Q1 by the charged electric charges thereof. Then, the transistor Q1 is turned on by converging the positive voltage VDD into the ground level GND, thereby connecting its emitter to the collector. The gate low voltage Vg1 is converged into the ground level GND by turning on the transistor Q1. The zener diode ZD is turned off by converging the negative voltage VEE [and the gate low voltage Vg1] into the ground level GND.
On the other hand, upon line inversion driving, the common voltage Vcom having an alternating current shape as shown in
Otherwise, since a channel of the TFT connected to the B side pixel charged with a positive(+) voltage with respect to the ground level GND is turned off, the pixel voltage Vp is converged into the ground level GND slowly. In other words, in the case of the liquid crystal cell 12 charged with a positive (+) voltage based on the ground level GND before the power source is turned off, a voltage applied to the gate of the TFT 10 becomes lower than the pixel charge voltage Vp. Accordingly, even though a power of the liquid crystal display panel is turned off, a residual image emerges on a screen (i.e., a liquid crystal display panel). Further, in the case of being driven in the line inversion system, a residual image appears at odd-numbered gate lines 11 or even-numbered gate lines 11. It takes a considerable time (i.e., more than about one minute) to extinguish such a residual image.
Accordingly, it is an object of the present invention to provide a residual image eliminating apparatus and method that is adaptive for eliminating a residual image emerging due to a residual electric charge existing in a pixel cell after the shut off of a power supply.
In order to achieve this and other objects of the invention, a residual image eliminating apparatus for a liquid crystal display device according to an aspect of the present invention includes a liquid crystal panel having a plurality of gate lines and a plurality of data lines crossing perpendicularly with respect to each other, and thin film transistors connected to the gate lines and the data lines to switch image signals to be applied to liquid crystal cells, and level shifting means for receiving a power supply voltage and a ground voltage to apply a first voltage level for turning off the thin film transistors to the gate lines upon power-on and to apply a higher voltage level than the ground voltage to the gate lines upon power-off.
A residual image eliminating method for a liquid crystal display device according to another aspect of the present invention includes the steps of receiving a power supply voltage and a ground voltage to apply a first voltage level for turning off the thin film transistors to the gate lines upon power-on, and applying a higher level voltage than the ground voltage to the gate lines upon power-off.
These and other objects of the invention will be apparent from the following detailed description of the embodiments of the present invention with reference to the accompanying drawings, in which:
Referring to
The liquid crystal display device includes a gate driver 20 connected to the gate lines 11, a data driver connected to the data lines 13, a power supply 2 for supplying a ground voltage level GND and a supply voltage VDD, a gate low voltage generator 4 and a gate high voltage generator 6 connected between the power supply 2 and the gate driver 20 to supply a different level of gate voltages Vg1 and Vgh to the gate driver 20, respectively. A common voltage generator 8 is connected between the power supply 2 and the common voltage electrode 15 to supply a common voltage Vcom to the common voltage electrode 15. The gate driver 20 sequentially applies a scanning pulse to the m gate lines 11, thereby sequentially driving pixels on the liquid crystal display panel 40 line by line.
The data driver 30 is synchronized with the scanning pulse to apply an image signal Vd corresponding to a logical value of red (R), green (G), and blue (B) video data to each of the n data lines 13. The gate low voltage generator 4 level-shifts the gate low voltage Vg1 to higher than the ground level GND upon shut-off of the supply voltage to form a channel in the TFT MN, thereby discharging electric charges charged in the liquid crystal cell 12 and the support capacitor 14 through the drain and the source of the TFT MN to the source lines 13. Herein, the gate low voltage Vg1 is a difference voltage between a voltage at a ground voltage input line GNDL of the gate low voltage generator 4 and a voltage at an output line VGLL of the gate low voltage generator 4 (or an optional point c at the gate line 11 which is an output line of the gate driver 20). This gate low voltage Vg1 is detected by contacting probes of a voltage meter (not shown) at each of the above two points (i.e., a and b, or a and c).
The gate high voltage generator 6 makes use of a supply voltage VDD applied from the power supply 2 through a supply voltage line VDDL to generate a gate high voltage Vgh having a voltage level higher than the maximum value of the data plus the threshold voltage of the TFT MN and supplies the gate high voltage Vgh to the gate driver 20 through a gate high voltage line VGHL. The common voltage generator 8 allows a contrary polarity of common voltage Vcom to be supplied to the liquid crystal cells 12 and the support capacitors 14 connected to even-numbered and odd-numbered gate lines 11.
The negative voltage generator 52 is connected between the power supply 2 and the gate low voltage selector 54 to invert the polarity of the supply voltage VDD having a positive polarity level inputted to itself through a supply voltage line VDDL, thus generating a negative polarity voltage VEE (e.g., −5V) on a negative voltage line NVL. Also, the negative voltage generator 52 may generate a negative polarity voltage VEE having an alternating current signal shape by inverting the polarity of the supply voltage VDD and controlling a level of the inverted supply voltage. Then, the negative polarity voltage VEE produced in this manner is supplied to the gate low voltage selector 54 through the negative voltage line NVL.
The electric charge accumulator 56 is connected to the gate high voltage generator 6 and/or the power supply 2 and, at the same time, to the gate low voltage selector 54, thereby charging an electric charge from the gate high voltage generator 6 applied thereto through a gate high voltage line VGHL when the supply voltage VDD has a positive polarity voltage. That is, when a power of the liquid crystal display panel is turned off (when a power source of the liquid crystal display panel is turned off to the gate low voltage selector 54), the electric charge accumulator 56 discharges electric charge to the gate driver 20 when the supply voltage VDD drops to the ground level GND. The gate low voltage selector 54 connected between the negative voltage generator 52 and the electric charge accumulator 56 raises the gate low voltage Vg1 as seen from
As shown in
Also, the gate low voltage selector 54 has a capacitor C2 connected between the supply voltage line VDDL and the base of the transistor Q2, and a third resistor R3 connected between the base and collector of the transistor Q2. The transistor Q2 is a PNP-type transistor which receives a supply voltage VDD having a positive level (e.g., 5V or 3.3V) from the supply voltage line VDDL at its base thereof through the capacitor C2 when a power source of the liquid crystal display panel is turned on. At this time, since almost an infinite value of resistance exists between the emitter and the collector of the transistor Q2, the voltage signal on the connection node N between the zener diode ZD and the transistor Q2 is not bypassed into the ground voltage GND, but it is supplied to the gate low voltage line VGLL. Meanwhile, the capacitor C2 charges the supply voltage VDD from the supply voltage line VDDL. At this time, a negative polarity voltage VEE dropped by means of the zener diode ZD1 is output, via the node N and the first resistor R1, to the gate low voltage line VGLL. Further, the capacitor C1 is charged with the gate high voltage Vgh on the gate high voltage line VGHL, and the second resistor R2 suppresses an electric charge charged in the capacitor C1.
Otherwise, when a power source of the liquid crystal display panel is turned off, the supply voltage VDD on the supply voltage line VDDL and the negative polarity voltage VEE on the negative voltage line NVL are converged to the ground level GND, and an electric charge charged in the capacitor C1 is discharged, via the second resistor R2, the gate low voltage line VGHL and the first resistor R1, into the node N. At the same time, the capacitor C1 applies a negative polarity voltage—VDD to the base of the transistor Q2 by the charged electric charges thereof. Then, the transistor Q2 is turned on to connect the node N to the ground voltage line GNDL, thereby increasing a voltage at the node N into the ground level GND rapidly. Accordingly, a voltage on the gate low voltage line VGLL also is raised into a level higher than the ground level as seen from
Then, an electric charge amount discharged from the capacitor C1 is gradually reduced, and a voltage on the gate low voltage line VGLL maintains the ground level GND upon complete discharging. As a result, a gate low voltage Vg1 as shown in
During the time interval A, a gate low voltage Vg1 higher than the ground level GND is applied to the gate of the TFT MN, thereby opening a channel of the TFT MN. Accordingly, electric charges stored in the liquid crystal cell 12 and the support capacitor 14 are discharged into the source lines 13 over the opened channel of the TFT MN. The time interval A, at which the gate low voltage Vg1 maintains a voltage level higher than the ground level GND, is determined by a time constant value depending on the second resistor R2 and the capacitor C1 and a parasitic resistor (not shown) in the path of the gate high voltage Vgh (i.e., in the gate high voltage line VGHL). The gate high voltage Vgh is available if higher than the ground level GND, but it has preferably the highest level voltage in the supply voltages used in the liquid crystal display panel. In other words, the capacitor C1 has been charged by means of the gate high voltage Vgh in the present embodiment, but it may be charged by means of any supply voltage higher than the ground level GND.
Moreover, the gate low voltage selector 54 may include a serial connection of a coupling capacitor Cc and a alternating current voltage source AC arranged between the node N and the ground voltage line GNDL. The alternating current voltage source supplies an alternating current voltage to the node N when a power source is turned on, thereby changing the gate low voltage Vg1 on the gate low voltage line VGLL in a constant period. The coupling capacitor Cc cuts off a direct current voltage component that can be applied from the alternating current voltage source AC to the node N. Such coupling capacitor Cc and alternating current voltage source AC are used when the liquid crystal display panel is driven in the line inversion system.
The capacitor C1 is charged with the gate high voltage Vgh from the gate high voltage line VGHL, and the second resistor R2 suppresses an electric charge charged in the capacitor C1. Otherwise, when a power source of the liquid crystal display panel is turned off, the negative polarity voltage VEE applied from the negative voltage line NVL to the zener diode ZD1 are converged to the ground level GND, and an electric charge charged in the capacitor C1 is discharged, via the second resistor R2, the gate low voltage line VGLL and the first resistor R1, into the node N. Accordingly, a voltage at the node N increases into the ground level GND rapidly. At this time, a voltage on the gate low voltage line VGLL also is raised into a level higher than the ground level as seen from
Then, an electric charge amount discharged from the capacitor C1 is gradually reduced, and a voltage on the gate low voltage line VGLL maintains the ground level GND upon complete discharging. As a result, a gate low voltage Vg1 as shown in
During the time interval A, a gate low voltage Vg1 higher than the ground level GND is applied to the gate of the TFT MN, thereby opening a channel of the TFT MN. Accordingly, electric charges stored in the liquid crystal cell 12 and the support capacitor 14 are discharged into the source lines 13 over the opened channel of the TFT MN. The time interval A, at which the gate low voltage Vg1 maintains a voltage level higher than the ground level GND, is determined by a time constant value depending on the second resistor R2 and the capacitor C1 and a parasitic resistor (not shown) in the path of the gate high voltage Vgh, (i.e., in the gate high voltage line VGHL). The gate high voltage Vgh is available if higher than the ground level GND, but it has preferably the highest level voltage in the supply voltages used in the liquid crystal display panel. In other words, the capacitor C1 has been charged by means of the gate high voltage Vgh in the present embodiment, but it may be charged by means of any supply voltage higher than the ground level GND.
Moreover, the gate low voltage selector 54 may include a serial connection of a coupling capacitor Cc and an alternating current voltage source AC arranged between the node N and the ground voltage line GNDL. The alternating current voltage source supplies an alternating current voltage to the node N when a power source is turned on, thereby changing the gate low voltage Vg1 on the ground voltage line GNDL in a constant period. The coupling capacitor Cc cuts off a direct current voltage component that can be applied from the alternating current voltage source AC to the node N. Such coupling capacitor Cc and alternating current voltage source AC are used when the liquid crystal display panel is driven in the line inversion system.
As described above, the gate low voltage selector 54 of
When a power source of the liquid crystal display panel is turned on, the transistor Q3 is turned on with the aid of a negative polarity voltage VEE supplied from the negative voltage generator 52 in
When a power source of the liquid crystal display panel is turned off, the gate high voltage Vgh on the gate high voltage line VGHL and the negative polarity voltage VEE on the negative voltage line NVL are converged to the ground level GND and thus a voltage difference between the emitter and the collector of the transistor Q3 is converged substantially to ‘0 V’. Accordingly, the current path between the emitter and the collector of the transistor Q3 is opened, and electric charges accumulated in the capacitor C3 are discharged, via the gate high voltage line VGHL and the pull-up resistor R4, into the gate low voltage line VGLL. As a result, the gate low voltage Vg1 on the gate low voltage line VGLL changes as seen from
During the time interval A, a gate low voltage Vg1 higher than the ground level GND is applied to the gate of the TFT MN to open a channel of the TFT MN. Accordingly, electric charges stored in the liquid crystal cell 12 and the support capacitor 14 are discharged into the source lines 13 over the opened channel of the TFT MN. The time interval A, at which the gate low voltage Vg1 maintains a higher voltage level than the ground level GND, is determined by values of the pull-up resistor R4 and the capacitor C3 and a parasitic resistor (not shown) in the path of the gate high voltage Vgh (i.e., in the gate high voltage line VGHL). The pull-up resistor R4 must have a sufficient resistance value enough to prevent the gate high voltage Vgh from being leaked into the gate low voltage line VGLL when the gate high voltage Vgh is charged into the capacitor C3. For example, assuming the time constant is 4 sec, the pull-up resistor R4 and the capacitor C3 preferably have a resistance value of 20 K and a capacitance value of about 60 to 200 micro F, respectively.
According to the present invention, when a power source of the liquid crystal display panel is turned off, a voltage at the gate line 11 maintains a voltage level higher than the ground level GND (i.e., a voltage level capable of producing a channel at the TFT) during a predetermined time interval, thereby providing a channel in the TFT. Accordingly, electric charges charged in the pixels in the positive or negative polarity based on the ground level GND are rapidly discharged, via the drains and the sources of the TFTs, into the source lines 13. As a result, according to the present invention, a residual image disappears within a shorter time. For example, as proven from the experiment, it takes more than one minute until any residual images disappear completely in the case of the conventional liquid crystal display device, whereas it takes less than 10 seconds until any residual images disappear completely in the case of the liquid crystal display device according to the present invention.
In the present invention, other forms of gate low voltage generator 4 for outputting higher gate low voltage during power off may be used. For example, a circuit for generating a pulse upon power off may be used.
As described above, in the residual image eliminating apparatus and method for the liquid crystal display device according to the present invention, a voltage at the gate line maintains a voltage level capable of opening a channel of the TFT during a certain time interval when a power source of the liquid crystal display panel is turned off, thereby discharging electric charges charged in the liquid crystal cells into the source lines. Accordingly, any residual images disappear rapidly when a power source of the liquid crystal display panel is turned off. As a result, the residual image eliminating apparatus and method for the liquid crystal display device according to the present invention is capable of effectively eliminating any residual images.
Although the present invention has been explained by the embodiments shown in the drawing hereinbefore, it should be understood to the ordinary skilled person in the art that the invention is not limited to the embodiments, but rather than that various changes or modifications thereof are possible without departing from the spirit of the invention. Accordingly, the scope of the invention shall be determined only by the appended claims and their equivalents.
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1998-38119 | Sep 1998 | KR | national |
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