This application claims priority under 35 U.S.C. § 119(a) to a Korean Patent Application filed in the Korean Intellectual Property Office on Feb. 18, 2008 and assigned Serial No. 10-2008-0014649, a Korean Patent Application filed in the Korean Intellectual Property Office on Feb. 29, 2008 and assigned Serial No. 10-2008-0019373, a Korean Patent Application filed in the Korean Intellectual Property Office on Nov. 25, 2008 and assigned Serial No. 10-2008-0117264, and a Korean Patent Application filed in the Korean Intellectual Property Office on Jan. 30, 2009 and assigned Serial No. 10-2009-0007662, the disclosures of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates generally to a communication system using Low-Density Parity-Check (LDPC) codes, and more particularly, to a channel encoding/decoding apparatus and method for generating LDPC codes of a particular type.
2. Description of the Related Art
In wireless communication systems, link performance significantly decreases due to various noises in channels, a fading phenomenon, and Inter-Symbol Interference (ISI). Therefore, in order to realize high-speed digital communication systems requiring high data throughput and reliability, such as next-generation mobile communication, digital broadcasting, and portable internet, it is necessary to develop a technology for overcoming noises, fading, and ISI. Recently, an intensive study was conducted relating to the use of an error-correcting code in increasing communication reliability by efficiently recovering distorted information.
An LDPC code, which was first introduced by Gallager in the 1960s, has been underutilized due to its complex implementation that could not be resolved by past technology. However, turbo code, which was discovered by Berrou, Glavieux, and Thitimajshima in 1993, shows the performance approximating Shannon's channel limit. Thus, research has been conducted on iterative decoding and graph-based channel encoding along with analyses on performance and characteristic of the turbo code. Due to this research, the LDPC code was restudied in the late 1990s, which proved that LDPC code has performance approximating Shannon's channel limit if it undergoes decoding by applying iterative decoding based on a sum-product algorithm on a Tanner graph (a special case of a factor graph) corresponding to the LDPC code.
The LDPC code is typically represented using a graph representation technique, and many characteristics can be analyzed through the methods based on graph theory, algebra, and probability theory. Generally, a graph model of channel codes is useful for description of codes. By mapping information on encoded bits to vertexes in the graph and mapping relations between the bits to edges in the graph, it is possible to consider a communication network in which the vertexes exchange predetermined messages through the edges. This makes it possible to derive a natural decoding algorithm. For example, a decoding algorithm derived from a trellis, which can be regarded as a kind of graph, can include the well-known Viterbi algorithm and a Bahl, Cocke, Jelinek and Raviv (BCJR) algorithm.
The LDPC code is generally defined as a parity-check matrix, and can be expressed using a bipartite graph, which is referred to as a Tanner graph. In the bipartite graph vertexes constituting the graph are divided into two different types, and the LDPC code is represented by the bipartite graph composed of vertexes, some of which are called variable nodes and the other of which are called check nodes. The variable nodes are mapped one-to-one to the encoded bits.
With reference to
Referring to
In the Tanner graph of the LDPC code, a degree of the variable node and the check node is defined as the number of edges connected to each respective node, and the degree is equal to the number of non-zero entries in a column or row corresponding to the associated node in the parity-check matrix of the LDPC code. For example, in
In order to express degree distribution for the nodes of the LDPC code, a ratio of the number of degree-i variable nodes to the total number of variable nodes is defined as fi, and a ratio of the number of degree-j check nodes to the total number of check nodes is defined as gi. For instance, for the LDPC code corresponding to
In Equation (1), as N increases, the density of ‘1’s in the parity-check matrix decreases. Generally, as for the LDPC code, since the code length N is inversely proportional to the density of non-zero entries, the LDPC code with a large N has a very low density of non-zero entries. The wording ‘low-density’ in the name of the LDPC code originates from the above-mentioned relationship.
Next, with reference to
In
Referring to
In the parity-check matrix, a structure of an information part, i.e., 0th column through (K1−1)th column, is made using the following rules.
Rule 1: A total of K1/M1 column groups are generated by grouping K1 columns corresponding to the information word in the parity-check matrix into multiple groups each composed of M1 columns. A method for forming columns belonging to each column group follows Rule 2 below.
Rule 2: Positions of ‘1’s in each 0th column in ith column groups (where i=1, . . . , K1/M1) are first determined. When a degree of a 0th column in each ith column group is denoted by Di, if positions of rows with 1 are assumed to be Ri,0(1), Ri,0(2), . . . , Ri,0(D
R
i,j
(k)
=R
i,(j-1)
(k)+q mod(N1−K1), k=1, 2, . . . , Di, i=1, . . . , K1/M1, j=1, . . . , M1−1 (2)
According to the above rules, it is can be appreciated that degrees of columns belonging to an ith column group (where i=1, . . . , K1/M1) are all equal to Di. For a better understanding of a structure of a DVB-S2 LDPC code that stores information on the parity-check matrix according to the above rules, the following detailed example will be described.
As a detailed example, for N1=30, K1=15, M1=5 and q=3, three sequences for the information on the positions of rows with 1 for 0th columns in 3 column groups can be expressed as follows. Herein, these sequences are called “weight-1 position sequences” for convenience.
R1,0(1)=0, R1,0(2)=1, R1,0(3)=2,
R2,0(1)=0, R2,0(2)=11, R2,0(3)=13,
R3,0(1)=0, R3,0(2)=10, R3,0(3)=14.
Regarding the weight-1 position sequence for 0th columns in each column group, only the corresponding position sequences can be expressed as follows for each column group. For example:
0 1 2
0 11 13
0 10 14.
In other words, the ith weight-1 position sequence in the ith line sequentially represents the information on the positions of rows with 1 in the ith column group.
It is possible to generate an LDPC code having the same concept as that of a DVB-S2 LDPC code of
It is known that the DVB-S2 LDPC code designed in accordance with Rule 1 and Rule 2 can be efficiently encoded using the structural shape. Respective steps in a process of performing LDPC encoding using the DVB-S2 based parity-check matrix will be described below by way of example.
In the following description, as a detailed example, a DVB-S2 LDPC code with N1=16200, K1=10800, M1=360 and q=15 undergoes an encoding process. For convenience, information bits having a length K1 are represented as (i0, i1, . . . , iK
Step 1: An LDPC encoder initializes parity bits as follows:
p0=p1= . . . =pN
Step 2: The LDPC encoder reads information on a row where 1 is located in a column group from a 0th weight-1 position sequence out of the stored sequences indicating the parity-check matrix.
0 2084 1613 1548 1286 1460 3196 4297 2481 3369 3451 4620 2622
R1,0(1)=0, R1,0(2)=2048, R1,0(3)=1613, R1,0(4)=1548, R1,0(5)=1286,
R1,0(6)=1460, R1,0(7)=3196, R1,0(8)=4297, R1,0(9)=2481, R1,0(10)=3369,
R1,0(11)=3451, R1,0(12)=4620, R1,0(13)=2622. (3)
The LDPC encoder updates particular parity bits px in accordance with Equation (3) using the read information and the first information bit i0. Herein, x denotes a value of R1,0(k) for k=1, 2, . . . , 13.
p0=p0i0, p2084=p2064
i0, p1613=p1613
i0,
p1548=p1548i0, p1286=p1286
i0, p1460=p1460
i0,
p3196=p3196i0, p4297=p4297
i0, p2481=p2481
i0,
p3369=p3369i0, p3451=p3451
i0, p4620=p4620
i0,
p2622=p2622i0
In Equation (3), px=pxi0 can also be expressed as px←px
i0, and
denotes binary addition.
Step 3: The LDPC encoder first finds out a value of Equation (4) for the next 359 information bits im (where m=1, 2, . . . , 359) after i0.
{x+(m mod M1)×q}mod(N1−K1), M1=360, m=1, 2, . . . , 359 (4)
In Equation (4), x denotes a value of R1,0(k) for k=1, 2, . . . , 13. It should be noted that Equation (4) has the same concept as Equation (2).
Next, the LDPC encoder performs an operation similar to Equation (3) using the value found in Equation (4). That is, the LDPC encoder updates p{x+(m mod M
p15=p15i1, p2009=p2009
i1, p1628=p1628
i1,
p1563=p1563i1, p1301=p1301
i1, p1475=p1475
i1,
p3211=p3211i1, p4312=p4312
i1, p2496=p2496
i1,
p3384=p3384i1, p3466=p3466
i1, p4635=p4635
i1,
p2637=p2637i0 (5)
It should be noted that q=15 in Equation (5). The LDPC encoder performs the above process for m=1, 2, . . . , 359, in the same manner as shown above.
Step 4: As in Step 2, the LDPC encoder reads information of the 1st weight-1 position sequence (k=1, 2, . . . , 13) for a 361st information bit i360, and updates a particular px, where x denotes R2,0(k). The LDPC encoder updates p{x+(m mod M
Step 5: The LDPC encoder repeats Steps 2, 3 and 4 for all groups each having 360 information bits.
Step 6: The LDPC encoder finally determines parity bits using Equation (6).
pi=pipi-1, i=1, 2, . . . , N1−K1−1 (6)
The parity bits pi of Equation (6) are parity bits that undervent LDPC encoding.
As described above, in DVB-S2, the LDPC encoder performs LDPC encoding through the process of Step 1 through Step 6.
It is well known that performance of the LDPC code is closely related to cycle characteristics of the Tanner graph. In particular, it is well known by experiments that performance degradation may occur when the number of short-length cycles is great in the Tanner graph. Thus, the cycle characteristics on the Tanner graph should be considered in order to design LDPC codes having high performance.
However, no method has been proposed that designs DVB-S2 LDPC codes having good cycle characteristics. For the DVB-S2 LDPC code, an error floor phenomenon is observed at a high Signal to Noise Ratio (SNR) as optimization on cycle characteristics of the Tanner graph is not considered. For these reasons, there is a need for a method capable of efficiently improving cycle characteristics in designing LDPC codes having the DVB-S2 structure.
The present invention has been made to address at least the above problems and/or disadvantages and to provide at least the advantages described below. Accordingly, an aspect of the present invention provides a channel encoding/decoding apparatus and method for designing a parity-check matrix of a quasi-cyclic LDPC code designed based on a circulant permutation matrix to design a DVB-S2 LDPC code in a communication system using LDPC codes.
Another aspect of the present invention provides a channel encoding/decoding apparatus and method for designing a parity-check matrix of the same LDPC code as the DVB-S2 LDPC code having a good Tanner graph characteristic in a communication system using LDPC codes.
According to one aspect of the present invention, a method is provided for generating a parity-check matrix of a Low-Density Parity-Check (LDPC) code. Parameters for designing the LDPC code are determined. A first parity-check matrix of a quasi-cyclic LDPC code is formed according to the determined parameters. A second parity-check matrix is created through the elimination of a predetermined portion of a parity part in the first parity-check matrix. A third parity-check matrix is created by rearranging the second parity-check matrix.
According to another aspect of the present invention, a method is provided for encoding a channel in a communication system using a Low-Density Parity-Check (LDPC) code. A stored parity-check matrix is read. A received signal is LDPC-encoded using the stored parity-check matrix. The parity-check matrix is divided into an information word and a parity. When a code rate is ⅗ and a length of a codeword is 16200, the parity-check matrix is formed as defined in the following table;
According to a further embodiment of the present invention, a method is provided for decoding a channel in a communication system using a Low-Density Parity-Check (LDPC) code. A parity-check matrix of the LDPC code is extracted. LDPC decoding is performed using the extracted parity-check matrix. The extracted parity-check matrix is divided into a parity and an information word. When a code rate is ⅗ and a length of a codeword is 16200, the parity-check matrix is formed as defined in the following table;
According to an additional aspect of the present invention, an apparatus is provided for encoding a channel in a communication system using a Low-Density Parity-Check (LDPC) code. An LDPC code parity-check matrix extractor reads a stored parity-check matrix. An LDPC encoder LDPC-encodes a received signal using the stored parity-check matrix. The parity-check matrix is divided into a parity and an information word. When a code rate is ⅗ and a length of a codeword is 16200, the parity-check matrix is formed as defined in the following table;
According to another further aspect of the present invention, an apparatus is provided for decoding a channel in a communication system using a Low-Density Parity-Check (LDPC) code. An LDPC code parity-check matrix extractor reads a stored parity-check matrix. An LDPC decoder performs LDPC decoding using the read parity-check matrix. The read parity-check matrix is divided into a parity and an information word. When a code rate is ⅗ and a length of a codeword is 16200, the read parity-check matrix is formed as defined in the following table;
The above and other aspects, features and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings in which:
Preferred embodiments of the present invention are described in detail with reference to the annexed drawings. The same or similar components are designated by the same or similar reference numerals although they are illustrated in different drawings. Detailed descriptions of constructions or processes known in the art may be omitted to avoid obscuring the subject matter of the present invention.
The present invention provides a method for designing a DVB-S2 LDPC code having a good Tanner graph characteristic. In addition, the present invention provides a method for generating an LDPC codeword using a parity-check matrix of the above-designed LDPC code and an apparatus thereof.
Structural characteristics of a DVB-S2 LDPC code are described below using a parity-check matrix of a DVB-S2 LDPC code shown in
0 1 2
0 11 13
0 10 14
Here, an ith weight-1 position sequence in the ith line sequentially represents the information on the positions of rows with 1 in the ith column group.
The parity-check matrix of
Rule 3: 0th row through (N1−K1−1)th row are rearranged so that a (q·i+j)th row is located in an (M1·j+i)th row, where 0≦i≦M1 and 0≦j<q.
Rule 4: With 0th column through (K1−1)th column being kept intact, K1th column through (N1−1)th column are rearranged so that a (K1+q·i+j)th column is located in a (K1+M1·j+i)th column.
A parity-check matrix with a shape shown in
If it is assumed in
In summary, it can be understood that a parity-check matrix similar to the quasi-cyclic LDPC code can be obtained by reconstructing a parity-check matrix of the DVB-S2 LDPC code through Rule 3 and Rule 4. Also, it is expected that the DVB-S2 LDPC code can be generated from the quasi-cyclic LDPC code through the reverse process of Rule 3 and Rule 4.
While there is no known research result on the DVB-S2 LDPC code, there are many known design methods for the quasi-cyclic LDPC code. The design methods for the quasi-cyclic LDPC code include well-known methods for optimizing cycle characteristics on the Tanner graph.
An embodiment of the present invention proposes a method for designing a DVB-S2 LDPC code using the well-known method for improving cycle characteristics on the Tanner graph of the quasi-cyclic LDPC code. However, since the method for improving cycle characteristics of the quasi-cyclic LDPC code is only indirectly related to the present invention, a detailed description thereof will be omitted for simplicity.
A description of a method for designing a DVB-S2 LDPC code using a quasi-cyclic LDPC code is provided below. The DVB-S2 LDPC code has a codeword length NJ, an information length K1, and a parity length (N1−K1), and q=(N1−K1)/M1.
A parity-check matrix of a quasi-cyclic LDPC code is shown in
The respective partial blocks constituting the parity-check matrix of
In
The parity-check matrix of
The quasi-cyclic LDPC code shown in
As described above, there are many known methods for optimizing cycle characteristics on the Tanner graph of the quasi-cyclic LDPC code. Since the design method for the quasi-cyclic LDPC code with a Tanner graph having the optimized cycle characteristics is only indirectly related to the present invention, a detailed description thereof is omitted herein.
It is assumed that degree distribution is determined to show excellent performance in the state where the structure of the parity part is fixed in the quasi-cyclic parity-check matrix of
The form shown in
It should be noted that the circulant permutation matrix PM
The following Rule 5 and Rule 6 are defined to apply the reverse process of Rule 3 and Rule 4.
Rule 5: With 0th column through (K1−1)th column being kept intact, K1th column through (N1−1)th column are rearranged so that a (K1+M1·j+i)th column is located in a (K1+q·i+j)th column, where 0≦i<M1 and 0≦j<q.
Rule 6: 0th row through (N1−K1−1)th row are rearranged so that an (M1·j+i)th row is located in a (q·i+j)th row.
The parity-check matrix of the LDPC code generated from the quasi-cyclic LDPC code of
DVB-S2 LDPC Code Design Process
Referring to
Next, in step 803, a parity-check matrix of a quasi-cyclic LDPC code consisting of M1×M1 circulant permutation matrixes and zero matrixes as shown in
In step 805, circulant permutation matrixes of column blocks corresponding to an information part in
In step 807, a parity-check matrix shown in
In step 809, columns and rows in the parity-check matrix of
A codeword can be generated by applying the above-described DVB-S2 LDPC encoding process to the LDPC code designed through the above steps.
To analyze performance of the DVB-S2 LDPC code, a DVB-S2 LDPC code having the following parameters was designed. For example,
N1=648000, K1=38880, M1=360, q=72
To design rate-⅗ DVB-S2 LDPC codes having the above parameters, parity-check matrixes shown in Table 1 and Table 2, for example, can be obtained from a quasi-cyclic LDPC code having a total of N/M1=180 column blocks and q=(N1−K1)/M1=72 row blocks by applying the DVB-S2 LDPC code design process. An ith weight-1 position sequence in an ith column sequentially represents the information on the positions of rows with 1 in an ith column group.
In addition, a DVB-S2 LDPC code having the following parameters was designed. For example,
N1=16200, K1=9720, M1=360, q=18
To design rate-⅗ DVB-S2 LDPC codes having the above parameters, parity-check matrixes shown in Table 3 through and Table 6, for example, can be obtained from a quasi-cyclic LDPC code having a total of N1/M1=45 column blocks and q=(N1−K1)/M1=18 row blocks by applying the DVB-S2 LDPC code design process. It is noted that an ith weight-1 position sequence in an ith column sequentially represents the information on the positions of rows with 1 in an ith column group.
A performance comparison between the newly designed DVB-S2 LDPC code and the existing DVB-S2 LDPC code is shown in
It can be appreciated that when an Additive White Gaussian Noise (AWGN) channel uses a Binary Phases Shift Key (BPSK) modulation scheme, performance improvement of approximately 0.15 dB is made at BER=10−4. The performance improvement of a rate-⅗ DVB-S2 LDPC code can be achieved by simply changing information about the parity-check matrix as shown in Table 1 through Table 6.
The DVB-S2 LDPC code design process described with reference to
N1=64800, K1=43200, M1=360, q=60
To design rate-⅔ DVB-S2 LDPC codes having the above parameters, parity-check matrixes shown in Table 7 through and Table 10, for example, can be obtained from a quasi-cyclic LDPC code having a total of N1/M1=180 column blocks and q=60 row blocks by applying the DVB-S2 LDPC code design process of
Referring to
A detailed structure of a transmission apparatus in the communication system using the redesigned DVB-S2 LDPC code is shown in
The transmission apparatus includes a controller 1130, an LDPC code parity-check matrix extractor 1110 and an LDPC encoder 1150.
The LDPC code parity-check matrix extractor 1110 extracts an LDPC code parity-check matrix according to the requirements of the system. The LDPC code parity-check matrix can be extracted from the sequence information shown in Table 1 through Table 10, can be extracted using a memory in which the parity-check matrix is stored, can be given in the transmission apparatus, or can be generated in the transmission apparatus.
The controller 1130 is adapted to determine a necessary parity-check matrix according to a code rate, a codeword length, or an information length to meet the requirements of the system.
The LDPC encoder 1150 performs encoding based on the LDPC code parity-check matrix information read by the controller 1130 and the LDPC code parity-check matrix extractor 1110.
The reception apparatus includes a controller 1250, a parity-check matrix decider 1230, an LDPC code parity-check matrix extractor 1270, a demodulator 1210 and an LDPC decoder 1290.
The demodulator 1210 demodulates a received LDPC code, and provides the demodulated signal to the parity-check matrix decider 1230 and the LDPC decoder 1290.
The parity-check matrix decider 1230, under the control of the controller 1250, decides the parity-check matrix of the LDPC code used in the system based on the demodulated signal.
The controller 1250 provides the decision result from the parity-check matrix decider 1230 to the LDPC code parity-check matrix extractor 1270 and the LDPC decoder 1290.
The LDPC code parity-check matrix extractor 1270, under the control of the controller 1250, extracts the parity-check matrix of the LDPC code required by the system, and provides the extracted parity-check matrix to the LDPC decoder 1290. As stated above, the parity-check matrix of the LDPC code can be extracted from the sequence information shown in Table 1 through Table 10, can be extracted using a memory in which the parity-check matrix is stored, can be given in the transmission apparatus, or can be generated in the transmission apparatus.
The LDPC decoder 1290, under the control of the controller 1250, performs decoding based on the received signal provided from the demodulator 1210 and the information on the LDPC code's parity-check matrix provided from the LDPC code parity-check matrix extractor 1270.
An operation flowchart of the reception apparatus in
In step 1301, the demodulator 1210 receives a signal transmitted from the communication system using the redesigned DVB-S2 LDPC code and demodulates the received signal. Thereafter, in step 1303, the parity-check matrix decider 1230 makes a decision on a parity-check matrix of the LDPC code used in the system based on the demodulated signal.
The decision result from the parity-check matrix decider 1230 is provided to the LDPC code parity-check matrix extractor 1270 in step 1305. The LDPC code parity-check matrix extractor 1270 extracts a parity-check matrix of the LDPC code required by the system, and provides it to the LDPC decoder 1290 in step 1307.
As mentioned above, the parity-check matrix of the LDPC code can be extracted from the sequence information shown in Table 1 through Table 10, can be extracted using a memory in which the parity-check matrix is stored, can be given in the transmission apparatus, or can be generated in the transmission apparatus.
Thereafter, in step 1309, the LDPC decoder 1290 performs decoding based on the information about the LDPC code's parity-check matrix provided from the LDPC code parity-check matrix extractor 1270.
As is apparent from the foregoing description, the present invention optimizes characteristics of the Tanner graph in designing the DVB-S2 LDPC code, thereby optimizing performance of the communication system using the LDPC code.
While the invention has been shown and described with reference to a certain preferred embodiment thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Number | Date | Country | Kind |
---|---|---|---|
10-2008-0014649 | Feb 2008 | KR | national |
10-2008-0019373 | Feb 2008 | KR | national |
10-2008-0117264 | Nov 2008 | KR | national |
10-2009-0007662 | Jan 2009 | KR | national |