This application claims priority under 35 U.S.C. §119(a) to Korean Patent Applications filed in the Korean Intellectual Property Office on Nov. 2, 2009, Mar. 26, 2010, Jun. 9, 2010, and Aug. 24, 2010, which were assigned Serial Nos. 10-2009-0105092, 10-2010-0027322, 10-2010-0054388, and 10-2010-0082182, respectively, the disclosures of all of which are hereby incorporated by reference.
1. Field of the Invention
The present invention relates generally to a communication system using linear block codes, and more particularly, to a transmission/reception apparatus and method for generating linear block codes in a specific form.
2. Description of the Related Art
In wireless communication systems, link performances are significantly degraded by various noises, fading, and Inter-Symbol Interference (ISI) of channels. Therefore, to realize high-speed digital communication systems requiring high data throughput and reliability, such as a next-generation mobile communication system, a digital broadcasting system, and a mobile Internet system, it is important to develop technologies for coping with the noises, fading, and ISI. Recently, error-correcting codes have been studied to improve communication reliability by efficiently restoring information distortion.
A Low-Density Parity Check (LDPC) code will be referred to herein as an example of a linear block code, but the present invention is not limited to the LDPC code.
The LDPC code is commonly represented using a graph representation, and its many characteristics can be analyzed by graph theory and methods based on algebra and probability theory. Generally, a graph model of channel codes is not only useful in code description, but also can be regarded as a communication network in which vertexes exchange messages through edges, if information about encoded bits are mapped to vertexes in the graph and relationships between the bits are mapped to edges in the graph, thus making it possible to derive a natural decoding algorithm. For example, in a trellis, which is a kind of graph, a derived decoding algorithm may include the well known Viterbi algorithm, and Bahl, Cocke, Jelinek, and Raviv (BCJR) algorithm.
The LDPC code is generally defined as a parity check matrix, and can be represented using a bipartite graph, which is referred to as a Tanner graph. In the bipartite graph, vertexes are divided into two different types, and the LDPC code is represented by a bipartite graph including vertexes called variable nodes and check nodes. The variable nodes are mapped to encoded bits on a one to one basis.
Referring to
Referring to
In the Tanner graph of the LDPC code, a degree of each of a variable node and a check node indicates the number of edges connected to the node, and is equal to the number of entries whose values are not ‘0’ in a row or a column corresponding to the node in the parity check matrix of the LDPC code. For example, in
In order to express degree distribution for nodes of an LDPC code, assuming that a ratio of the number of variable nodes with degree=i to the total number of variable nodes is fi, and a ratio of the number of check nodes with degree=j to the total number of check nodes is gi, in the LDPC code corresponding to
In Equation (1), the density of ‘1’ decreases with an increase in N in the parity check matrix. Generally, because for an LDPC code, the density of non-zero entries is inversely proportional to the codeword length N, an LDPC code with a large value for N has a very low density. The wording ‘low density’ in the name of the LDPC code was derived from this principle.
Referring to
In the parity check matrix of
In the parity check matrix, an information word part consisting of 0-th to (K1−1)-th columns has a structure, which is formed according to the following rules.
Rule (1): A total of K1/M1 column groups are generated by grouping K1 columns for the information word into M1 groups in the parity check matrix. Each column in each column group is formed according to Rule (2) below.
Rule (2): First, locations of 1 in each 0-th column in an i-th column group (where i=0, 1, . . . , K1/M1−1) are determined. A degree of a 0-th column in an i-th column group is represented by Di. If locations of rows with 1 are Ri,0(1), Ri,0(2), . . . , Ri,0(D
R
i,j
(k)
=R
i,(j-1)
(k)
+q mod(Ni−K1) (2)
According to the rules above, degrees of columns in an i-th (i=0, 1, . . . , K1/M1−1) column group are all Di.
As a more detailed example, as to each 0-th column in each of three column groups for N1=30, K1=15, M1=5, q=3, location information of rows with 1 can be represented as follows. For example, if {0, 1, 2} is a 0-th column group, {0, 1, 2} indicates that 1 exists in a 0-th row, a 1-st row and a 2-nd row in a 0-th column in the 0-th column group.
For information about rows with 1 in each 0-th column in each column group, only location information may be represented on a column group basis for convenience, as follows:
That is, the sequence sequentially represents information about rows with 1 for a 0-th column in an i-th column group.
By making a parity check matrix using the information in the above detailed example, and Rules (1) and (2), an LDPC code having the same concept as that of the LDPC code with the structure of
Next, reference will be made to a process of performing LDPC encoding using the parity check matrix.
For convenience, information bits with a length K1 are represented by (i0, i1, . . . , iK
Encoding Method of an LDPC Code
Step 1: Parity bits are initialized.
p0=p1= . . . =pN
Step 2: Information about rows with 1 in a 0-th column in a first column group of an information word is called from information about the stored parity check matrix.
R
1,0
(1)=0,R1,0(2)=2084,R1,0(3)=1613,R1,0(4)=1548,R1,0(5)=1286,R1,0(6)=1460,R1,0(7)=3196,R1,0(8)=4297,R1,0(9)=2481,R1,0(10)=3369,R1,0(11)=3451,R1,0(12)=4620,R1,0(13)=2622
Using the called information and information bit i0, specific parity bits px are updated as shown in Equation (3) below, where x is a value of R1,0(k), for k=1, 2, . . . , 13.
p0=p0⊕i0,p2048=p2048⊕i0,p1613=p1613⊕i0,p1548=p1548⊕i0,p1286=p1286⊕i0,p1460=p1460⊕i0,p3196=p3196⊕i0,p4297=p4297⊕0,p2481=p2481⊕i0,p3369=p3369⊕i0,p3451=p3451⊕i0,p4620=p4620⊕i0,p2622=p2622⊕i0 (3)
In Equation (3), ⊕ represents binary addition, and px=px⊕i0 is exchangeable with px←px⊕i0.
Step 3: For the next 359 information bits i1, i2, . . . , i359 succeeding i0, a value of Equation (4) below is obtained.
{x+(m mod M1)×q} mod(N1−K1),m=1,2, . . . ,359 (4)
In Equation (4), x is a value of R1,0(k), for k=1, 2, . . . , 13. It is to be noted that Equation (4) is similar in concept to Equation (2).
Using the values obtained in Equation (4), an operation similar to that of Equation (3) is performed. That is, p{x+(m mod M
For example, for m=1, i.e., for i1, p{x+q} mod(N
p15=p15⊕i1,p2099=p2099⊕i1,p1628=p1628⊕i1,p1563=p1563⊕i1,p1301=p1301⊕i1,p1475=p1475⊕i1,p3211=p3211⊕i1,p4312=p4312⊕i1,p2496=p2496⊕i1,p3384=p3384⊕i1,p3466=p3466⊕i1,p4635=p4635⊕i1,p2637=p2637⊕i (5)
It is to be noted that in Equation (5), q=15. The above process is performed in a similar manner for m=1, 2, . . . , 359.
Step 4: Like in Step 2, information about R2,0(k) (k=1, 2, . . . , 13) is called for a 361st information bit i=360 to update specific parity bits px, where x is R2,0(k). For the next 359 information bits succeeding i361, i362, . . . , i719 succeeding i=360, p{x+(m mod M
Step 5: For each of 360 information bit groups, Steps 2, 3, and 4 are repeated. Finally, parity bits are determined using Equation (6) below.
p
i
=p
i
⊕p
i−1
,i=1,2, . . . ,N1−K1−1 (6)
In Equation (6), bits pi are parity bits that have completely undergone LDPC encoding.
Accordingly, using the above-described LDPC encoding method, encoding is performed through Steps 1 through 5.
It is well known that performances of common LDPC codes are closely related to cycle characteristics of the Tanner graph. In particular, it has been determined through experimentation that performance degradation may occur if there are many short-length cycles in the Tanner graph. Therefore, to design LDPC codes having excellent performance, cycle characteristics on the Tanner graph should be considered.
Briefly, the cycle characteristics are the number of nodes by which an edge has passed while in the Tanner graph, the edge starting at one variable node returns to the variable node after passing by at least one check node and other variable nodes. For example, in
However, it is very difficult to design a parity check matrix of a very large LDPC code whose codeword length is about tens of thousands of bits, considering cycle characteristics on the Tanner graph. Actually, no design method has yet been proposed, which improves cycle characteristics of LDPC codes having the specific structure of FIG. 3. In reality, in LDPC codes having the above structure, an error floor is observed at a high Signal to Noise Ratio (SNR), because optimization of cycle characteristics on the Tanner graph is not considered.
Accordingly, for designing LDPC codes having the specific structure of
Additionally, in European digital broadcasting standards using the LDPC code, the possible number of lengths of a coded block of the LDPC code is only two due to the limited use of the code, and to support even these two block lengths, different parity check matrixes are stored.
However, to apply LDPC codes to an actual communication system, the LDPC codes should be designed to be suitable to data throughput required in the communication system. Particularly, LDPC codes having various block lengths are required to support various data throughputs upon a user's request, not only in adaptive communication systems utilizing Hybrid Automatic Retransmission reQuest (HARQ) and Adaptive Modulation and Coding (AMC), but also in a communication system supporting various broadcast services.
In addition, because storing an independent parity check matrix for each block length of an LDPC code reduces memory efficiency, there is a need to study a new method for efficiently supporting various block lengths from the given existing parity check matrix, without designing a new parity check matrix.
Accordingly, the present invention is designed to address at least the above-described problems and/or disadvantages and to provide at least the advantages described below. An aspect of the present invention is to provide a parity check matrix generation method for generating a linear block code having a variable block length in a communication system.
Another aspect of the present invention is to provide a parity check matrix generation method for generating a structured LDPC code having a variable block length in a communication system.
Another aspect of the present invention is to provide a transmission/reception method and apparatus using the parity check matrix generation method.
Another aspect of the present invention is to provide a method and apparatus for efficiently generating a parity check matrix of an LDPC code by suboptimizing cycle characteristics in designing an LDPC code having a specific structure.
Another aspect of the present invention is to provide a method and apparatus for encoding and decoding an LDPC code having a variable block length by suboptimizing cycle characteristics from one parity check matrix in a communication system using LDPC codes.
Another aspect of the present invention is to provide a method and apparatus for generating LDPC codes having different block lengths from a parity check matrix designed by suboptimizing cycle characteristics, to improve efficiency of a memory for storing LDPC codes.
In accordance with an aspect of the present invention, a method is provided for generating a parity check matrix used to generate a linear block code in a communication system. The method includes determining a basic parameter of a second parity check matrix satisfying a rule predetermined with respect to a given first parity check matrix; generating a submatrix corresponding to a parity part of the second parity check matrix, using the basic parameter; and generating a submatrix corresponding to an information word part of the second parity check matrix, using the first parity check matrix and the basic parameter.
In accordance with another aspect of the present invention, a method is provided for encoding a linear block code using the second parity check matrix generated according to the above method.
In accordance with another aspect of the present invention, a method is provided for decoding the linear block code using the second parity check matrix generated according to the above method.
In accordance with another aspect of the present invention, a transmission apparatus in a communication system is provided. The apparatus includes an encoder for encoding an information work into a linear block code; a transmitter for transmitting the linear block code; and a controller for determining a second parity check matrix from a given first parity check matrix according to the linear block code, and controlling the encoder to perform encoding using the second parity check matrix. The controller determines a basic parameter of the second parity check matrix satisfying a rule predetermined with respect to the given first parity check matrix, generates a submatrix corresponding to a parity part of the second parity check matrix, using the basic parameter, and generates a submatrix corresponding to an information word part of the second parity check matrix, using the first parity check matrix and the basic parameter.
In accordance with another aspect of the present invention, a reception apparatus in a communication system is provided. The apparatus includes a receiver for receiving a signal transmitted over a communication network; a decoder for decoding the received signal encoded in a linear block code, into an information word; and a controller for determining a second parity check matrix from a given first parity check matrix according to the linear block code, and controlling the decoder to perform decoding using the second parity check matrix. The controller determines a basic parameter of the second parity check matrix satisfying a rule predetermined with respect to the given first parity check matrix, generates a submatrix corresponding to a parity part of the second parity check matrix, using the basic parameter, and generates a submatrix corresponding to an information word part of the second parity check matrix, using the first parity check matrix and the basic parameter.
The above and other aspects, features, and advantages of certain embodiments of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:
Throughout the drawings, the same drawing reference numerals will be understood to refer to the same elements, features and structures.
Various embodiments of the present invention will now be described in detail with reference to the accompanying drawings. In the following description, specific details such as detailed configuration and components are merely provided to assist the overall understanding of these embodiments of the present invention. Therefore, it should be apparent to those skilled in the art that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the invention. In addition, descriptions of well-known functions and constructions are omitted for clarity and conciseness.
In accordance with an embodiment of the present invention, a method for generating a parity check matrix of an LDPC code, for example, a linear block code, is provided. It should be noted that the parity check matrix generation method described below may be applied in the same way to other linear block codes that use a parity check matrix, not just an LDPC code.
Methods for generating a parity check matrix of a large-sized LDPC code from a parity check matrix of a given basic small-sized LDPC code are provided below. In addition, an apparatus for supporting a variable block length in a communication system using LDPC codes in a specific shape, and a method for controlling the same are also provided. It should be apparent to those skilled in the art that a parity check matrix of a small-sized LDPC code may be generated from a parity check matrix of a given large-sized LDPC code using the following methods. However, the present invention is not limited to supporting all of the designed variable block lengths.
For convenience of description, an LDPC code will have the same structure as the LDPC code designed based on Rules (1) and (2) of the prior art, as illustrated in
Locations of rows with 1 in each 0-th column in an i-th (i=0, 1, . . . , K1/M1−1) column group, representing information about the parity check matrix H1, are Ri,0(1), Ri,0(2), . . . , Ri,0(D
In accordance with an embodiment of the present invention, a method is provided for designing a second parity check matrix H2 satisfying the following rules. A codeword length and an information word length of the parity check matrix H2 are N2 and K2, respectively.
Rule (3): For a positive integer p, N2=pN1, K2=pK1, and M2=pM1. Therefore, K2/M2=K1/M1 is satisfied, assuring that H2 is equal to H1 in the number of column groups in the information word part. In addition, (N2−K2)/M2=q=(N1−K1)/M1 is given.
Rule (4): H2 and H1 are equal in degree distribution for the information word part. Locations of rows with 1 in each 0-th column in an i-th (i=0, 1, . . . , K2/M2−1) column group of the parity check matrix H2 are Si,0(k) Si,0(k), for (k=1, 2, . . . , Di), where Di is a degree of a 0-th column in an i-th column group.
Rule (5): Cycle characteristics on a Tanner graph of H2 should be equal to or better than cycle characteristics on a Tanner graph of H1.
Rule (6): H1 should be able to be generated from information about H2.
Rule (7): An LDPC code defined by H1 should be able to be encoded using information about H2.
In accordance with an embodiment of the present invention, the following method is provided for generating a parity check matrix of an LDPC code, as illustrated in the flowchart of
Method of Generating Parity Check Matrix of LDPC Code
Referring to
In step 520, a submatrix corresponding to parity bits of the parity check matrix H2 is defined in a predetermined structure. More specifically, the operation of step 520 includes the following Steps 1 and 2.
Step 1: An (N2−K2)×(N2−K2) matrix having the same structure as that of a submatrix corresponding to the parity bits of
Step 2: ‘i’ is initialized to 0 (i=0).
In step 530, a sequence corresponding to information bits of the given parity check matrix H1 is called. More specifically, the operation of step 530 includes the following Step 3.
Step 3: For each component of a sequence Ri,0(k) (k=1, 2, . . . , Di) representing information about an i-th column group corresponding to information bits of the parity check matrix H1, a set Ai(k) consisting of p elements is defined.
In step 540, from the sequence representing the parity check matrix H1, a sequence corresponding to information bits is determined in the parity check matrix H2 using the following Step 4.
Step 4: Assuming that components of a submatrix corresponding to (i+1)-th through ((N2−K2)/M2−1)-th column groups, which correspond to information bits in the parity check matrix H2, are all zero (0), sequences Si,0(k) (k=1, 2, . . . , Di) satisfying the following conditions are sequentially obtained.
Condition (1)
Si,0(k)εAi(k),for k=1,2, . . . ,Di
Condition (2)
Among sequences satisfying Condition (1), if there are several sequences having the best cycle characteristics on the Tanner graph, i.e., if there are several best sequences, then one of them is selected arbitrarily.
Step 5: For *i=1, . . . , (N2−K2)/M2−1, Steps 3 and 4 are repeated. That is, step 530 and step 540 are repeated for i=1, . . . , (N2−K2)/M2−1, although not illustrated in
In accordance with an embodiment of the present invention, Ai(k) is generated in Step 3 above, using Equation (7) or Equation (8) below.
A
i
(k)
={R
i,0
(k)
,R
i,0
(k)+(N1−K1), . . . ,Ri,0(k)+(p−1)×(N1−K1)} (7)
A
i
(k)={(Ri,0(k)−si(k))×p+si(k)·(Ri,0(k)−si(k))×p+s1(k)−q} . . . ,(Ri,0(k)−si(k))×p+s1(k)−(p−1)×q (8)
In Equation (8), si(k) (k=0, 1, . . . , Di−1) is defined as shown in Equation (9) below.
s
i
(k)
=R
i
(k) mod q,k=0,1, . . . ,Di−1 (9)
For a better understanding of the method illustrated in
The major parameters used to describe the example of
Reference will now be made to
Because location information of rows with 1 in a 0-th column in the column group of
For location information of the eight rows, column structures are sequentially represented as indicated by reference numeral 701 in
Assuming that in the location information of the eight rows, a sequence satisfying Conditions (1) and (2) through Step 4 was {0,5,16} or a second candidate 703, a 0-th column in the new column group may be defined as a column, of which row length is 18 and in which 1 exists in each of 0-th row, 5-th row and 16-th row.
Now, 1-st through 5=(M2−1)-th columns will be generated by applying the method of generating an LDPC code in the form of
Referring to
Referring to
Because location information of rows with 1 in a 0-th column in the column group of
For location information of the eight rows, column structures are sequentially represented as indicated by reference numeral 901 in
Assuming that in the location information of the eight rows, a sequence satisfying Conditions (1) and (2) through Step 4 is {0,10,15} or a second candidate 903, a 0-th column in the new column group may be defined as a column, of which row length is 18 and in which 1 exists in each of 0-th row, 10-th row and 15-th row.
Now, 1-st through 5=(M2−1)-th columns will be generated by applying the method of generating an LDPC code in the form of
Referring to
As description will now be provided to show that the method illustrated in
Rules (3) and (4) are satisfied on the basic assumptions of the method.
Referring to Rule (5), assuming that Si,0(k)=Ri,0(k) for all i and k in Step 4, because the structure of the parity check matrix H1 was applied to the parity check matrix H2 in the same way, H2 is equal to H1 in cycle characteristics on a Tanner graph. In this case, therefore, Rule (5) is satisfied.
However, because a sequence having the best cycle characteristics on a Tanner graph is selected in Step 4, a sequence having cycle characteristics better than or equal to those of Si,0(k)=Ri,0(k) is selected for all i and k. That is, it is noted that the worst case may not occur in which cycle characteristics deteriorate, even though it is guaranteed that the cycle characteristics are equal. Therefore, it is noted that Rule (5) is satisfied by Step 4.
Referring to Rule (6), information about column groups representing the parity check matrix H2 is defined as Si,0(k), (i=0, 1, . . . , (N2−K2)/M2−1), k=1, 2, . . . , Di). When Equation (7) is used in Step 3, Si,0(k) has a form such as Si,0(k)=Ri,0(k)+l×(N1−K1) for a certain integer l. Because N1 and K1 are known values, Ri,0(k) can be extracted from Si,0(k) using Equation (10) below.
R
i,0
(k)
=S
i,0
(k) mod(N1−K1) (10)
Similarly, when Equation (8) is used in Step 3, Si,0(k) has a form such as (Ri,0(k)−si(k))×p+si(k)−l×q for a certain integer 1.
It is noted that because (Ri,0(k)−si(k)) is a multiple of q, Ri,0(k) can be easily extracted from Si,0(k) even though a value of Ri,0(k) is unknown, because of si(k)=Ri,0(k) mod q=Si,0(k) mod q. Also, because p and q are already known values, Ri,0(k) can be easily extracted from Si,0(k) using Equation (11).
Referring to Equations (10) and (11), if information about column groups of the parity check matrix H2 is known, values of Ri,0(k) can be obtained through simple operations without separately storing the values. In addition, because H1 and H2 are equal even in q, H1 can be obtained from Ri,0(k) acquired from Si,0(k), thereby satisfying Rule (6).
Referring to Rule (7), all LDPC codes defined by H1 and H2 can be encoded as described in the rules of the prior art. When a code word length, an information word length, and a value of q are given, encoding is performed using only information about rows with 1 in a 0-th column in each column group of the information word. Because Ri,0(k) can be obtained from Si,0(k) by Rule (6), Rule (7) is satisfied.
While H2 is obtained from H1 in the description above, by way of example, a larger parity check matrix may be obtained by repeating the method, as illustrated in
In summary, efficient parity check matrixes may be designed by repeatedly applying the method illustrated in
N1|N2 . . . |Ns (12)
K1|K2 . . . |Ks (13)
M1|M2 . . . |Ms (14)
In addition, if only information about a parity check matrix Hs obtained by the method of
It is noted that by satisfying Rule (6), the parity check matrix of an LDPC code, proposed by an embodiment of the present invention, may generate parity check matrixes having various sizes from one parity check matrix. It is also noted that because a size of a parity check matrix indicates a codeword length of its LDPC code, an LDPC code generated by the method proposed in accordance with an embodiment of the present invention can support LDPC codes having various block lengths using Equation (10) or Equation (11). Despite the support of LDPC codes with various block lengths, information about only one parity check matrix is stored, thereby ensuring the high memory efficiency.
In accordance with an embodiment of the present invention, a parity check matrix H2 is efficiently generated by applying the method illustrated in
M1=1,N1=48,K1=10,q=38p1=90,M2=90,N2=4320,K2=900 (15)
M1=1,N1=48,K1=12,q=36p1=90,M2=90,N2=4320,K2=1080 (16)
M1=1,N1=48,K1=16,q=32p1=90,M2=90,N2=4320,K2=1440 (17)
M1=1,N1=48,K1=24,q=24p1=90,M2=90,N2=4320,K2=2160 (18)
M1=1,N1=48,K1=30,q=18p1=90,M2=90,N2=4320,K2=2700 (19)
M1=1,N1=48,K1=32,q=16p1=90,M2=90,N2=4320,K2=2880 (20)
Table 1 shows an example of a parity check matrix representing location information of rows with 1 in each 0-th column in a parity check matrix consisting of 10 column groups. {122, 149, . . . , 2773} represent locations of rows with 1 in a 0-th column in a 0-th column group, {167, 279, . . . , 2681} represent locations of rows with 1 in a 0-th column in a 1-st column, and {866, 1229, 2661} represent locations of rows with 1 in a 0-th column in a 9-th column. The parity check matrixes represented by Tables 2-41 below can also be construed in the same way.
In accordance with another embodiment of the present invention, parity check matrixes H2 and H3 are efficiently generated by applying the method of
M1=1,N1=48,K1=10,q=38p1=30,M2=30,N2=1440,K2=300p2=3,M3=90,N3=4320,K3=900 (21)
M1=1,N1=48,K1=12,q=36p1=30,M2=30,N2=1440,K2=360p2=3,M3=90,N3=4320,K3=1080 (22)
M1=1,N1=48,K1=16,q=32p1=30,M2=30,N2=1440,K2=480p2=3,M3=90,N3=4320,K3=1440 (23)
M1=1,N1=48,K1=24,q=24p1=30,M2=30,N2=1440,K2=720p2=3,M3=90,N3=4320,K3=2160 (24)
M1=1,N1=48,K1=30,q=18p1=30,M2=30,N2=1440,K2=900p2=3,M3=90,N3=4320,K3=2700 (25)
M1=1,N1=48,K1=32,q=16p1=30,M2=30,N2=1440,K2=960p2=90,M3=90,N3=4320,K3=2880 (26)
In accordance with another embodiment of the present invention, parity check matrixes H2 and H3 are efficiently generated by applying the method of
M1=1,N1=48,K1=9,q=39p1=30,M2=30,N2=1440,K2=270p2=3,M3=90,N3=4320,K3=810 (27)
M1=1,N1=48,K1=16,q=32p1=30,M2=30,N2=1440,K2=480p2=3,M3=90,N3=4320,K3=1440 (28)
M1=1,N1=48,K1=21,q=27p1=30,M2=30,N2=1440,K2=630p2=3,M3=90,N3=4320,K3=1890 (29)
M1=1,N1=48,K1=28,q=20p1=30,M2=30,N2=1440,K2=840p2=3,M3=90,N3=4320,K3=2520 (30)
M1=1,N1=48,K1=32,q=16p1=30,M2=30,N2=1440,K2=960p2=3,M3=90,N3=4320,K3=2880 (31)
In accordance with another embodiment of the present invention, a parity check matrix H2 is efficiently generated by applying the method of
M1=1,N1=48,K1=16,q=32p1=90,M2=90,N2=4320,K2=1440 (32)
M1=1,N1=48,K1=16,q=27p1=90,M2=90,N2=4320,K2=1890 (33)
M1=1,N1=48,K1=28,q=20p1=90,M2=90,N2=4320,K2=2520 (34)
M1=1,N1=48,K1=32,q=16p1=90,M2=90,N2=4320,K2=2880 (35)
In accordance with another embodiment of the present invention, a parity check matrix H2 is efficiently generated by applying the method of
M1=1,N1=48,K1=9,q=39p1=90,M2=90,N2=4320,K2=810 (36)
M1=1,N1=48,K1=16,q=32p1=90,M2=90,N2=4320,K2=1440 (37)
M1=1,N1=48,K1=21,q=27p1=90,M2=90,N2=4320,K2=1890 (38)
M1=1,N1=48,K1=28,q=20p1=90,M2=90,N2=4320,K2=2520 (39)
M1=1,N1=48,K1=32,q=16p1=90,M2=90,N2=4320,K2=2880 (40)
In accordance with another embodiment of the present invention, a parity check matrix H2 is efficiently generated by applying the method of
M1=1,N1=60,K1=12,q=48p1=72,M2=72,N2=4320,K2=864 (41)
M1=1,N1=60,K1=15,q=45p1=72,M2=72,N2=4320,K2=1080 (42)
M1=1,N1=60,K1=20,q=40p1=72,M2=72,N2=4320,K2=1440 (43)
M1=1,N1=60,K1=25,q=35p1=72,M2=72,N2=4320,K2=1800 (44)
Referring to
The LDPC encoder 1111 and the LDPC decoder 1133 select a parity check matrix according to a block length required by the communication system, and perform encoding and decoding thereon using a predetermined encoding/decoding scheme. Particularly, in accordance with an embodiment of the present invention, the LDPC encoder 1111 and the LDPC decoder 1133 support various block lengths in an LDPC code by generating a parity check matrix of a large-sized LDPC code from a parity check matrix of a small-sized LDPC code or by generating a parity check matrix of a small-sized LDPC code from a parity check matrix of a large-sized LDPC code, or may support various block lengths using a parity check matrix of an LDPC code having the longest block length, without separately storing parity check matrixes of LDPC codes having different block lengths.
The transmission apparatus includes an LDPC code parity check matrix extractor 1210, a controller 1230, and an LDPC encoder 1250.
The LDPC code parity check matrix extractor 1210 extracts an LDPC code parity check matrix according to system requirements. The LDPC code parity check matrix may be extracted from the sequence information finally obtained by the method illustrated in
The controller 1230 determines a required parity check matrix according to a codeword length or an information word length to meet the system requirements. Accordingly, the controller 1230 may include the LDPC code parity check matrix extractor 1210.
The LDPC encoder 1250 performs encoding based on information about the LDPC code parity check matrix, called by the controller 1230 and the LDPC code parity check matrix extractor 1210.
The reception apparatus includes a demodulator 1310, a parity check matrix determiner 1330, a controller 1350, an LDPC code parity check matrix extractor 1370, and an LDPC decoder 1390.
The demodulator 1310 receives and demodulates an LDPC code, and transfers the demodulated signal to the parity check matrix determiner 1330 and the LDPC decoder 1390.
The parity check matrix determiner 1330, under control of the controller 1350, determines a parity check matrix of an LDPC code used in the system, from the demodulated signal.
The controller 1350 transfers the determination made by the parity check matrix determiner 1330 to the LDPC code parity check matrix extractor 1370 and the LDPC decoder 1390.
The LDPC code parity check matrix extractor 1370, under control of the controller 1350, extracts a parity check matrix of an LDPC code required by the system and transfers the extracted parity check matrix to the LDPC decoder 1390. Alternatively, the controller 1350 may include at least one of the parity check matrix determiner 1330 and the LDPC code parity check matrix extractor 1370. The LDPC code parity check matrix may be extracted from the sequence information finally obtained by the method of
The LDPC decoder 1390, under control of the controller 1350, performs decoding based on the received signal transferred from the demodulator 1310 and information about the LDPC code parity check matrix transferred from the LDPC code parity check matrix extractor 1370.
In step 1410, the parity check matrix determiner 1330 determines, from a received signal, a parity check matrix of an LDPC code used in the system. In step 1420, the controller 1350 transfers information about the parity check matrix of the LDPC code to the LDPC code parity check matrix extractor 1370 and the LDPC decoder 1390, as a result of the determination made by the parity check matrix determiner 1330. In step 1430, the LDPC code parity check matrix extractor 1370 extracts a parity check matrix of the LDPC code required in the system, and delivers it to the LDPC decoder 1390. In step 1440, the LDPC decoder 1390 decodes the received parity check matrix of the LDPC code.
While the examples of
As is apparent from the foregoing description, according to the above-described embodiments of the present invention, a parity check matrix of a linear block code having a very long codeword length can be efficiently designed from a small-sized parity check matrix while maintaining suboptimized cycle characteristics on a Tanner graph.
In addition, the present invention can generate linear block codes having various block lengths using information about a parity check matrix given in a communication system using linear block codes. Because linear block codes having various block lengths can be supported from one parity check matrix, parity check matrix information can be efficiently stored, facilitating system expansion.
While the present invention has been shown and described with reference to certain embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims and their equivalents.
Number | Date | Country | Kind |
---|---|---|---|
10-2009-0105092 | Nov 2009 | KR | national |
10-2010-0027322 | Mar 2010 | KR | national |
10-2010-0054388 | Jun 2010 | KR | national |
10-2010-0082182 | Aug 2010 | KR | national |