Patent Application
20060133607
This invention relates to cryptographic keys, and more particularly to apparatus and methods for generating cryptographic keys.
In computer systems, cryptographic keys are used to control access to code or data. The keys always have to be passed across some medium, which can then be tapped to allow possible interception of the keys. In a secure system, a root key can be used to establish a primary root of trust, upon which the various keys and other security mechanisms are built. Root keys have been produced and stored using mechanisms, which are susceptible to software, network, and insider attacks that can compromise the root key during manufacture, distribution, and use of the system.
Keys in secure systems have been stored in non-volatile memories, including fuse/anti-fuse, EEPROM, flash, ROM, ferro-RAM, magneto-resistive RAM, and battery backed memories. However, these implementations involve human or machine interaction with the target device for generation and programming of the key or root key. This process inherently reveals the key to one or more machines, transports, and humans. This creates multiple opportunities for the key to be recorded and/or compromised. Additionally, these historical implementations store the key in a location in the system that is accessible to the host computer operating system or its ports, creating an additional opportunity for compromise after the computing system is delivered and put into service.
Technology exists to establish an identifier, for circuits implemented in silicon, without historical generation of a number and the associated programming of a non-volatile element. This technology, referred to as a silicon identifier, utilizes the randomness in the threshold voltage (Vt) of any transistor, in conjunction with a comparator, to generate identifier bits on the silicon without requiring a programming step. The identifier bits form an identification (ID) data word that is a function of the natural randomness in the threshold voltages in silicon transistors. The comparator compares Vt with a threshold voltage and produces a 0 or a 1 value in response to the comparison. The 0 or 1 becomes a bit in the data word.
A limitation of this technology is that transistors with Vt values that are very similar to the threshold value can result in a compared value that varies with time, temperature, voltage, and noise levels. Thus, due to environmental conditions, these transistors will sometimes produce a 1 and at other times produce a 0 value. Nevertheless, the silicon ID, is still “statistically unique”, meaning it can be determined with high probability which ID in the field corresponds to an ID realized in the factory.
For a security key, it is important that the bits of the key remain constant over time. If silicon ID technology is used to generate a key, there is a need for a method of achieving a stable ID over time.
This invention provides an apparatus comprising a circuit for generating a secret root key having bits representative of threshold voltages, and an error correction module for correcting errors in bits of the secret root key to produce a corrected secret root key.
The invention also encompasses a method of producing a secret root key for an electronic device. The method comprises: producing a plurality of logic ones and zeros in response to transistor threshold voltages, and error correcting the plurality of logic ones and zeros to produce a corrected secret root key.
In another aspect, the invention provides a data storage system comprising a storage medium, a controller including a cryptographic and security module for encrypting and decrypting data to be stored in and retrieved from the storage medium, wherein the cryptographic and security module includes a circuit for generating a secret root key having bits representative of threshold voltages and an error correction module for correcting errors in bits of the secret root key to produce a corrected secret root key.
This invention provides apparatus and methods for generating and using a secret key that can be contained within a confined electronics module. The secret key can be employed in apparatus such that the secret key is never visible outside this electronics module.
The method for producing the secret key improves upon the statistically unique silicon identifier technology by incorporating error correcting code (ECC) circuitry to create a secret key that does not change over time.
The silicon ID circuit produces an array of bits that are delivered on a bus 14 to error correction module 16. The bits delivered on bus 14 form an uncorrected secret root key. The error correction module includes a register 18 for storing an error correction code/error detection code (ECC/EDC) value, and error correction and error detection logic 20 for detecting correcting errors in the silicon ID data word. The ECC/EDC value contains two values, the first is the ECC or Error Correcting Code Value, and the second is the EDC or Error Detection Code Value. The corrected secret root key can be read on a bus 22 and the computed ECC/EDC value can be read on bus 24. A control and status register 28 is accessible via a write/read control bus 30.
Upon any power-up of the key apparatus in
The circuit of
The silicon identifier block requires no programming and the random, secret, statistically unique identifier is present after manufacture of the silicon device. The ECC circuitry is employed to generate an ECC value for correction of the instability of the identifier (ID) over the life of the device. The error correcting code can be varied with the nature of the statistics of the errors and will vary in its strength. For example, Reed-Solomon type coding can be used.
Reed-Solomon error correction is a coding scheme that works by first constructing a polynomial from the data bits. Because of the redundant information contained in the polynomial data, it is possible to reconstruct the original polynomial and thus the data bits even in the face of errors, up to a certain degree of error.
Reed Solomon codes are linear block codes. A Reed-Solomon code is specified as RS (n, k) with s-bit symbols. This means that the encoder takes k data symbols of s bits each and adds parity symbols to make an n symbol codeword. There are n−k parity symbols of s bits each. A Reed-Solomon decoder can correct up to t symbols that contain errors in a codeword, where 2t=n−k.
Additionally, the error correcting code can include capability for detecting that an error exists (Error Detecting Code or EDC). Error detection is used to determine whether the key has been corrupted. In one example, the error correction module constructs a value (called a checksum) that is a function of the message. The error detector can then use the same function to calculate the checksum of the received key and compare it with the appended checksum to see if the key was correctly received.
Silicon ID technology can be used to realize a unique and secret identifier for use as a root cryptographic key in the disc drive.
The symmetric cipher block 42 is used to provide symmetric encryption of data. In one example the symmetric encryption module can include Advanced Encryption Standard (AES) and Triple Data Encryption Standard (TDES) algorithms. The hash module 44 is provided for hashing of data. The hash module can be implemented using an SHA-1 algorithm. The asymmetric encryption acceleration module 50 can use, for example, a 1024 and 2048 bit Rivest, Shamir, Adleman (RSA) algorithm.
The system microprocessor interface 48 provides the connection between the cryptographic and security module and the system microprocessor. This connection is used to transfer commands to and retrieve status from the cryptographic and security module. In one embodiment, this connection is a parallel address and data bus, but it may also be implemented with a serial port connection. The system microprocessor interface can also include a hardware interrupt signal line that attaches directly to the system microprocessor interrupt controller. This interrupt would be used to notify the system microprocessor of the completion of a command, and of results available in the buffer.
The cryptographic and security module connects to a DRAM controller 64 and a drive microprocessor 66 as shown in
A monotonically increasing counter circuit 74 provides for secure knowledge of relative time. The cryptographically good random number generator 56 provides random numbers with technical infeasibility of prediction. The key store 54 can be a volatile memory for storing temporary keys.
The command controller 60 is provided for receipt and decoding of commands received from the system microprocessor and for tasking of the sub-circuitry. The command controller has the primary responsibility for decoding commands and setting microprocessor sub-blocks for the desired operation, and data flow. The command controller can also sequence the operations required to perform the RSA computations. The command controller has the primary responsibility for decoding commands and setting microprocessor sub-blocks for the desired operation, and data flow. The command controller is also expected to sequence the operations required to perform the RSA computations.
To preserve the integrity of the access to the cryptographic and security module, it is important that there be no alternate accessibility to the cryptographic and security module, outside of the defined command interface described above. This will ensure that attackers cannot make malicious access to the module using debug or manufacturing pathways. Because of these constraints, the module can include an internal self-test unit.
This self-test unit can be used to verify the correct functionality of the module while preventing “back-door” access to the cryptographic and security module. The self-test module can also be invoked during normal operation of the chip, in a drive, to verify continued correct functionality of the cryptographic and security module. The self-test hardware 58 autonomously ensures correct functionality of the cryptographic and security circuitry.
The cryptographic and security module is coupled to the disc unit 76 through the buffer access and arbitration unit 64. A buffer memory 78 stores various information designated as source data, result data, command queue, and result queue. The buffer manager provides buffer access and arbitration. A host unit 80 interacts with the buffer manager. The drive microprocessor 66 is coupled to the host unit, buffer manager, disc unit, and the cryptographic and security module.
The random number generator (RNG) 56 provides cryptographically good random numbers, meaning that it is technically infeasible to predict what any given number will be. In addition to the random number generation, the block will work in conjunction with the system microprocessor to provide a randomness quality monitor and to generate random primes to be used in RSA key-pair generation.
The random number generator provides random numbers for the following: a random number for the root key 52, random numbers to be distributed within the crypto block to other crypto sub-blocks, random numbers for the system microprocessor, and a stream of random numbers to be stored in the buffer memory and potentially on the disc.
Error correction can be provided as illustrated in
In the disc drive example, the ECC correction value is returned to the system microprocessor and stored to the non-volatile disc drive medium and/or other non-volatile storage element on the disc drive circuit board. On every subsequent initialization of the secret key, the secret key will default to the disabled state and operations with the secret key will not be allowed until the secret key is initialized. On each initialization, the ECC module will be loaded with the ECC correction value and each use of the silicon identifier will have the ECC correction value invoked. Upon determination of an error, the ECC module will perform the correction, and provide the corrected secret key to its output, to be used by the security and cryptographic elements in an associated electronics module.
When used in a disc drive, the secret key is only accessible within a cryptographic and security electronics module. The cryptographic and security module contains cryptographic and security elements which utilize the secret key for cryptographic and security operations. In the embodiment depicted in
The cryptographic and security module of
This invention produces the secret key within the cryptographic and security module ensuring that the secret key is never visible outside of this module and thus, is never compromised. Once realized, this cryptographically random secret root of trust can be used secretly within the disc drive system to support additional security functions in support of a secure disc drive and a secure computing system. These functions can include, but, are not limited to: secure bootstrapping of the disc drive and computer system, secure bootstrapping of keys and initial values, secure accounting of time across power cycles, and other secure functions. Each data storage system can have its own unique identifier or key that is permanently stored in the system.
In addition to the disclosed examples, it should be recognized that the electronic device and method of producing a key of this invention can be utilized in a plurality of electronic devices and systems that require the generation of a cryptographic key or other stable data word. This invention facilitates the generation of a cryptographic key or data word without the need to program a key generator.
While the invention has been described in terms of several examples, it will be apparent to those skilled in the art that various changes can be made to the disclosed examples without departing from the scope of the invention as set forth in the following claims.
