The invention provides an apparatus and a method for generating chopper-stabilized signals, wherein the problem of the offset voltage may be solved by making an OP amplifier be switched between a first chopper-stabilized mode and a second chopper-stabilized mode according to a voltage polarity control signal provided from a TFT LCD and without according to a start control signal.
A liquid crystal molecule in the TFT LCD cannot be always held on a certain voltage, or otherwise the molecule cannot be rotated to form different gray-scale levels in response to the electric field variation due to the damage to the property thereof. So, the voltage of the molecule has to be recovered every period of time in order to prevent the property of the liquid crystal molecule from being damaged. The display voltage in the TFT LCD may have two polarities including a positive polarity (P) and a negative polarity (N).
A timing controller of the TFT LCD generates a voltage polarity control signal (POL), having many pulses, for controlling the display voltage. In addition, the voltage polarity inversion of the voltage polarity control signal may be a two-line inversion or a one-line inversion.
In step 408, when the voltage transformation manner of the voltage polarity inversion of the voltage polarity control signal is the one-line inversion, the sampling signal is judged as a first sequence signal or a second sequence signal, and the numbers of the first sequence signals and the second sequence signals are counted. Thereafter, in step 410, when one of the numbers of the first sequence signals and the second sequence signals is first counted to 3, the sequence signal is temporarily stored as a frame transformation signal template. When the sampling signal is the same as the frame transformation signal template, a frame transformation signal is generated, and a first chopper-stabilized signal is generated in conjunction with the frame transformation signal and the voltage polarity control signal. The first chopper-stabilized signal makes the OP amplifiers of the TFT LCD be properly and alternately switched between the first chopper-stabilized mode chopper-A and the second chopper-stabilized mode chopper-B so that the offset voltage is eliminated.
In step 412, when the voltage transformation manner of the voltage polarity inversion of the voltage polarity control signal is the two-line inversion, the sampling signal is judged as a third sequence signal or a fourth sequence signal and the numbers of the third sequence signals and the fourth sequence signals are counted. Thereafter, in step 414, when one of the numbers of the third sequence signals and the fourth sequence signals is first counted to 3, this sequence signal is temporarily stored as the frame transformation signal template. When the sampling signal is the same as the frame transformation signal template, the frame transformation signal is generated, and the first chopper-stabilized signal is generated according to the frame transformation signal and the voltage polarity control signal. The first chopper-stabilized signal makes the OP amplifiers of the TFT LCD be properly and alternately switched between the first chopper-stabilized mode chopper-A and the second chopper-stabilized mode chopper-B so that the offset voltage is eliminated.
After a predetermined period of time has elapsed, step 416 is entered. If the frame transformation signal template cannot be obtained, a second chopper-stabilized signal is generated according to the voltage polarity control signal. The second chopper-stabilized signal makes the OP amplifiers of the TFT LCD be properly and alternately switched between the first chopper-stabilized mode chopper-A and the second chopper-stabilized mode chopper-B so that the offset voltage is eliminated.
The inversion checking device 612 judges whether the voltage inversion of the voltage polarity control signal POL is the one-line inversion or the two-line inversion according to the sampling signal SS. When the control unit 620 cannot obtain a frame transformation signal template FI according to the voltage transformation manner of the voltage polarity inversion of the voltage polarity control signal POL and the sampling signal SS, the rule checking device 613 enables the control unit 620 to output a second trigger signal T2, and the signal generating unit 630 generates the second chopper-stabilized signal CHOP2 with a specific order according to the second trigger signal T2 in conjunction with the voltage polarity control signal POL.
The control unit 620 includes a control circuit 621 and a count circuit 624. The control circuit 621 outputs a first trigger signal T1 or the second trigger signal T2 to the signal generating unit 630. The count circuit 624 outputs the frame transformation signal template FI according to the voltage transformation manner of the voltage polarity inversion of the voltage polarity control signal POL and the sampling signal SS. The control circuit 621 includes a central controller 622 and a watchdog 623. The central controller 622 outputs the first trigger signal T1 or the second trigger signal T2 so that the signal generating unit 630 correspondingly generates the first chopper-stabilized signal CHOP1 or the second chopper-stabilized signal CHOP2.
In addition, if the count circuit 624 cannot obtain the frame transformation signal template FI after m frame time periods, wherein m is a positive integer greater than or equal to 20, the watchdog 623 enables the central controller 622 to output the second trigger signal T2, and the signal generating unit 630 generates the second chopper-stabilized signal CHOP2 with the specific order according to the second trigger signal T2 in conjunction with the voltage polarity control signal POL.
The count circuit 624 includes a first register 626, a second register 627, a logic circuit 625, a counter 628 and a sequence register 629. When the voltage transformation manner of the voltage polarity inversion of the voltage polarity control signal POL is the one-line inversion, the logic circuit 625 judges whether the sampling signal SS is a first sequence signal S1 or a second sequence signal S2. The first sequence signal and the second sequence signal are defined as any two combinations exclusive of PNPNPNPN or NPNPNPNP. If the sampling signal SS is the first sequence signal S1, the sampling signal SS is stored to the first register 626. If the sampling signal SS is the second sequence signal S2, the sampling signal SS is stored to the second, register 627. When the voltage transformation manner of the voltage polarity inversion of the voltage polarity control signal POL is the two-line inversion, the logic circuit 625 judges whether the sampling signal SS is a third sequence signal S3 or a fourth sequence signal S4, wherein the third sequence signal and the fourth sequence signal are defined as any two combinations exclusive of PPNNPPNN or PNNPPNNP or NNPPNNPP or NPPNNPPN. If the sampling signal SS is the third sequence signal S3, the sampling signal SS is stored to the first register 626. If the sampling signal SS is the fourth sequence signal S4, the sampling signal SS is stored to the second register 627.
The counter 628 counts the numbers of the first sequence signals S1 and the second sequence signals S2, or the numbers of the third sequence signals S3 and the fourth sequence signals S4. When one of the numbers of the first sequence signals S1 and the second sequence signals S2 is first counted to 3, or one of the numbers of the third sequence signals S3 and the fourth sequence signals S4 is first counted to 3, the sequence register 629 stores the corresponding sequence signal as the frame transformation signal template FI, and outputs the frame transformation signal template to the signal generating unit 630.
The signal generating unit 630 includes a first logic circuit 631, a second logic circuit 632 and a multiplexer 633. The first logic circuit 631 receives the first trigger signal T1 from the central controller 622, and compares the frame transformation signal template FI with the sampling signal SS. When the frame transformation signal template FI is the same as the sampling signal SS, a frame transformation signal is generated. The first logic circuit 631 generates the first chopper-stabilized signal CHOP1 according to the frame transformation signal and the voltage polarity control signal POL. The second logic circuit 632 receives the second trigger signal T2 from the central controller 622 and generates the second chopper-stabilized signal CHOP2 with a specific order. An exchanged order, which is obtained after the front half portion of the specific order and the rear half portion of the specific order are exchanged, is reverse to the specific order. The multiplexer 633 is coupled to the first logic circuit 631 and the second logic circuit 632, and is controlled by the central controller 622 to select one of the first chopper-stabilized signal CHOP1 or the second chopper-stabilized signal CHOP2 as the chopper-stabilized signal CHOP to be outputted to the OP amplifier.
According to the apparatus and the method for generating the chopper-stabilized signals, the problem of the offset voltage may be solved and the uniformity can be enhanced by making the OP amplifier be switched between the first chopper-stabilized mode and the second chopper-stabilized mode according to the voltage polarity control signal provided from the TFT LCD and without according to the start control signal.
While the invention has been described by way of example and in terms of a preferred embodiment, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.
Number | Date | Country | Kind |
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095137213 | Oct 2006 | TW | national |