Patent Application
20230090726
The application relates to an apparatus and a method for hardware-based true random number and sequence of numbers generation and, in particular, to an apparatus for hardware-based random number generators (RNG) and its operation, in particular, to an apparatus for hardware-based random number generators (RNG) with electroforming-free memristors. Furthermore, the application relates, in particular, to the setup of the electronic circuit and a method for operating the RNG as a true random number generator (TRNG) and as a sequence of numbers generator (SNG).
Advances in energy- and cost-efficient computing and wireless connectivity have led to the Internet of Things (IoT). The IoT is a major drive for scientific, technological, economic, and social progress, and 50.1 billion IoT devices are expected to be in use by 2020, see [1].
Stochastic computing (SC) with a stochastic number generator (SNG) is a computing paradigm which offers extremely compact, energy-efficient and fault-tolerant realizations of certain functions at the cost of lower precision and longer computation time. These unconventional features make it an interesting choice for IoT applications such as area monitoring or environmental monitoring.
TRNGs rely on intrinsic stochasticity in physical variables of the system. It has been shown that TRNGs can be implemented electronically based on silicon CMOS technology. A large number of TRNGs are suitable for manufacturing on an ASIC silicon process or for an implementation on reconfigurable logic platforms, e.g., FPGA (field programmable gate array) or CPLD (complex programmable logic device). The entropy sources of such designs are, for example, thermal noise due to oscillator jitter [2], resistor amplifier analog-to-digital converter chains (see [3]), or metastable elements with capacitive feedback (see [4]).
The first memristive TRNG was proposed in 2010, see [5]. The read instability in many memristive devices due to random telegraph noise (RTN) can be used as a source of entropy for TRNG, e.g., RTN from the LRS of a W/TiN/TiON/SiO2/Si memristor [6]. These circuits are difficult to activate and control because the applied voltages strongly depend on the probabilities “0” and “1”. Recently, it was also proved that RTN is randomly activated or deactivated without predictability (see [7]).
Balatti et al. proposed a TRNG which is based on the cycle-to-cycle and device-to-device voltage variations of Cu/AlOx- and Ti/HfOx-based memristors (see [8], [9]). This memristor-based TRNG also entails careful tuning of the applied voltage/current flow to realize a predetermined probability distribution. In addition, an SET-RESET pulse pair is always used to generate each random bit since the memory elements are non-volatile. In addition, none of the TRNGs mentioned before can pass all the standard statistical test packages developed by the National Institute of Standards and Technology (NIST 800-22 Test Suite) (see [10]), even if the data is post-processed.
Wei et al. have realized a TRNG with random numbers from small read current variations at certain resistance states in TaOx-based memristors [11]. Again, complicated algorithms and circuitry are used to ensure the stochasticity of the generated binary bits before they can pass the NIST tests.
Stochastic computing (SC) has been considered to be a promising alternative to conventional deterministic computing. SC processes data in a probabilistic approach and handles computational uncertainties more effectively and efficiently (see [12]) with high fault tolerance, which meets the key requirement for future nanotechnology. According to the working principle of SC, the degree of accuracy of SC is subject to the randomness of stochastic bit streams. For this purpose, a sequence of numbers generator (SNG) with a controlled adjustable probability of 0/1 bit streams is used. In conventional CMOS approaches, a silicon technology-based stochastic number generator (SNG) is used to generate 0/1 bit streams of predetermined probability. These SNGs account for a large part of the resource consumption in SC with costs of up to 80% of the entire system from [12].
According to an embodiment, an apparatus for generating a sequence of random numbers may have: a switchable element switchable to a first state by applying a first bias voltage, and switchable to a second state by applying a second bias voltage different from the first bias voltage; wherein the switchable element is configured, when switched to the first state by the first bias voltage, to output a first output voltage having a first random or pseudorandom voltage value from a first range of voltage values and wherein the switchable element is configured, when switched to the second state by the second bias voltage, to output a second output voltage having a second random or pseudorandom voltage value from a second range of voltage values; and a comparator configured to output, if the first output voltage from the first range of values is smaller than or equal to a first threshold voltage, a first numerical value; and output, if the first output voltage from the first range of values is greater than the first threshold voltage, a second numerical value different from the first numerical value; wherein the comparator is configured, if the second output voltage from the second range of value is smaller than or equal to a second threshold voltage, to output the first numerical value, and if the second output voltage from the second range of values is greater than the second threshold voltage, to output the second numerical value; or if the second output voltage from the second range of values is smaller than or equal to a second threshold voltage, to output the second numerical value, and if the second output voltage from the second range of values is greater than the second threshold voltage, to output the first numerical value.
According to another embodiment, a method for generating a sequence of random numbers may have the steps of: applying a first bias voltage to a switchable element to switch the switchable element to a first state, or applying a second bias voltage, different from the first bias voltage, to the switchable element to switch the switchable element to a second state; wherein the switchable element is configured, when switched to the first state by the first bias voltage, to output a first output voltage having a first random or pseudorandom voltage value from a first range of voltage values; and wherein the switchable element is configured, when switched to the second state by the second bias voltage, to output a second output voltage having a second random or pseudorandom voltage value from a second range of voltage values; and outputting a first numerical value if the first output voltage from the first range of values is smaller than or equal to a first threshold voltage; or outputting a second numerical value, different from the first numerical value, if the first output voltage from the first range of values is greater than the first threshold voltage; or outputting the second numerical value if the first output voltage from the first range of values is smaller than or equal to a first threshold voltage; or outputting the first numerical value if the first output voltage from the first range of values is greater than the first threshold voltage.
Another embodiment may have a non-transitory digital storage medium having stored thereon a computer program for performing a method for generating a sequence of random numbers, the method having the steps of: applying a first bias voltage to a switchable element to switch the switchable element to a first state, or applying a second bias voltage, different from the first bias voltage, to the switchable element to switch the switchable element to a second state; wherein the switchable element is configured, when switched to the first state by the first bias voltage, to output a first output voltage having a first random or pseudorandom voltage value from a first range of voltage values; and wherein the switchable element is configured, when switched to the second state by the second bias voltage, to output a second output voltage having a second random or pseudorandom voltage value from a second range of voltage values; and outputting a first numerical value if the first output voltage from the first range of values is smaller than or equal to a first threshold voltage; or outputting a second numerical value, different from the first numerical value, if the first output voltage from the first range of values is greater than the first threshold voltage; or outputting the second numerical value if the first output voltage from the first range of values is smaller than or equal to a first threshold voltage; or outputting the first numerical value if the first output voltage from the first range of values is greater than the first threshold voltage, when said computer program is run by a computer
An apparatus for generating a sequence of random numbers according to an embodiment is provided. The apparatus comprises a switchable element switchable to a first state by applying a first bias voltage, and switchable to a second state by applying a second bias voltage different from the first bias voltage. The switchable element is configured, when switched to the first state by the first bias voltage, to output a first output voltage having a first random or pseudorandom voltage value from a first range of voltage values. Furthermore, when switched to the second state by the second bias voltage, the switchable element is configured to output a second output voltage having a second random or pseudorandom voltage value from a second range of voltage values. Furthermore, the apparatus comprises a comparator configured to output, if the first output voltage from the first range of values is smaller than or equal to a first threshold voltage, a first numerical value; and to output, if the first output voltage from the first range of values is greater than the first threshold voltage, a second numerical value different from the first numerical value. Additionally, if the second output voltage from the second range of values is smaller than or equal to a second threshold voltage, the comparator is configured to output the first numerical value, and if the second output voltage from the second range of values is greater than the second threshold voltage, to output the second numerical value. Or else the comparator is configured to output the second numerical value if the second output voltage from the second range of values is smaller than or equal to a second threshold voltage, and to output the first numerical value if the second output voltage from the second range of values is greater than the second threshold voltage.
Furthermore, a method for generating a sequence of random numbers according to an embodiment is provided. The method comprises:
Furthermore, a computer program having program code for performing the above-described method according to an embodiment is provided.
Embodiments of the invention will be described below with reference to the drawings, in which:
The apparatus includes a switchable element 110 switchable to a first state by applying a first bias voltage, and switchable to a second state by applying a second bias voltage different from the first bias voltage.
The switchable element 110 is configured, when switched to the first state by the first bias voltage, to output a first output voltage having a first random or pseudorandom voltage value from a first range of voltage values.
Furthermore, when switched to the second state by the second bias voltage, the switchable element 110 is configured to output a second output voltage having a second random or pseudorandom voltage value from a second range of voltage values.
Additionally, the apparatus comprises a comparator 120 configured to output a first numerical value, if the first output voltage from the first range of values is smaller than or equal to a first threshold voltage; and if the first output voltage from the first range of values is greater than the first threshold voltage, a second numerical value different from the first numerical value.
Furthermore, if the second output voltage from the second range of values is smaller than or equal to a second threshold voltage, the comparator 120 is configured to output the first numerical value, and if the second output voltage from the second range of values is greater than the second threshold voltage, the comparator 120 is configured to output the second numerical value.
Or else the comparator 120 is configured to output the second numerical value if the second output voltage from the second range of values is smaller than or equal to a second threshold voltage, and to output the first numerical value if the second output voltage from the second range of values is greater than the second threshold voltage.
According to an embodiment, the comparator 120 may be configured, for example, to output the first numerical value or the second numerical value as a first output value in a first output step. Thus, the apparatus may, for example, be configured to apply either the first bias voltage or the second bias voltage to the switchable element 110 depending on whether the comparator 120 outputs the first numerical value or the second numerical value. Thus, the switchable element 110 may be configured, for example, to output a further output voltage having a random or pseudo-random voltage value, depending on whether the first bias voltage or the second bias voltage has been applied, from the first range of voltage values or from the second range of voltage values. Furthermore, the comparator 120 may be configured to output, for example, as a second output value, in a second output step, the first numerical value or the second numerical value depending on the further output voltage.
In one embodiment, the apparatus may further comprise, for example, a multiplexer which may be configured to apply either the first bias voltage or the second bias voltage to the switchable element 110 depending on whether the comparator 120 outputs the first numerical value or the second numerical value.
According to an embodiment, the switchable element 110 may be, for example, a memristor.
In one embodiment, the switchable element 110 may comprise, for example, yttrium manganese oxide.
According to an embodiment, the switchable element 110 may comprise, for example, bismuth ferrite and/or, for example, bismuth ferrite doped with titanium.
In one embodiment, for example, a largest absolute value of the first range of voltage values may be at least twice as large as a largest absolute value of the second range of voltage values, or the largest absolute value of the second range of voltage values may be at least twice as large as the largest absolute value of the first range of voltage values, for example.
According to an embodiment, the largest absolute value of the first range of voltage values may be, for example, at least four times as large as the largest absolute value of the second range of voltage values, or the largest absolute value of the second range of voltage values may be, for example, at least four times as large as the largest absolute value of the first range of voltage values.
In one embodiment, the second threshold voltage may be different from the first threshold voltage, for example.
According to an embodiment, the first threshold voltage may be defined, for example, such that a statistical probability that the first output voltage having the first random or pseudorandom voltage value is greater than the first threshold voltage has a value between 45% and 55%, and/or the second threshold voltage may be defined, for example, such that a statistical probability that the second output voltage having the second random or pseudorandom voltage value is greater than the second threshold voltage has a value between 45% and 55%.
In one embodiment, the first threshold voltage may be set such that, for example, the statistical probability that the first output voltage having the first random or pseudorandom voltage value is greater than the first threshold voltage is 50%, and/or the second threshold voltage may be set such that, for example, the statistical probability that the second output voltage having the second random or pseudorandom voltage value is greater than the first threshold voltage is 50%.
According to an embodiment, the sequence of random numbers may be, for example, a binary sequence of random numbers. Here, for example, an output of the first numerical value or the second numerical value by the comparator 120 may correspond to exactly one random number of the binary sequence of random numbers.
For example, in one embodiment, the sequence of random numbers is not a binary sequence of random numbers. Here, the apparatus may be configured, for example, to form a random number of the sequence of random numbers using several numerical values output by the comparator 120.
According to an embodiment, the apparatus may be configured, for example, to form said random number of the sequence of random numbers using said several numerical values output by the comparator 120 by having each of said several numerical values form exactly one binary digit of said random number of the sequence of random numbers in binary notation.
In one embodiment, for example, the apparatus may include a current conformity unit which applies a predefined input current to the switchable element 110 when the first bias voltage is applied.
According to an embodiment, the apparatus may have, for example, two or more memristors.
In one embodiment, the plurality of memristors may be arranged in series, for example, and/or the plurality of memristors may be arranged in parallel in a line array, for example, and/or the plurality of memristors may be arranged in a crossbar array, for example.
According to an embodiment, the switchable element 110 may be, for example, a first switchable element 110 and the comparator 120 may be, for example, a first comparator. Thus, the apparatus may further comprise, for example, a further switchable element 110 and, for example, a further comparator to generate random numbers of the sequence of random numbers.
The actual polarity and amplitude of the applied write bias voltage are determined by the potential of the upper electrode (T1) and the lower electrode (T2) of the resistive switch. For example, the upper electrode (T1) can be considered to be a reference for the bias voltage applied to the device. If the potential of the upper electrode is higher than that of the lower electrode, this can be considered to be a positive voltage applied to the device. Otherwise, if the potential of the lower electrode is higher, this can be considered to be a negative voltage applied to the device.
It should be noted that if the upper electrode and the lower electrode have the same potential, there is no potential difference at the device, i.e. no actual voltage would be present at the device.
Embodiments provide one or more switchable elements, e.g., one or more memristive devices (one or more memristors), for random number generators (RNG). In embodiments, the operation of such memristive devices is realized as a true random number generator (TRNG) and as a sequence of numbers generator (SNG).
In embodiments, a switchable element, e.g., a memristive device (a memristor), is provided in a single cell, line, or array design in which the current-voltage (IV) characteristic of each cell varies randomly. According to an embodiment, the distribution of responses (output), for example of a read current, when “challenges” (input) of a read voltage are queried, for example, may be distributed in a box-like manner around a probability threshold value, which may be specific to each cell of the memristive device in single cell, line or array design.
In some embodiments, the probability of the 0/1 bit stream may be determined by a probability threshold value, for example. If the probability of the 0/1 bit stream is 50%:50%, the RNG may be used as a TRNG, for example for key exchange. With a random choice of the probability of the 0/1 bit stream, the RNG can be used as an SNG, for example for stochastic computing.
In some embodiments, providing random bit streams using memristive devices with strict hardware and power constraints can be used for efficient key exchange and for efficiently computing data-intensive problems. The use of a memristive device to build TRNGs and SNGs based on an electroforming-free memristor provides an efficient design which significantly reduces the relative costs.
Reliable operation of the RNG under extreme temperatures can be ensured, for example, by comparably changing the IV characteristics of all the cells of the memristive device in single cell, line, or array designs.
In particular,
For example, in
In the exemplary YMO-based memristive device of
In one embodiment, for example, current compliance (CC) is used during the switching process to prevent permanent failure of the device.
Successive switching cycles of a single cell of a YMO-based memristive device (
Memristive devices with a random variation of IV characteristics can be used to realize RNGs.
Statistical results in the memristive YMO device show that the randomness of the distribution of the SET and RESET switching voltages in both positive and negative bias directions can be used to generate 0/1 bit streams.
In
For example,
Further specific embodiments are described below.
In a particular embodiment, a single cell of a YMO-based memristive device is provided for realizing a TRNG. The SET and RESET distortions with a cumulative probability of 50% are selected as source distortions in the block design of TRNG as VSET and VRESET for receiving the Hamming distance between the classes of 50%.
In one embodiment, operation of YMO-based memristive devices may be provided as TRNG and SNG. For example, both stochastic and secure properties may be used for a TRNG. For example, an excellent autocorrelation for maintaining secrecy results. Due to the purely stochastic distribution of switching devices in YMO membrane cells during SET and RESET processes, the YMO membrane cell is provided as a random source for the TRNG design, for example.
In embodiments, the setup of
A SET bias voltage VSET of fixed width is applied to a YMO memristor cell 110 and to a series resistor Rs.
When under the applied (bias) voltage the YMO memristor cell 110 is turned on and thus the output voltage across the series resistor Rs is Icc·Rs, which is higher than the well-defined reference voltage of the comparator 120 Vref, the output voltage of the comparator goes to the high logic level, therefore the output of the comparator 120 is “logic-1”.
Icc is the matching level current of the YMO device. For the reference voltage Vref of the comparator 120, Vref=Icc·RS-VOFFSET. VOFFSET has a small constant value, e.g. 0.001 V, which is not related to the dynamics of YMO cells.
In the next switching cycle, VRESET corresponding to feedback “1” from the output of comparator 120 in the previous cycle is selected by the multiplexer 130 and applied to the YMO memristor cell 110 to reset the cell to HRS. Thus, the voltages VRs in HRS are lower than Vref. The output of comparator 120 in this case is “logic-0”.
In one embodiment, to achieve uniformity (50% probability of LRS/HRS), the pulse width and amplitude of the SET/RESET processes are set based on a statistical examination.
Compared to existing memristor-based TRNGs, advantages of the exemplary apparatus of
First, no additional SET/RESET bias voltage is required to generate a random bit. In previous devices, a pair of SET and RESET pulses was used to generate each random bit due to the non-volatility of a memristive device based on Cu/AlOx and Ti/HfOx (see [15], [16]). Such a disadvantage results in a low bit rate of TRNGs. The exemplary apparatus of
Second, no additional read bias voltage is required during the process. The random bits are generated based on the comparison between the voltage across Rs (VRs=IM·Rs) and the reference voltage (Vref=Icc·Rs-V0).
Third, the definition of the reference voltage can be kept constant. In the proposed YMO-based TRNG, the definition of Vref is not related to the switching bias voltage of YMO cells. It is clearly defined to be Vref=Icc·Rs-V0, which is convenient for the large-scale design of TRNG.
CMOS-based stochastic circuits consist of SNG conversion sources and arithmetic logic gates. SNGs are essential components for memristive implementations of SC circuits. The high resource consumption of conventional SNGs developed in CMOS technology is reduced, for example, by the exemplary apparatus of
As is shown in
Further embodiments of the invention are described below.
In one embodiment, for example, a Sequence Number Generator (SNG) implementation having a single, electroforming-free, unipolar memristor without an electroforming step can be realized.
According to an embodiment, for example, the memristor may have a stochastic current-voltage characteristic, that is the read current Ir may be randomly below or above a threshold value for a given write voltage Uw, write pulse length tw, and read voltage Ur, for example.
For example, in one embodiment, the memristor can show the stochastic current-voltage characteristic, such as for positive write voltages, for negative write voltages, for write voltages which place the memristor in the high resistance state (HRS) (Ur=URESET), and for write voltages which place the memristor in the low resistance state (LRS) (Ur=USET).
According to an embodiment, for example, the reference value for the memristor may be fixed.
For example, in one embodiment, the write pulse length tp may determine the probability of the sequence number generator (SNG) as a function of the write voltage, (negative, positive, URESET, USET).
According to an embodiment, for example, the write pulse length may be internally randomly selected, and thus, for example, the probability of the sequence number generator may be randomly selected.
For example, in one embodiment, a realization of several (N) sequence number generators (SNGs) with several (N) electroforming-free unipolar memristors can be performed without an electroforming step.
According to an embodiment, for example, the (N) memristors of the (N) sequence number generators (SNG) may be implemented with a common unstructured or a structured back-side electrode and may be arranged in series or in series and/or in parallel in a line array or in a crossbar array.
In one embodiment, for example, each of the N memristors may have a stochastic current-voltage characteristic, wherein, for example, the read current Ir may be randomly below or above a threshold value for a given write voltage Uw, write pulse length tw and read voltage Ur.
According to an embodiment, for example, each of the N memristors can show the stochastic current-voltage characteristic, for example, for positive write voltages, for negative write voltages, for write voltages which put the memristor in the high resistance state (HRS) (Ur=URESET), and for write voltages which put the memristor in the low resistance state (LRS) (Ur=USET).
In one embodiment, for example, (N) reference values may be set for each of the (N) memristors.
According to an embodiment, for example, the write pulse length tp of each of the (N) memristors may determine the probability of the sequence number generator (SNG) of each of the (N) memristors as a function of the write voltage Uw (negative, positive, URESET, USET).
For example, in one embodiment, the write pulse length tp of each of the (N) memristors may be internally randomly selected, wherein the probability of the sequence number generator of each of the (N) memristors can be randomly selected.
Key exchange can be shown as an application example, for example. For example, a true random number generator with a threshold value of 50:50 can be used for this.
Stochastic computing with a sequence number generator can be provided as a further application example, for example.
Although some aspects have been described in the context of an apparatus, it is understood that these aspects also represent a description of the corresponding method so that a block or component of an apparatus is also to be understood to be a corresponding method step or feature of a method step. Similarly, aspects described in connection with or as a method step also constitute a description of a corresponding block or detail or feature of a corresponding apparatus. Some or all of the method steps may be performed by (or using) a hardware apparatus, such as a microprocessor, a programmable computer, or an electronic circuit. In some embodiments, some or several of the most important method steps may be performed by such an apparatus.
Depending on particular implementation requirements, embodiments of the invention may be implemented in hardware or in software, or at least partially in hardware or at least partially in software. The implementation may be performed using a digital storage medium, for example, a floppy disk, a DVD, a BluRay disc, a CD, ROM, PROM, EPROM, EEPROM, or a FLASH memory, a hard disk drive, or any other magnetic or optical storage on which electronically readable control signals are stored which can or do cooperate with a programmable computer system such that the respective method will be performed. Therefore, the digital storage medium may be computer-readable.
Thus, some embodiments according to the invention include a data carrier having electronically readable control signals capable of cooperating with a programmable computer system such that any of the methods described herein will be performed.
Generally, embodiments of the present invention may be implemented as a computer program product having program code, the program code operative to perform any of the methods when the computer program product runs on a computer.
For example, the program code may also be stored on a machine-readable medium.
Other embodiments comprise the computer program for performing any of the methods described herein, wherein the computer program is stored on a machine-readable medium. In other words, an embodiment of the method according to the invention is thus a computer program comprising program code for performing any of the methods described herein when the computer program runs on a computer.
Thus, a further embodiment of the methods of the invention is a data carrier (or digital storage medium or computer-readable medium) having recorded thereon the computer program for performing any of the methods described. The data carrier or digital storage medium or computer-readable medium is typically tangible and/or non-volatile.
Thus, a further embodiment of the method according to the invention is a data stream or sequence of signals representing the computer program for performing any of the methods described herein. The data stream or sequence of signals may, for example, be configured to be transferred via a data communication link, for example via the Internet.
Another embodiment comprises processing means, such as a computer or programmable logic device, configured or adapted to perform any of the methods described herein.
Another embodiment includes a computer having installed thereon the computer program for performing any of the methods described herein.
Another embodiment according to the invention comprises an apparatus or system configured to transmit a computer program for performing at least one of the methods described herein to a receiver. The transmission may be, for example, electronic or optical. The receiver may be, for example, a computer, mobile device, storage device, or similar device. The apparatus or system may include, for example, a file server for transmitting the computer program to the receiver.
In some embodiments, a programmable logic device (for example, a field programmable gate array, FPGA) may be used to perform some or all of the functionalities of the methods described herein. In some embodiments, a field programmable gate array may cooperate with a microprocessor to perform any of the methods described herein. Generally, in some embodiments, the methods are performed on the part of any hardware apparatus. This may be general-purpose hardware, such as a computer processor (CPU), or hardware specific to the method, such as an ASIC.
While this invention has been described in terms of several advantageous embodiments, there are alterations, permutations, and equivalents which fall within the scope of this invention. It should also be noted that there are many alternative ways of implementing the methods and compositions of the present invention. It is therefore intended that the following appended claims be interpreted as including all such alterations, permutations, and equivalents as fall within the true spirit and scope of the present invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 102020206790.2 | May 2020 | DE | national |
This application is a continuation of copending International Application No. PCT/EP2021/064222, filed May 27, 2021, which is incorporated herein by reference in its entirety, and additionally claims priority from German Application No. 102020206790.2, filed May 29, 2020, which is also incorporated herein by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/EP2021/064222 | May 2021 | US |
| Child | 18059530 | US |
