Disclosed embodiments relate generally to photovoltaic devices, and more particularly, to an apparatus for and a method of improving efficiency of thin-film photovoltaic devices.
Photovoltaic devices can include semiconductor material deposited over a substrate such as glass, for example, with a first layer of the semiconductor material serving as a window layer and a second layer of the semiconductor material serving as an absorber layer. The semiconductor window layer forms a junction with the semiconductor absorber layer where incident light is converted to electricity. During operation, light passes through the photovoltaic device and is absorbed by electrons at or near this junction. This produces photo-generated electron-hole pairs, where the electron acquires sufficient energy to “move” to an elevated state, leaving behind a hole. A built in electric field promotes the movement of these photo-generated electron-hole pairs, which produces electric current that can be output to other electrical devices.
One limiting factor on thin-film photovoltaic device efficiency is the reduced lifetime of the photo-generated electron hole pairs when they are in the semiconductor absorber layer. This is called reduced carrier lifetime. Carrier lifetime is calculated as the average time it takes electrons in an absorber layer to lose their excited energy by recombining with a paired hole. Recombination may also occur near structural defects such as grain boundaries in polycrystalline materials. To increase carrier lifetime in the absorber layer, it is desirable to increase absorber layer grain size, the average size of merged semiconductor particles in a semiconductor layer. Increasing absorber layer grain size occurs through grain growth (the merging of these semiconductor particles within the semiconductor layer). The greater the grain size of the semiconductor particles, the more difficult it is for excited electrons associated with the particles to lose their excited energy by recombination or the longer the carrier lifetime of the semiconductor particles. Increased carrier lifetime of semiconductor particles in the semiconductor layer increases photovoltaic device efficiency because the fewer excited electron-hole pairs will be lost in an undesirable recombination event.
In order to improve the efficiency of thin-film photovoltaic devices, the semiconductor absorber layer is often subjected to a cadmium chloride heat-treatment to promote grain growth. Cadmium chloride heat-treatments include applying a cadmium chloride compound to an exposed surface of a deposited semiconductor absorber layer and then heating the layer. The heat helps the cadmium chloride diffuse into the semiconductor absorber layer where it interacts with the semiconductor particle promoting their merger into larger particle, which is absorber layer grain growth. However, this treatment only promotes absorber layer grain growth of 1 to 2 um, providing only a limited improvement of carrier lifetime in the absorber layer. After the completion of the heat-treatment, a surface cleaning step may be performed to remove residue of the halide coating and byproducts of the annealing process such as oxide phases formed from the semiconductor material or the halide material.
Accordingly, a method and apparatus for producing an absorber layer grain growth of more than 2 um as well as improving the interface between the semiconductor absorber layer and the semiconductor window layer when the semiconductor window layer has been thinned out enough to reduce optical loss are desirable.
In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and which illustrate specific embodiments of the invention. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to make and use them. It is also understood that structural, logical, or procedural changes may be made to the specific embodiments disclosed herein without departing from the spirit or scope of the invention.
A method for producing semiconductor thin-film layers in a photovoltaic device is provided. The method includes depositing a thin-film semiconductor window layer and a thin-film semiconductor absorber layer or multiple semiconductor absorber layers over a substrate, then applying a halide heat treatment. The halide heat treatment includes applying a first coating of a halide compound on at least one surface of the semiconductor absorber layer or layers, heat-treating the surface to activate the halide compound applied thereon, providing at least a second coating of the halide compound on the at least one surface and heat-treating the surface once more. The second heat-treatment may occur under the same or different ambient conditions than the first heat-treatment. For example, the temperature used in the second heat-treatment may differ from that of the first heat-treatment and/or ambient atmospheric conditions under which the first treatment occurred may differ from those of the second heat-treatment.
In accordance with the provided method, the halide compound that diffuses into the absorber layer chemically interacts with the crystalline structure of the layer. The repetition of this interaction during the multiple halide applications and heatings facilitates better combination and recrystallization of the molecules of the semiconductor absorber material than when the halide compound is not present or only applied in a single application.
As shown in
Further, semiconductor layers may be deposited on the TCO stack 170. The semiconductor layers may include a semiconductor window layer 150, which may be made of cadmium sulfide, and a semiconductor absorber layer 160 made of cadmium telluride. Both the semiconductor window layer 150 and semiconductor absorber layer 160 can be deposited using any known deposition technique, including vapor transport deposition (VTD).
In
The heatings of the halide coated surface 165 after each halide coatings may be performed at temperatures, for example, temperatures T1 after applying the first halide coating and T2 after applying the second halide coating, in the range of about 350° C. to about 600° C. for durations of time, for example D1 after the first halide coating and D2 after the second halide coating, in the range of about 1 minute to about 60 minutes. In various embodiments, temperature T1 may be less than temperature T2, temperature T1 may be greater than temperature T2, or temperature T1 may be equal to temperature T2. Similarly, duration D1 may be equal to duration D2, duration D1 may be less than duration D2, or duration D1 may be greater than duration D2. For example, after the first coating of the halide compound is applied to the desired surface adjacent to or part of the semiconductor layers, the surface may be heated to a first temperature of about 450° C. for a duration of about 10 minutes. Then, after the second coating of the halide compound is applied to the same surface, the surface may be heated again to a second temperature of about 420° C. for a duration of about 10 minutes. In another embodiment, after the first coating of the halide compound is applied to the desired surface adjacent to or part of the semiconductor layers, the surface may be heated to a first temperature of about 450° C. for a duration of about 10 minutes. Then, after the second coating of the halide compound is applied to the same surface, the surface may be heated again to a second temperature of about 500° C. for a duration of about 30 minutes.
Heating the halide coatings at lower temperatures promotes incorporation of the halide into the semiconductor layer while heating the halide treatments at higher temperature drives the formation of the crystalline structure, increasing grain growth. So, heating the halide coatings first at a lower temperature and then second at a higher temperature, for example, where temperature T1 may be less than temperature T2, will first promote incorporation of the halide into the semiconductor layer and then drive the formation of the crystalline structure in the presence of the halide to increase grain growth. Alternatively, heating the halide coatings first at a higher temperature and then second at a lower temperature, for example, where temperature T1 may be greater than temperature T2, will first drive the formation of the crystalline structure in the presence of the halide and then promote incorporation of optimum levels of halide in the newly formed crystalline structure. Heating the halide coatings multiple times at the same temperature can achieve both effects for longer durations of time without favoring the formation of the crystalline structure over incorporation of the halide compound into the layer.
The heatings of the halide coated surface 165 after each halide coating may be performed under various ambient atmospheric conditions. For example, the ambient atmosphere may include oxygen, or be oxygen depleted; it may contain sulfur or be sulfur free. An ambient atmosphere that includes oxygen promotes the interaction of the halide compound with the semiconductor layer. For an ambient atmosphere containing oxygen, oxygen may be supplied in the processing chamber.
In another embodiment, after application of the first or second halide coating a sulfur containing ambient may be created around the halide coated surface 165 by supplying a sulfur containing gas, for example, hydrogen sulfide, around the halide coated surface 165. A sulfur containing ambient is especially beneficial for the formation of cadmium telluride thin-film layers, as sulfur has been found to interact well with a halide and cadmium telluride to promote grain growth. For an ambient atmosphere containing sulfur, sulfur may be supplied in the processing chamber.
In another embodiment, after application of the first or second halide coating, an oxygen or sulfur depleted ambient may be created around the halide coated surface 165 by using a vacuum to remove all gas from around the halide coated surface 165 or by supplying an inert gas, for example, nitrogen gas, around the halide coated surface 165. The absence of oxygen or sulfur is beneficial in situations where another processing gas is necessary, for example a sulfur gas and the presence of oxygen would interfere with the function of the additional process gas. The absence of oxygen may also be beneficial in a halide diffusions step where no grain growth is intended because it can minimize oxidation of the halide coated surface 165.
The ambient conditions for the multiple post-application heatings may be the same or different. For example, in one embodiment, after application of the first halide coating, a first post-application heating may be performed in an oxygen containing ambient and after application of the second halide coating, a second post-application heating may be performed in an oxygen depleted ambient. In another embodiment, after application of the first halide coating, a first post-application heating may be performed in an oxygen depleted ambient and after application of the second halide coating, a second post-application heating may be performed in an oxygen containing ambient. In another embodiment, after application of the first halide coating a first post-application heating may be performed in a sulfur containing ambient and after application of the first or second halide coating, a second post-application heating may be performed in a sulfur depleted ambient. In another embodiment, after application of the first halide coating, a first post-application heating may be performed in a sulfur depleted ambient and after application of the second halide coating, a second post-application heating may be performed in a sulfur containing ambient.
In another embodiment, a single coating of a halide compound may be applied to multiple surfaces between multiple layers adjacent to or part of the semiconductor layers. For example, as shown in
In another embodiment, as shown in
In another exemplary embodiment, as shown in
In another embodiment, successive layers of the same semiconductor material may be deposited with halide coated surfaces in between each layer. The combined layers of the same semiconductor material form a combined semiconductor layer. For example, as shown in
The conveyor system 501 may transport the photovoltaic device 100 with the cadmium sulfide layer 150 and the cadmium telluride layer 160 as shown in
It should be noted that the treatment system 550 may be placed in sequence before or after other known fabrication systems responsible, for example, for depositing the thin film layers on the substrate 110 of the photovoltaic device 100 as shown in
Referring back to
Additionally, inert gas introduction ports 561, 562, 563, and corresponding exhaust ports 565, 566, 567, may be placed at the intersections between modules 506 and 507, modules 507 and 508, and modules 508 and 509 to produce inert gas curtains around the first and second heater modules 507 and 509. Inert gas introduction ports 561, 562, 563 will provide a flow of inert gas into the chamber 503 which will then be pulled out of the chamber 503 through corresponding exhaust ports 565, 566, 567 creating a flowing stream of inert gas between the modules 506, 507, 508, 509 which may maintain the ambient conditions within the heating modules 507, 509.
In alternative embodiments, the treatment system 550 may farther include a deposition module 510 and an additional halide application module 504 placed in sequence with the modules 506, 507, 508, 509 of the treatment system 550 to produce a photovoltaic device 100 as shown in
It should be noted that in alternative embodiments, where desired, the modules 504, 506, 507, 508, 509, 510 may be arranged in any desired sequence in the treatment system 550 to produce photovoltaic devices 100 as shown in
As shown in
The embodiments described above are offered by way of illustration and example. It should be understood that the examples provided above may be altered in certain respects and still remain within the scope of the claims. It should be appreciated that, while the invention has been described with reference to the above embodiments, other embodiments are within the scope of the claims.
This application is a continuation of U.S. patent application Ser. No. 13/899,153, filed May 21, 2013, which claims the benefit of priority of U.S. Provisional Patent Application No. 61/649,680, filed May 21, 2012, entitled: “Apparatus and Method for Improving Efficiency of Thin-Film Photovoltaic Devices” the entirety of which are incorporated by reference herein.
Number | Date | Country | |
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61649680 | May 2012 | US |
Number | Date | Country | |
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Parent | 13899153 | May 2013 | US |
Child | 15342533 | US |