Patent Application
20140259101
1. Field
The present invention relates generally to a secure thread inheriting a context of a non-secure thread.
2. Background
In the ARMv7 architecture, with security extensions implemented, non-secure environment OS threads invoke secure functionality (e.g. Trustzone™) through secure monitor calls directed to a secure environment. The secure environment creates a context for executing/processing a secure monitor call from the non-secure environment. Generally, the secure environment chooses to setup its execution context independent of the non-secure environment. This independent configuration for a secure thread may conflict with the configuration of a non-secure thread. For example, a separate setting of the interrupt state may exhibit undesirable effects, such as interrupt latency.
There is therefore a need for a technique for preventing undesirable effects caused by a configuration conflict between a non-secure thread and a secure thread.
An aspect of the present invention may reside in a method for inheriting a non- secure thread context. In the method, a first secure monitor call associated with a first non-secure thread of a non-secure environment of a processing system is received. A first secure thread is created, in response to the first secure monitor call, that inherits a first interrupt state of the first non-secure thread.
In more detailed aspects of the invention, the first interrupt state may comprise enable or disable, and may be inherited using a current program status register. The first secure thread may be in a secure environment of the processing system.
In other more detailed aspects of the invention, a second secure monitor call associated with a second non-secure thread may be received. A second secure thread may be created, in response to the second secure monitor call, that inherits a second interrupt state of the second non-secure thread. Further, a third secure monitor call associated with a third non-secure thread may be received. A third secure thread may be created, in response to the third secure monitor call, that inherits a third interrupt state of the third non-secure thread.
Another aspect of the invention may reside in an apparatus, comprising: means for receiving a first secure monitor call associated with a first non-secure thread of a non-secure environment; and means for creating a first secure thread, in response to the first secure monitor call, that inherits a first interrupt state of the first non-secure thread.
Another aspect of the invention may reside in an apparatus, comprising a processor configured to: receive a first secure monitor call associated with a first non-secure thread of a non-secure environment; and create a first secure thread, in response to the first secure monitor call, that inherits a first interrupt state of the first non-secure thread.
Another aspect of the invention may reside in a computer program product, comprising computer-readable medium, comprising: code for causing a computer to receive a first secure monitor call associated with a first non-secure thread of a non-secure environment; and code for causing a computer to create a first secure thread, in response to the first secure monitor call, that inherits a first interrupt state of the first non-secure thread.
The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.
With reference to
With further reference to
The inherited interrupt state for a secure thread (e.g., ST1) is the current interrupt state of a corresponding non-secure thread (e.g., NST1) at the time the secure monitor call is made. At a later time, the corresponding non-secure thread (e.g., NST1) may have a change in its interrupt state, and a secure monitor call made after that change would result in the inherited interrupt state being that of the changed (or then current) interrupt state of the non-secure thread at the time the later secure monitor call is made.
In other more detailed aspects of the invention, the first secure thread ST1 may be in a secure environment 320 of the processing system. Also, a second secure monitor call SMC2 associated with a second non-secure thread NST2 may be received. A second secure thread ST2 may be created, in response to the second secure monitor call, that inherits a second interrupt state of the second non-secure thread. Further, a third secure monitor call SMC3 associated with a third non-secure thread NST3 may be received. A third secure thread ST3 may be created, in response to the third secure monitor call, that inherits a third interrupt state of the third non-secure thread.
The inheritance of the interrupt state ensures that the interruptibility of an operation within the secure environment 320 is consistent with the thread interruptibility of the non-secure thread requesting the operation. This inheritance helps the non-secure environment 210 (or world) control the non-secure interrupt latency even when it requests services from the secure environment 220 (or world).
With further reference to
Another aspect of the invention may reside in an apparatus, comprising a processor 510 configured to: receive a first secure monitor call SMC1 associated with a first non-secure thread NST1 of a non-secure environment 310; and create a first secure thread ST1, in response to the first secure monitor call SMC1, that inherits a first interrupt state of the first non-secure thread NST1.
Another aspect of the invention may reside in a computer program product, comprising computer-readable medium 520, comprising: code for causing a computer 500 to receive a first secure monitor call SMC1 associated with a first non-secure thread NST1 of a non-secure environment 310; and code for causing a computer 500 to create a first secure thread ST1, in response to the first secure monitor call SMC1, that inherits a first interrupt state of the first non-secure thread NST1.
Other thread attributes may be inherited, such as thread priority and/or memory mapping, e.g., a mapping of input and/or output buffers shared between the secure environment and the non-secure environment. The inheritance of output buffer memory mapping attributes from the non-secure side may help the secure environment and the non-secure environment leverage the sharing of the cache lines, thereby eliminating the need of performing cache maintenance operation when information is exchanged. Security is not compromised as the information is outbound from the secure environment.
An apparatus or station may comprise a computer 500 that includes a processor 510, a storage medium 520 such as memory and/or a disk drive, a display 530, and an input such as a keypad 540, and a wireless connection 550. The processor and/or the storage medium may comprise the processing system that hosts the non-secure environment 310 and the secure environment 320. The processor may be implemented as a system-on-a-chip (SOC) in accordance with the ARMv7 architecture. An ARM-based processor is a RISC (Reduced Instruction Set Computing) processor. A secure execution environment is available in the ARMv7 architecture, with security extensions implemented.
With reference to
Those of skill in the art would understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal
In one or more exemplary embodiments, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software as a computer program product, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both non-transitory computer-readable storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
