Apparatus and method for memory control, and mobile device

Abstract

A memory control apparatus that includes a queue to store up to 2 access requests to a memory and a command issuer to issue a command to the memory according to access requests stored to the queue. The command issuer includes an address comparator to evaluate whether the access requests stored to the queue are for a same page of the memory. If the access requests are for a same page, the command issuer consecutively issues read/write commands, whereas if the access requests are for different pages, the command issuer issues a pre-charge command after issuing one read command.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram showing a memory controller and peripheral circuitry thereof according to an embodiment of the present invention;

FIG. 2 is a schematic diagram showing a cellular phone as an example of an apparatus having the memory controller according to an embodiment of the present invention;

FIG. 3 is a state transition diagram of a memory that is controlled by the memory controller according to an embodiment of the present invention;

FIG. 4 is a timing chart showing an operation when the memory controller according to an embodiment of the present invention compares addresses at a timing T3;

FIG. 5 is a timing chart explaining a read command READ and a read command with auto pre-charge READA;

FIG. 6 is a timing chart explaining a difference in operations of READ and READA if consecutive access requests are for different banks;

FIG. 7 is a flowchart showing an operation when the memory controller according to an embodiment of the present invention compares addresses at the timing T3;

FIG. 8 is a flowchart showing an operation when the memory controller according to an embodiment of the present invention compares addresses at a timing T5;

FIG. 9.is a timing chart showing an operation when the memory controller according to an embodiment of the present invention compares addresses at the timing T5;

FIG. 10 is a view showing a conventional memory controller;

FIG. 11 is a block diagram showing a SDRAM of 128 Mbits (2M words×16 bits×4 banks) as an example of a conventional memory;

FIG. 12 is a view showing a state transition of a conventional memory;

FIG. 13 is a timing chart for explaining a conventional memory control operation focusing on speed, when performing a consecutive read without pre-charging after a read operation; and

FIG. 14 is a timing chart for explaining a conventional memory control operation focusing on speed, when performing a READA command with auto pre-charge.

Claims

1. A memory control apparatus comprising: a queue to store 2 or more access requests to a memory; anda command issuer to include an evaluator to evaluate whether the 2 or more access requests stored to the queue are access requests to a same page of the memory and to issue a command to the memory according to the evaluation result by the evaluator.

2. The memory control apparatus according to claim 1, wherein the command issuer consecutively issues read/write commands if consecutive access requests are for a same page of the memory, whereas if consecutive access requests are for different pages, the command issuer issues a command to pre-charge.

3. The memory control apparatus according to claim 2, wherein the command issuer issues a read/write command with an auto pre-charge after issuing a command if access requests are for different pages.

4. The memory control apparatus according to claim 2, wherein the command issuer issues a pre-charge command if access requests are for different pages.

5. The memory control apparatus according to claim 1, wherein the evaluator evaluates whether two of the access requests stored to the queue are for a same page, and the command issuer issues a read/write command with an auto pre-charge to automatically pre-charge after the command is issued if the two access requests are for different pages.

6. The memory control apparatus according to claim 1, wherein the evaluator evaluates whether an address indicated by the issued read/write command and an address indicated by an access request are for a same page, if the access request is stored to the queue from after the read/write command is issued to the pre-charge command is issued, and the command issuer issues a read/write command consecutively to the previously issued read/write command if the addresses are for a same page.

7. The memory control apparatus according to claim 1, wherein the queue stores up to two access requests.

8. A method for memory control comprising: evaluating whether 2 or more of the access requests stored to a queue are for a same page of a memory, the queue storing 2 or more of access requests to the memory; andissuing the command according to the evaluation result.

9. The method according to claim 8, wherein in the issuance of the command, read/write commands are consecutively issued if consecutive access requests are for a same page of the memory, whereas if consecutive access requests are for different pages, a command to pre-charge-the memory is issued.

10. The method according to claim 9, further comprising issuing a read/write command with an auto pre-charge if the access requests are for different pages, the read/write command with an auto pre-charge automatically pre-charging after being issued.

11. The method according to claim 9, further comprising issuing a pre-charged command if the access requests are for different pages.

12. The method according to claim 9, further comprising: evaluating two of the access requests to be for a same page if two of the access requests are stored to the queue; andissuing a read/write command with an auto pre-charge to automatically pre-charge after issuing a command, if the two access requests are for different pages.

13. The method according to claim 9, further comprising: evaluating whether an address indicated by the issued read/write command and an address indicated by an access request are for a same page, if the access request is stored to the queue while the memory is in an active state;issuing a read/write command consecutively to the previously issued read/write command if the addresses are for a same page; andissuing a pre-charge command if the addresses are for different pages.

14. A mobile device comprising: a memory;a memory controller to control the memory; anda controller to access the memory via the memory control apparatus,wherein the memory controller comprises:a queue to store 2 or more access requests to the memory; anda command issuer to include an evaluator to evaluate whether the 2 or more access requests stored to the queue are access requests to a same page of the memory and to issue a command to the memory according to the evaluation result by the evaluator.