Apparatus and method for performing small scale subtraction

Abstract

A subtracting circuit which is capable of performing highly accurate, small scale subtraction. The subtracting circuit includes a first input capacitance receiving a first input voltage, a first set of inverters connected with an output terminal of the first input capacitance, a second input capacitance connected with an output terminal of the first set of inverters and receiving a second input voltage, and a second set of inverters connected with an output terminal of the second input capacitance, each set of inverters having capacitive feedback. The subtracting result is output from the second set of inverters.

Description

FIELD OF THE INVENTION

The present invention relates to a subtracting circuit.

BACKGROUND OF THE INVENTION

Conventionally, a digital type subtracting circuit operate on a large scale and an analog type subtracting circuit operates with low accuracy in its calculation.

SUMMARY OF THE INVENTION

The present invention is invented so as to solve the conventional problems. It has a purpose to provide a subtracting circuit capable of performing a subtracting calculation on a small scale with high accuracy. Calculation through this subtracting circuit is therefore easily available for various kinds of calculation manners.

According to the present invention, an inverter is serially connected to an output terminal of two inputs which are coupled capacitively at an input terminal. Another inverter is connected to an output terminal of the above inverter as well as to an output terminal or another dual input capacitive coupling circuit. Accordingly the latter inverter outputs a subtraction result.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

PREFERRED EMBODIMENT OF THE INVENTION

Hereinafter, an embodiment of a subtracting circuit according to the present invention is described with referring to the attached drawings.

In FIG. 1, a subtracting circuit is composed of the first dual input capacitive coupling circuit CP.sub.1, the second dual input capacitive coupling circuit CP.sub.2, the first inverter INV.sub.1 and the second inverter INV.sub.2.

In the first dual input capacitive coupling circuit C.sub.P1, a voltage V.sub.1 and a voltage V.sub.01 are respectively input to capacitors C.sub.1 and C.sub.01. Voltage V.sub.2 is input through a capacitance C.sub.2.

C.sub.P1 is composed of capacitances C.sub.1 and C.sub.01 which are parallelly connected with the first inverter INV.sub.1. A capacitance C.sub.2 is also connected with INV.sub.1. A feedback circuit FC is provided for feeding an output of inverter INV.sub.1 back to its input through a capacitance C.sub.01 in order to get an effect of a summing amplifier.

When voltages for impressing C.sub.1, C.sub.01 and C.sub.2 are V.sub.1, V.sub.01 and V.sub.2, respectively, an input voltage V.sub.00 for INV.sub.1 is defined as following formula (1). ##EQU1##

INV.sub.1 is composed of 3 inverters serially connected. An output of the first inverter changes to low level when V.sub.00 exceeds a threshold voltage. An output of the next inverter changes to high level. Then, an output of the last inverter changes to low level. When the output voltage is defined as V.sub.01, V.sub.01 can be obtained by formula (2).

V.sub.01 =-A.sub.1 V.sub.00 (2) where A1 is an open loop gain. When formula (2) is input to formula (1) after transforming the formula, formulas (3) and (4) can be obtained. ##EQU2## Here, the first term in parentheses of formula (4) can be omitted as it is negligible compared with the second term of it. So formula (4) is substantially defined as formula (5). ##EQU3##

In the second dual input capacitive coupling circuit C.sub.p2, voltage V.sub.01 and a voltage V.sub.out from an output terminal of INV.sub.2 are input, voltage V.sub.3 is also input through a capacitance C.sub.3. Capacitances C.sub.02 and C.sub.03 are parallelly connected within C.sub.P2 for input to the second inverter INV.sub.2. Capacitance C.sub.3 is connected to INV.sub.2 in parallel with C.sub.02 and C.sub.03.

A feedback circuit FC feeds an output from inverter INV.sub.2 back to its input through a capacitance C.sub.03 in order to get an effect of summing amplifier.

Voltage which are applied to C.sub.02, C.sub.03 and C.sub.3 are V.sub.01, V.sub.OUT so that V.sub.3, respectively, and an input voltage V.sub.02 for INV.sub.2 is defined as following formula (6). ##EQU4##

An inverter INV.sub.2 is composed of 3 inverters by serial connecting, similar to INV.sub.1. An output of the first inverter changes to low level when V.sub.02 exceeds a threshold voltage. An output of the next inverter changes to high level. Then an output of the last inverter changes to low level. When the output voltage is defined V.sub.out, then formula (7) is obtained, according to the same reason of above formulas from (2) to (5). ##EQU5## Here, inputting formula (5) to formula (7) and transforming it, formulas (8) and (9) are obtained. ##EQU6## Here if C.sub.01 is equal to C.sub.02, then formula (10) is obtained. ##EQU7##

As a result, subtraction result is substantially obtained.

As mentioned above, an inverter is serially connected to an output terminal of the dual input capacitive coupling circuit provided at an input terminal, another inverter is connected to an output terminal of the above inverters as well as to an output terminal of another capacitive coupling circuit connected with another two inputs of voltage. The latter inverter outputs a subtraction result, so that the present invention has a purpose to provide a subtracting circuit capable of subtracting calculation with small scale and high accuracy and easily realize a various kinds of manners of calculations.

Claims

1. A subtracting circuit comprising:

a first input capacitance for receiving a first input voltage;

a first set of inverters having an input coupled to said first input capacitance, said first set of inverters being series connected and consisting of an odd number of inverters;

a second input capacitance for receiving a second input voltage;

a connecting capacitance having a first terminal coupled to an output of said first set of inverters and a second terminal coupled to said second input capacitance, said second terminal of said connecting capacitance developing a voltage indicative of a difference between said first input voltage and said second input voltage;

a second set of inverters having an input coupled with said second terminal of said connecting capacitance for generating a subtracted output voltage, said second set of inverters being series connected and consisting of an odd number of inverters;

a first feed-back capacitance connecting said input and said output of said first set of inverters; and

a second feed-back capacitance connecting said input and an output of said second set of inverters.

2. A method for subtracting voltage signals comprising the steps of:

inputting at least one first voltage signal;

generating a coupled first voltage signal based on said first input voltage signal using a capacitor;

inverting said coupled first voltage signal with a first set of serially connected inverters to generate an inverted first voltage signal;

coupling first feedback voltage with said coupled first voltage signal, said first feedback voltage being based on said inverted first voltage signal;

inputting at least one second voltage signal;

coupling said inverted first voltage signal and said second input voltage signal using a capacitor to generate a third voltage signal which is indicative of a difference between said input voltage signals;

inverting said third voltage signal with a second set of serially connected inverters to generate an output voltage signal which is based on a difference between said first and said second voltage signals input; and

coupling second feedback voltage with said third voltage signal, said second feedback voltage being based on said output voltage signal.