Claims
- 1. An apparatus comprising:
a memory controller to control a random access memory that has self-refresh capability; and a self-refresh circuit external to the memory controller to place the memory into a self-refresh state.
- 2. An apparatus as recited in claim 1, wherein the self-refresh circuit is purely hardware-based.
- 3. An apparatus as recited in claim 1, wherein the memory is a form of dynamic random access memory.
- 4. An apparatus as recited in claim 3, wherein the memory is a form of synchronous dynamic random access memory.
- 5. An apparatus as recited in claim 1, wherein the self-refresh circuit is to place the memory into the self-refresh state in response to a predetermined condition associated with a power-down or reset event.
- 6. An apparatus as recited in claim 1, wherein the self-refresh circuit comprises:
a state machine to receive a plurality of control signals and to generate a plurality of memory control signals to control the memory; and a multiplexer circuit coupled to the state machine and to the memory.
- 7. An apparatus as recited in claim 6, wherein the self-refresh circuit further comprises a bus clock generator to generate a clock signal to control the memory.
- 8. An apparatus as recited in claim 1, further comprising a power management and selection circuit to receive power from a primary power source and from an auxiliary power source and to provide power to the memory from the primary power source when a level of the primary power source satisfies a predetermined condition and from the auxiliary power source when the level of the primary power source does not satisfy the predetermined condition.
- 9. An apparatus comprising:
a memory controller to control a dynamic random access memory that has self-refresh capability; and means external to the memory controller for placing the memory into a self-refresh state.
- 10. An apparatus comprising:
a memory controller to generate a first plurality of memory control signals for controlling a dynamic random access memory that has self-refresh capability; and a self-refresh circuit external to the memory controller to place the memory into a self-refresh state in response to a predetermined condition, the self-refresh circuit to generate a second plurality of memory control signals for controlling the memory based on a plurality of input signals, each of the second plurality of memory control signals corresponding to a separate one of the first plurality of memory control signals, the self-refresh circuit to select between the first plurality of memory control signals and the second plurality of memory control signals to provide to the memory, based on the plurality of input signals.
- 11. An apparatus as recited in claim 10, wherein the self-refresh circuit is purely hardware-based.
- 12. An apparatus as recited in claim 10, wherein the memory is a form of synchronous dynamic random access memory.
- 13. An apparatus as recited in claim 10, wherein the self-refresh circuit comprises:
a state machine to receive the plurality of control signals and to generate the second plurality of memory control signals; and a plurality of multiplexers coupled to the state machine and to the memory.
- 14. An apparatus as recited in claim 10, wherein the plurality of input signals includes a trigger signal that is asserted in response to occurrence of any of a plurality of conditions that require a reset.
- 15. An apparatus as recited in claim 10, wherein the self-refresh circuit further comprises a bus clock generator to generate a clock signal to control the memory.
- 16. An apparatus as recited in claim 10, further comprising a power management and selection circuit to receive power from a primary power source and from an auxiliary power source and to provide power to the memory from the primary power source when a level of the primary power source satisfies a predetermined condition and from the auxiliary power source when the level of the primary power source does not satisfy the predetermined condition.
- 17. A self-refresh management circuit for use in a processing system that includes a dynamic random access memory that has self-refresh capability and a memory controller to control the memory, the self-refresh management circuit comprising:
a state machine, external to the memory controller, to generate a set of memory control signals for controlling the memory, to cause the memory to enter a self-refresh state, the set of memory control signals corresponding to a separate set of memory control signals output by the memory controller; and a multiplexer circuit, external to the memory controller, to receive and select between the set of memory control signals from the state machine and the set of memory control signals from the memory controller, in response to a selection signal from the state machine.
- 18. An apparatus as recited in claim 17, wherein the self-refresh management circuit is purely hardware-based.
- 19. A self-refresh management circuit as recited in claim 17, wherein the memory is a form of synchronous dynamic random access memory.
- 20. A self-refresh management circuit as recited in claim 17, wherein the state machine is responsive to a trigger signal that is asserted in response to occurrence of any of a plurality of conditions that require a reset.
- 21. A self-refresh management circuit as recited in claim 17, further comprising a bus clock generator to generate a clock signal to control the memory.
- 22. A self-refresh management circuit for use in a processing system that includes a processor, a dynamic random access memory that has self-refresh capability coupled to the processor, and a memory controller to generate a first plurality of memory control signals for controlling the memory, the self-refresh management circuit comprising:
a state machine external to the memory controller and having a plurality of states selected according to a plurality of input signals, the state machine to generate a second plurality of memory control signals for controlling the memory according to a state of the state machine and to place the memory into a self-refresh state, each of the second plurality of memory control signals corresponding to a separate one of the first plurality of memory control signals, the state machine further to output a selection signal according to the state of the state machine, and a plurality of multiplexers external to the memory controller, each having a first input and a second input and providing an output memory control signal to the memory to control the memory, each of the multiplexers to receive a separate one of the first plurality of memory control signals at the first input and a separate one of the second plurality of memory control signals at the second input and to select between the first input and the second input, according to the selection signal, to determine the output memory control signal.
- 23. An apparatus as recited in claim 22, wherein the self-refresh circuit is purely hardware-based.
- 24. A self-refresh management circuit as recited in claim 22, wherein the memory is a form of synchronous dynamic random access memory.
- 25. A self-refresh management circuit as recited in claim 22, wherein the plurality of input signals includes a trigger signal that is asserted in response to occurrence of any of a plurality of conditions that require a reset.
- 26. A self-refresh management circuit as recited in claim 22, wherein the self-refresh circuit further comprises a bus clock generator to generate a clock signal to control the memory.
- 27. A storage system apparatus comprising:
a processor; a storage interface coupled to the processor to allow data communication with a plurality of non-volatile mass storage devices; a network interface coupled to the processor to allow data communication with a remote processing system over a network; a dynamic random access memory that has self-refresh capability, coupled to the processor; a memory controller to control the memory; and a self-refresh management circuit coupled to the memory external to the memory controller, the self-refresh management circuit including
a state machine to generate a plurality of memory control signals for controlling the memory and to cause the memory to enter a self-refresh state, the plurality of memory control signals corresponding to a separate plurality of memory control signals output by the memory controller, and a plurality of multiplexers, each to receive and select between a separate one of the plurality of memory control signals from the state machine and a corresponding separate one of the plurality of memory control signals from the memory controller, in response to a selection signal from the state machine.
- 28. An apparatus as recited in claim 27, wherein the self-refresh management circuit is purely hardware-based.
- 29. A storage system apparatus as recited in claim 27, wherein the memory is a form of synchronous dynamic random access memory.
- 30. A storage system apparatus as recited in claim 27, wherein the state machine is responsive to a trigger signal that is asserted in response to occurrence of any of a plurality of conditions that require a reset.
- 31. A method comprising:
operating a processing system that includes a processor, a memory controller and a random access memory that has self-refresh capability; and using a self-refresh circuit external to the memory controller to place the memory into a self-refresh state.
- 32. A method comprising:
receiving a plurality of input signals relating to operation of a processing system that includes a memory controller and a dynamic random access memory that has self-refresh capability; receiving a first plurality of memory control signals generated by the memory controller; generating a second plurality of memory control signals outside the memory controller, each of the second plurality of memory control signals corresponding to a separate one of the first plurality of memory control signals; and selectively providing either the first plurality of memory control signals or the second plurality of memory control signals to the memory, based on the plurality of control signals, to place the memory into a self-refresh state.
- 33. A method as recited in claim 32, wherein said generating a second plurality of memory control signals comprises using a state machine outside the memory controller to generate the second plurality of memory control signals.
- 34. A method as recited in claim 32, wherein said selectively providing either the first plurality of memory control signals or the second plurality of memory control signals to the memory comprises using a plurality of multiplexers controlled according to a state of the state machine.
- 35. A method as recited in claim 32, wherein the plurality of input signals includes a trigger signal that is asserted in response to occurrence of any of a plurality of conditions that require a reset.
- 36. A method as recited in claim 32, further comprising:
receiving power from a primary power source and from an auxiliary power source; providing power to the memory from the primary power source when a level of the primary power source satisfies a predetermined condition; and providing power to the memory from the auxiliary power source when the level of the primary power source does not satisfy the predetermined condition.
Parent Case Info
[0001] This is a continuation-in-part of copending U.S. patent application Ser. No. 10/219,376, filed on Aug. 15, 2002 and entitled, “Method and Apparatus to Establish Safe State in a Volatile Computer Memory under Multiple Hardware and Software Malfunction Conditions,” which is incorporated herein by reference.
Continuation in Parts (1)
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Number |
Date |
Country |
Parent |
10219376 |
Aug 2002 |
US |
Child |
10407533 |
Apr 2003 |
US |