BRIEF DESCRIPTION OF THE DRAWINGS
Examples of the subject matter claimed herein are illustrated in the figures of the accompanying drawings and in which reference numerals refer to similar elements and in which:
FIG. 1 shows examples of status signals that may be produced by an LED, or the like, to provide information.
FIG. 2 is an exemplary diagram illustrating a battery charger according to one embodiment of the disclosure.
FIG. 3 is an example of waveforms of low and high frequency pulse trains and a serrated pulse train according to one embodiment of the disclosure.
FIG. 4 is an exemplary diagram showing spectra corresponding to the low and high frequency pulse trains and the serrated pulse train in FIG. 3.
FIG. 5 is an example of a circuit topology for adjusting LED current for various blink rates of the serrated pulse train according to one embodiment of the disclosure.
FIG. 6 is a first exemplary block diagram of a pulse generator according to an embodiment of the disclosure.
FIG. 7 is a second exemplary block diagram of a pulse generator according to an embodiment of the disclosure.
FIG. 8 is a third exemplary block diagram of a pulse generator according to an embodiment of the disclosure.
FIG. 9 is a fourth exemplary block diagram of a pulse generator according to an embodiment of the disclosure.
FIG. 10 is an example of a circuit topology of an oscillator according to an embodiment of the disclosure.
FIG. 11 is exemplary waveforms of the oscillator shown in FIG. 10.
FIG. 12 is an example of a circuit topology of a frequency divider according to an embodiment of the disclosure.
FIG. 13 is an example of a flip-flop circuit implemented in the frequency divider of FIG. 12.
FIG. 14 is an example of a circuit topology of a serrated pulse generator and a deglitcher used for a battery charger according to an embodiment of the disclosure.
FIGS. 15A-1SE shows exemplary waveforms generated by the oscillator of FIG. 10, the frequency divider of FIG. 12 and the serrated pulse generator of FIG. 14.
FIG. 16 is an example of waveforms illustrating synchronization of edges of pulses according to an embodiment of the disclosure.
FIGS. 17A and 17B are exemplary timing charts showing generation of a serrated pulse train according to an embodiment of the disclosure.
FIG. 18 is an exemplary timing chart showing generation of truncated clock signals according to an embodiment of the disclosure.
FIG. 19 is an exemplary block diagram illustrating connection of a /CHRG pin of a battery charger according to an embodiment of the disclosure.
FIG. 20 is an example of a modified serrated signal according to an embodiment of the disclosure.
FIG. 21 is an example of a circuit topology of another serrated pulse generator configured for providing multiple status bits used for a battery charger according to an embodiment of the disclosure.
FIGS. 22-25 are exemplary simulated waveforms generated in the circuit shown in FIG. 21, in which FIG. 22 shows a simulation with data bit B0=L and data bit B1=L, FIG. 23 shows a simulation with data bit B0=H and data bit B1=L, FIG. 24 shows a simulation with data bit B0=L and data bit B1=H, and FIG. 25 shows a simulation with data bit B0=H and data bit B1=H.
FIG. 26 is an exemplary diagram illustrating a modified battery charger according to one embodiment of the disclosure.
FIG. 27 is an exemplary circuit topology of control logic for a multiple-bit receiver included in the battery charger of FIG. 26.
FIG. 28 is exemplary simulated waveforms explaining operation of the control logic shown in FIG. 27.