Claims
- 1. A method of programming a PMOS floating gate memory cell having a p+ source, a p+ drain, a floating gate, and a control gate, said method comprising the steps of:
- injecting into said floating gate hot electrons induced predominantly by band-to-band tunneling until a predetermined event occurs; and
- after said predetermined event occurs, predominantly inducing injection of channel hot electrons into said floating gate.
- 2. The method of claim 1, wherein said predetermined event comprises a threshold voltage of said memory cell reaching a predetermined level.
- 3. The method of claim 2, wherein said predetermined level is between approximately 0 and 2 volts.
- 4. The method of claim 1, wherein said predetermined event comprises a gate current of said memory cell decreasing below a predetermined level.
- 5. The method of claim 4, wherein said predetermined level is approximately 1 pA.
- 6. The method of claim 1, wherein the band-to-band tunneling of electrons is induced by applying a first voltage to said p+ source, a second voltage to said p+ drain, and approximately 10 volts to said control gate.
- 7. The method of claim 1, wherein the injection of channel hot electrons into said floating gate is induced by applying a first voltage to said p+ source, a second voltage to said p+ drain, and approximately 8 volts to said control gate.
- 8. The method of either claim 6 or 7, wherein said first voltage is approximately 8 volts and said second voltage is approximately 3 volts.
- 9. The method of claim 1, wherein when said predetermined event occurs, a program voltage applied to said control gate is reduced from approximately 10 volts to approximately 8 volts.
- 10. A method of programming a floating gate memory cell by using a programming voltage to successively alternate between (1) predominantly injecting hot electrons induced by a band-to-band tunneling into said floating gate and (2) predominantly injecting channel hot electrons into said floating gate.
- 11. The method of claim 10, wherein a clock signal alternating between a first potential associated with the first injecting step and a second potential associated with the second injecting step is coupled to said control gate to facilitate programming of said memory cell.
- 12. The method claim 11, wherein said first potential is approximately 10 volts and said second potential is approximately 8 volts.
- 13. The method of claim 11, wherein said clock signal has a period associated therewith of approximately 1-2 .mu.s.
- 14. The method of claim 11, wherein a first portion of a period of said clock signal, during which said control gate is at said first potential, is greater than a second portion of said period of said clock signal, during which said control gate is at said second potential.
- 15. The method of claim 11, wherein a first portion of a period of said clock signal, during which said control gate is at said first potential, is less than a second portion of said period of said clock signal, during which said control gate is at said second potential.
- 16. The method of claim 11, wherein said clock signal has a period associated therewith, said period increasing as function of time.
- 17. The method of claim 11, wherein said clock signal has a period associated therewith, said period decreasing as function of time.
CROSS REFERENCE TO RELATED APPLICATIONS
This application is related to the commonly-owned U.S. patent applications Ser. No. 08/948531, filed Oct. 9, 1997, now U.S. Pat. No. 5,909,392 entitled "PMOS Memory Array Having OR Gate Architecture," and Ser. No. 08/947850, filed Oct. 9, 1997, now pending entitled "Nonvolatile PMOS Two Transistor Memory Cell and Array", both filed on the same day as the present application.
Non-Patent Literature Citations (1)
Entry |
Ohnakado, T., et al., "Novel Electron Injection Method Using Band-to-Band Tunneling Induced Hot Electron (BBHE) for Flash Memory with a P-Channel Cell", IEEE pp. 279-282 (1995). |