A more detailed understanding of the invention may be had from the following description, given by way of example and to be understood in conjunction with the accompanying drawings wherein:
The present invention will be described with reference to the drawing figures wherein like numerals represent like elements throughout. For purposes of describing the present invention, the phrase low, medium, or high voltage levels may be used. It will be appreciated that the words “low”, “medium”, and “high” are relative terms and not necessarily a fixed voltage. Accordingly, the phrase low, medium, and/or high voltage level may be any voltage and may vary, for example, based on the processing technology and/or the material in which an electronic device is implemented.
As used herein, the word “level” may represent a fixed voltage or a voltage range, as desired. A node and a voltage at a node may be used interchangeably. Substantially may mean slightly less than, equal to, or slightly more than a numerical value.
The present invention may be used in any electronic device desiring a robust, temperature compensated reference current. In particular, a memory device may need a constant reference current for proper operation in operating environments having various wide temperature ranges. Examples of memory devices include parallel or serial Electrically Erasable Programmable Read-Only Memories (EEPROMs), Flash memories, serial Flash memories, and stacked Flash and Random Access Memory (RAM) modules.
The reference current level Iref at node 208 is dependent upon current I1 at node 205, the compensation current Icomp, and the gain of OP-AMP 210. Current I1 on node 205 is linearly proportional to the absolute temperature (PTAT) of the operating environment for circuit 200. The NMOS transistors 224, 226, and 228 are matched having the same W/L ratios and substantially equal threshold voltage levels. Transistors 224, 226, and 228 may also have similar layout patterns in an integrated circuit and may be in proximity to each other, as desired. Since the threshold voltage of NMOS transistor 224 is substantially similar or equal to NMOS transistor 226, the node voltage VF of transistor 224 is equal to the emitter-to-base voltage level Veb of PNP BJT transistor 218 giving the following relationship for the compensation current Icomp:
In Equation (6), Veb(T) is given by Equation (7) as follows:
In Equation (7), kb is Boltzmann's constant 1.381×10−23 Joules per Kelvins (K), T is the absolute temperature in Kelvins, q is the constant electron charge of 1.602×10−19 Coulombs, and Is(T) is the saturation current of transistor 224 given by Equation (3). The emitter current Ie(T) at node 230 is given by Equation (8) as follows:
In Equation (8), M is a variable multiplier characteristic of BJT 220 with respect to the size of BJT 218, and R is related to the resistance value of resistors R1 212, R2 214, and R3 216. Substituting Equation (8) and Equation (3) into Equation (7) and taking the first derivative of Veb(T) with respect to temperature gives Equation (9) as follows:
In Equation (9), A is the area of the device gate, D is the carrier diffusivity, N is the doping concentration, W is the channel width, B is a material dependent parameter, typically 5.4×1031 K−3 cm6 for silicon, and Egap is the energy gap, typically 1.12 eV for silicon, for NMOS transistor 224. Purely as an example, assuming a predetermined working temperature range of −40° Celsius to 125° Celsius the variation of
is minimal, typically −1/−2 mV/° K., and substantially constant. Equation (9) provides a substantially constant slope and linear function for Veb(T) resulting in a linear relationship to temperature of the compensation current Icomp(T) in Equation (6).
The compensation current Icomp(T) can properly negate the effects of the current I1(T) at node 205 by using an appropriate adjusted value for resistor RF 232, providing a substantially constant, flat reference current Iref at node 208. As illustrated in
Since Icomp is independent of the threshold voltages of NMOS transistors 224, 226, and 228 it is also not directly dependent on circuit fabrication process variations of transistors or other elements in circuit 200. Current Icomp is also independent of any supply voltage levels, such as Vdd. Moreover, the compensation current does not require NMOS transistor 224 to be biased in weak-inversion mode, providing more robust operation and design flexibility of generator circuit 200 since weak-inversion mode depends strongly on process varying parameters.
Although the features and elements of the present invention are described in the preferred embodiments in particular combinations, each feature or element can be used alone without the other features and elements of the preferred embodiments or in various combinations with or without other features and elements of the present invention.