The preferred embodiment of the present invention will be described in detail by way of following examples and with reference to the above-mentioned figures.
The above analysis on time-slicing and frame-slicing power reduction schemes show that a high burst data-rate, Cb in equation (1), is necessary for both time-slicing and frame-slicing schemes to achieve the required power saving efficiency. Also, to maintain a certain level of quality of service (QoS), the required high Cb should be always achievable independent of channel environment variations. Together, in practice, these requirements imply that the system architecture design and the choice of related algorithms should make the high-rate transmission workable under the worst channel conditions such as a fast fading environment (with larger Doppler frequency shift—a significant problem for mobile devices).
After that, the bit streams will be encoded by an inner channel encoder 38 such as a convolutional coder, Turbo coder or Turbo-like coder. The coded bits are then sent to an inner interleaver 40. The resulting interleaved bit streams 42 are mapped to phase shift keying (PSK) or quadrature amplitude modulation (QAM) constellations (not shown). Finally, these constellation mapped symbols, are used to form the orthogonal frequency division multiplexing (OFDM) signal frames by an OFDM Modulator 44.
The transmitter also comprises a digital-to-analogue converter (DAC) 46 and a RF transmitter 48 for transmitting the transmission signal over a channel 50 to the receiver.
At the receiver side, the reverse operations of the transmitter are performed with some additional processing blocks such as automatic gain control (AGC), synchronisation and channel estimation for handling the noisy and multipath fading channel environments. As illustrated in
If one considers PALL=PRF+PBB to be the overall power consumption of a regular DTT receiver (i.e., the device may not implement a TDM-based power reduction scheme), and PRF and PBB be the power consumed by the RF tuner 52 and the baseband processor (not shown), respectively. The required power consumption for a handheld device becomes:
Since DTV broadcasting is mainly in downlink transmission, it can be assumed that PRF only varies with the AGC 58 control in adaptation to variations of actual channel 50 environment. In the baseband part, however, the situation is quite different. Processing complexity and, thus, required power consumption, PBB, are usually design-dependent and become fixed after realisation. Thus, PBB can be regarded as independent on the channel variations. Obviously, by default, the baseband processor would operate at its highest level of PBB as the design and implementation of baseband demodulator and decoder need to take account of the worst channel condition. Taking into consideration the fact that PRF and PBB occupy almost an equal proportion of the overall power in a regular OFDM-based DTT system, it becomes necessary to reduce further PBB such that the required power consumption, PALL, of a regular device, or, PHA, of a handheld device is minimized. Following equation (2), when the required PBB of a regular DMB-T device goes down from 800 mW to 500 mW, for example, PHA will be down to 30 mW from 40 mW.
Given a high target of Cb, operational module control algorithms which are usually of high complexity are most likely selected for achieving robust receiving under less-than-ideal channel conditions. The channel estimation algorithm, for example may need to be enhanced for fast fading channel conditions in a mobile environment. These enhanced algorithms, which are usually computationally expensive, are actually redundant in situations such as when the user is slowly moving (e.g., pedestrian) and even still.
A power reduction scheme is illustrated in
The receiver is configured to make a decision on whether to operate one or more of operational modules 80, 82, 84, 85, 86, 87 in the first or the second mode from a real-time assessment of the channel 50 conditions. One way of doing this is to monitor the error detection activities of the RS decoder (88 in
When continued monitoring of the channel is effected—i.e. an estimation of the channel environment is an ongoing process—the receiver is configured to toggle between first and second modes of operation in dependence of the continued estimation. Because of the reduction in complexity of the operational status of the receiver, embodiments of the receiver are configured to consume less electrical power when the module operates in the second mode of operation than when in the first mode of operation.
A detailed explanation of
N is a predetermined minimum number of consecutive error-free RS coding blocks which are received at the receiver prior to a determination that the channel is in a “good” condition;
M is a predetermined maximum number of consecutive error-free RS coding blocks which are to be received in the second mode of operation prior to reverting to operation in the first mode of operation;
After operation in the second mode of operation, P is a predetermined minimum number of consecutive error-free RS coding blocks which are to be received in the first mode of operation prior to switching back to operation in the second mode of operation when the channel is in a “good” condition; and
k is a count of error-free RS coding blocks received in a channel “good” condition (i.e. after receipt of N error-free blocks described above) and is used to control the process flow.
Initially, k is set to zero, and any or all of operational modules 80, 82, 84, 85, 86, 87 are operated in the first mode of operation. RS decoder 88 monitors the signal received over channel 50 for N consecutive error-free RS coding blocks at decision step 90. Before N consecutive error-free RS coding blocks are detected, the condition of channel 50 is considered to be “not good”. As such, k is kept at zero at step 92 and the one or more operational modules 80, 82, 84, 85, 86, 87 are operated in the respective first modes of operation. Upon detection of the Nth consecutive error-free RS coding block at step 90, the apparatus determines that the channel is in a “good” condition, and switches operation of one or more of operational modules 80, 82, 84, 85, 86, 87 to the second mode of operation.
Power saving can be effected by replacing complicated operation of the operational modules 80, 82, 84, 85, 86, 87 with simpler operational modes when the channel is found to be good for signal transmission. That is, in one example, the first mode of the operational module is a normal mode of operation and the second mode of the operational module is a simplified mode of operation. In
When in the second mode of operation, the apparatus will revert operation of the one or more operational modules to the first mode of operation in either of two ways. First, if an error is detected in an RS coding block, decision step 90 determines that N consecutive error-free coding have not now been received. Count k is then reset to zero at step 92 and the one or more operational modules are then switched back to the first mode of operation.
Secondly, to prevent any possible misjudgement due to, for example, baseband processing delay, and in order to make the channel adaptation still robust when it is not possible to make a clear distinction between good or not good channel conditions, a regular return to the first mode of operation (i.e. a more sophisticated processing state), even when the current channel conditions are found good, is performed. After determination at step 90 that the channel 50 is in a “good” condition, the apparatus checks at step 94 whether the number of the presently-received block is equal to M. In other words, the apparatus determines whether the maximum number of consecutive RS coding blocks in the second mode (i.e. simplified mode) of operation has been exceeded (k is equal to M). If the apparatus determines at step 94 that M has not been exceeded, then the one or more of operational modules 80, 82, 84, 85, 86, 87 continue to operate in the second mode and count k is incremented by 1 at step 96.
If no error is detected in the received RS coding blocks, the apparatus controller loops around steps 80/82/84/85/86/87, 88, 90, 94, 96 incrementing k in each loop until the apparatus determines that count of the presently-received RS coding block means that the number M has been reached (that is, k is equal to M) and proceeds to revert operation of the one or more operational modules 80, 82, 84, 85, 86, 87 to the first (normal) mode of operation.
When operation is switched back to the first mode, predetermined count P defines the number of RS coding blocks to be received in this iteration of operation of the one or more operational modules 80, 82, 84, 85, 86, 87 in the first mode. At step 98, the apparatus determines whether the kth received coding block means count k=M+P. If not, count k is incremented by 1 at step 100 and operation of the one or more operational modules continues in the first mode of operation.
Upon detection that k equals M+P, k is reset (i.e. forced to zero) at step 92, and the one or more operational modules 80, 82, 84, 85, 86, 87 of the apparatus continue operation in the first mode. However, in the next pass through step 90, the apparatus detects that k has been reset to zero. If the channel condition remains “good” then receipt of N error-free coding blocks at step 90 is immediately detected and operation of the one or more operational modules is switched back to the second mode of operation.
Thus, by monitoring the parameter k, a balance between quality of service (QoS) with power savings can be effected. Further, continued toggling between first and second modes of operation is controlled by prescribing the maximum number of consecutive RS coding blocks that can be received in the second mode, and the minimum number of consecutive RS coding blocks that should be received in the first mode; that is, with reference to counts M and P. Therefore, it can be seen that such a signal processing algorithm can control the apparatus to toggle operation of the one or more operational modules between first and second modes in dependence of the received coding blocks, not only between good and bad channel conditions, but also in a regular pattern when the channel is friendly to transmission.
It should be pointed out that, here, the choice of the parameters N, M and P depends on actual design requirements, as these parameters are the determinant factors for balancing the required power saving efficiency and the QoS to be provided. If N is selected small, M large and P small, more power saving can be achieved, but at the price of lower QoS, and vice versa. In actual implementation, these parameters can be predefined or be hardware-reconfigurable.
Thus, it is possible to reduce further the required PBB of a DTT receiver by making PBB adaptive to the actual channel environment. Given a high target of Cb, those algorithms which are usually of high complexity are most likely selected for achieving robust receiving under very bad channel conditions. The channel estimation algorithm, for example may need to be enhanced for fast fading channel conditions in a mobile environment. These enhanced algorithms, which are usually computationally expensive, are actually redundant in most situations such as when the user is moving slowly (e.g., pedestrian) and even still.
The channel estimation 84, which is a significant component for achieving acceptable system performance in a mobile environment, is now discussed as a detailed example of demonstrating the effectiveness of the proposed power saving scheme. As discussed above, this module may be switched from enhanced to simplified functionality to reduce power consumption.
In the DMB-T system, the channel estimation is per signal frame based and is performed in the time domain using the PN sequence of each Frame Sync 20, please refer to China Patent Application No. 200410009944.1, publication date: May 18, 2005 (Patent 944). Suppose that the channel impulse response (CIR) at the Frame Sync 20 of the nth signal frame has been estimated as ĥ(n,N0,l). Here, N0 denotes the relative position of Frame Sync 20 in a signal frame 8 and l denotes the index of CIR taps. Assume that the first path is the main path of the channel 50, the channel frequency response (CFR) estimation at the kth subcarrier, Ĥ(n,N0,k), over the Frame Sync 20 interval of the nth signal frame 8 can be obtained by performing a discrete Fourier transform (DFT) on ĥ(n,N0,l).
It can be seen that the CFR estimation achieved, Ĥ(n,N0,k), can be used for equalising the Frame Body 22 of the nth signal frame provided that the channel 50 is invariant over the duration of a signal frame 8. However, this may not be always true in practice, as indicated in Patent 944. When the channel 50 is timing-varying over the duration of a signal frame 8, the following enhanced channel estimation described in Patent 944 may apply.
Assume that the channel 50 undergoes a linear variation over the period of a signal frame 8, the kth subcarrier's CFR, Ĥ(n,N0,k), at the time instant of the ith data symbol of the nth Signal Frame Body 22 can be estimated by linear interpolation as:
Ĥ(n,i,k)=ĤA(n,k)−aiĤD(n,k) (3)
where ai is a linear function of i. Define:
Ĥ
A(n,k)(Ĥ(n,N0,k)+{circumflex over (H)}(n−1,N0,k))/2 (4)
and:
H
D(n,k)=(Ĥ(n,N0,k)−{circumflex over (H)}(n−1,N0,k))/2 (5)
And let X(n)=[X(n,1), X(n,2), . . . , X(n,Nb)] and Y(n)=[Y(n,1), Y(n,2), . . . , Y(n,Nb)] be transmitted and received data vectors of the nth signal frame body 22, respectively. Also, let us define the diagonal matrices, A=diag (a1, a2, . . . aNb); U(n)=diag (ĤA(n,1), ĤA(n,2), . . . , ĤA(n,Nb)); and V(n)=diag (ĤB(n,1), ĤB(n,2), . . . , ĤB(n,Nb)) with ĤB(n,k)=ĤD(n,k)/ĤA(n,k). The system transmission thus can be modelled in the frequency domain as:
Y(n)=(I−T(n))·U(n)·X(n)+Z(n) (6)
where Z(n) is a white Gaussian noise vector, and, T(n)=WAWHV(n) with W and WH being the DFT and inverse DFT (IDFT) matrices, respectively. Thus, the equalised nth signal frame body becomes:
{circumflex over (X)}(n)=U(n)−1·(I−T(n))−1·Y(n) (7)
where I is an identity matrix. The actual implementation of equation (7) requires significant expense as it involves a very complicated matrix inversion operation, (I−T(n))−1. The high complexity can be reduced by using the following approximation as:
As a result, the simplified equalisation can be performed as:
Therefore, the receiver is configured to receive a signal frame of the transmitted signal, the signal frame comprising a frame body, and to perform, in the frequency domain, a simplified equalisation of the frame body. Thus, embodiments of the receiver perform the simplified equalisation of the frame body by performing an approximation of a matrix inversion operation.
Obviously, the above channel estimation and equalisation can be easily incorporated into the proposed power reduction scheme, as a trade-off between system performance and computational complexity can be easily made simply by choosing a suitable Q value (i.e. number of iterations of the “T” process). Receiver designers can choose Q=0 in a case where the channel is good and increase it to 1 or an even larger value for fast varying channels. Note that, from equations (8) and (9), with an increment of 1, an extra “T” process is required. Since the “T” process involves both IDFT and DFT operations, significant power savings are expected by reducing one “T” process in this case. That is, the receiver performs the approximation of the matrix inversion operation in an iterative process, a number of iterations of the iterative process being determined in dependence of the estimate of the channel environment. The receiver may also transition between enhanced and simplified functionality of the channel estimator module by variation of the number of iterations of the iterative process.
Embodiments of the receiver are configured to operate with simplified functionality by performing the simplified equalisation of the frame body instead of the normal equalisation. Significant power reductions may still be realised in such implementations.
It should be emphasised that, although this particular example demonstrates the RS decoder's error detection capability to assess the channel conditions in this invention, the concept can be extended to other scenarios where the RS coding is replaced by another error detection/correction mechanism such as a cyclic redundancy check (CRC) or even low-density parity-check (LDPC) code. As long as the replacement has error detection capability, the power reduction scheme presented in this example remains valid.
Further, it will be appreciated that the invention has been described by way of example only and variations in design detail may be made without departing from the spirit and scope of the invention.
Number | Date | Country | Kind |
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200606233-5 | Sep 2006 | SG | national |