Claims
- 1. A data processing system comprising:
a plurality of digital signal processor subsystems, each subsystem including:
a digital signal processor, and a memory unit; a peripheral direct memory access unit coupled to the memory unit of each subsystem, the peripheral direct access memory having a plurality of memory subunits, each memory subunit receiving packets of data from at least one of the processor subsystems; and a high level data link controller, the high level data link memory including:
FIFO memory unit, and a processor, the processor reading signal groups from a location and transmitting the signal groups, the processor unit providing an ABORT signal to the processor generating a packet currently being transmitted by the processor when the next packet signal groups is not available in the FIFO memory unit a timely fashion for transmission with the packet.
- 2. The data processing system as recited in claim 1 wherein, when the ABORT signal is generated, a message is sent indicating that the previously transmitted packet should be ignored.
- 3. The data processing system as recited in claim 1 wherein after the generation of the ABORT signal, signal groups associated with the packet are transferred from the peripheral direct memory access unit to the FIFO memory unit.
- 4. The data processing system as recited in claim 3 wherein the signal groups transferred to the FIFO memory unit after the ABORT signal are removed from the FIFO memory unit and discarded.
- 5. The data processing system as recited in claim 4 wherein processor sends a SECOND INTERRUPT signal to the peripheral direct memory access unit after all the signal groups associated with a packet have been transferred to the FIFO memory unit, the SECOND INTERRUPT signal resulting in signal groups associated with a different packet being transferred to the FIFO memory unit.
- 6. The data processing system as recited in claim 5 wherein the processor applies a FIRST INTRRUPT signal to peripheral direct memory access unit to transfer a signal group from a channel memory to the FIFO memory unit.
- 7. In a data processing system having a plurality of digital signal processor subsystems, a method of transferring a packet of signal groups from a peripheral direct memory access unit to a high level data link controller, the method comprising:
associating each digital signal processing unit with a one of a plurality of channel memories in the peripheral direct memory access unit; transferring packets of signal groups from the digital signal processors to the associated channel memory transferring the signal groups to a FIFO memory unit in the high level data link controller for processing and transmission as a packet; and generating an ABORT signal when a signal group is not available for processing in the FIFIO memory unit.
- 8. The method as recited in claim 7, the method further comprising:
applying the ABORT signal to the digital processor system generating the signal groups being processed as a packet.
- 9. The method as recited in claim 8, the method further comprising:
transmitting a signal group indicating that the transmitted packet portion should not be processed.
- 10. The method as recited in claim 8, the method further comprising:
in response to a SECOND INTERRUPT signal, selecting a one of the channel memories; in response to a FIRST INTERRUPT signal, transferring a first signal group of a packet from the channel memory selected by the SECOND INTERRUPT signal to the a FIFO memory unit in the high level data link controller; when a signal group has been transferred to the FIFO memory unit and the FIFO memory has an empty location, generating a next FIRST INTERRUPT signal, the next FIRST INTERRUPT signal causing a next sequential signal group for be transferred from the selected channel memory to the FIFO memory unit; continuing to generate a next FIRST INTERRUPT signal until all the signal groups of a packet are transferred to the FIFO memory after generation of an ABORT signal.
- 11. In a data processing system having plurality of digital signal processor subsystems, an interface unit for transferring packets of signal groups from the digital signal processor subsystems to an external component, the interface unit comprising;
a peripheral direct memory access unit, the peripheral direct memory access unit including;
a plurality of first in-first out channel memories; each channel memory coupled to and receiving packets of signal groups from at least one digital signal processor subsystem, and a multiplexer coupled to the channel memories for transmitting signal groups from a location in a channel memory, the channel memory being selected by control signals applied to the multiplexer; and a high level data link controller including;
a FIFO memory receiving signal groups from the multiplexer; and a processor, the processor reading signal groups from the FIFO memory and applying processed signal groups to the external component as a packet, wherein the processor generates an ABORT signal when a signal group is not available for processing in the FIFO memory unit.
- 12. The interface unit as recited in claim 11 wherein the ABORT signal is applied to the digital processor subsystem generating the signal groups being processed by the high level data link controller.
- 13. The interface unit as recited in claim 12 wherein a message is sent to the external component to which the packet is addressed.
- 14. The interface unit as recited in claim 13 wherein the processor generates a FIRST INTERRUPT signal when a signal group is stored in the FIFO memory and a location in the FIFO memory is available for storage, the FIRST INTERRUPT signal causing a next signal group in a packet in the channel memory selected by the control signals to be stored in the FIFO memory unit, the FIFO memory unit continuing to receive signal groups for the packet that caused the ABORT signal.
- 15. The interface unit as recited in claim 14 wherein when the last signal group of a packet is stored in the FIFO memory unit, a second interrupt signal is generated by the processor, the second interrupt signal changing the control signals wherein signal groups from a new channel memory are stored in the FIFO memory.
RELATED APPLICATIONS
[0001] U.S. Patent Application (Attorney Docket Number TI-32603), entitled APPARATUS AND METHOD FOR DISTRIBUTION OF SIGNALS FROM A HIGH LEVEL DATA LINK CONTROLLER TO MULTIPLE DIGITAL SIGNAL PROCESSOR CORES, invented by Patrick J. Smith, Jay B. Reimer, Ramesh A. Iyer, and Henry D. Nguyen, filed on even date herewith and assigned to the assignee of the present Application and U.S. Patent Application (Attorney Docket Number TI-32605), entitled APPARATUS AND METHOD FOR CONTROLLING BLOCK SIGNAL FLOW IN A MULTI DIGITAL SIGNAL PROCESSOR CONFIGURATION FROM A SHARED PERIPHERALDIRECT MEMORY CONTROLLER TO HIGH LEVEL DATA LINK CONTROLLER, invented by Patrick J. Smith, Jay B. Reimer, Ramesh A. Iyer and Henry D. Nguyen, filed on even date herewith and assigned to the assignee of the present Application are related Applications.