Patent Application
20050071823
One or more embodiments of the invention relate generally to the field of segmented addressing model architectures. More particularly, one or more of the embodiments of the invention relate to a method and apparatus for simulating segmented addressing on a flat address model architecture.
Generally, computer programs are initially written in high level program statements. In order to be executed by a computer, the program statements are compiled into machine instructions that a microprocessor can recognize and execute. The machine instructions are selected from a set of machine instructions unique to a particular instruction set architecture (ISA).
Computer program statements that have been decoded into machine instructions for a source ISA such as Intel® X86, may undergo a binary translation in order to be executed at a target ISA, such as a reduced instruction set computing (RISC) architecture, or a very long instruction word (VLIW) architecture.
The translation may be performed by a dynamic translator, typically stored in memory. During translation, instructions are typically translated one basic block of instructions (BB) at a time and stored in memory. For example, each basic block of instructions may include a contiguous sequence of non-branch instructions (i.e., do not change order of executing instructions) which typically ends with a conditional branch instruction.
Unfortunately, some architectures support a segmented addressing model for protection or historical reasons. In a segmented addressing model, the processor represents a logical address with a segment selector. A segment selector includes two sections: a segment identifier and an offset, such as, for example, ds:[0x400000]. This example represents a segmented address used by architectures which support a segmented addressing model in which ds denotes a segment register holding the segment selector and 0x400000 represents an offset. To translate a logical address, such as provided above, into a linear address, segmentation hardware locates the base linear address of a segment by looking up a segment table indexed by the segment selector and then adding the base linear address to the offset.
Unfortunately, running such code with a dynamic binary translator on a flat addressing model architecture is not possible since the architecture does not support the segmented memory model. Accordingly, certain programs that are written according to a segmented addressing model may generally not be translated for execution within an architecture that is limited to a flat memory addressing mode. Therefore, there remains a need to overcome one or more of the limitations in the above-described, existing art.
The various embodiments of the present invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which:
A method and apparatus for simulating segmented addressing on a flat memory model architecture are described. In one embodiment, the method includes the translation of instructions from a source instruction set architecture (ISA) having a segmented memory addressing model into a target ISA having a non-segmented memory addressing model. The conversion of instructions into translated instructions for execution within the target ISA is performed by simulating a segmented memory addressing model within the target ISA for the translated instructions. In one embodiment, hardware components and data structures of the target ISA are allocated to simulate the segmented memory addressing model within the target ISA. Accordingly, translated code utilizes allocated flags, such as predicate registers, in order to convert translated program statements having logical address expressions into linear addressing expressions supported by the target ISA.
In the following description, certain terminology is used to describe features of the invention. For example, the term “logic” is representative of hardware and/or software configured to perform one or more functions. For instance, examples of “hardware” include, but are not limited or restricted to, an integrated circuit, a finite state machine or even combinatorial logical. The integrated circuit may take the form of a processor such as a microprocessor, application specific integrated circuit, a digital signal processor, a micro-controller, or the like.
An example of “software” includes executable code in the form of an application, an applet, a routine or even a series of instructions. The software may be stored in any type of computer or machine readable medium such as a programmable electronic circuit, a semiconductor memory device inclusive of volatile memory (e.g., random access memory, etc.) and/or non-volatile memory (e.g., any type of read-only memory “ROM,” flash memory), a floppy diskette, an optical disk (e.g., compact disk or digital versatile disk “DVD”), a hard drive disk, tape, or the like.
In one embodiment, the present invention may be provided as an article of manufacture which may include a machine or computer-readable medium having stored thereon instructions which may be used to program a computer (or other electronic devices) to perform a process according to one embodiment of the present invention. The computer-readable medium may include, but is not limited to, floppy diskettes, optical disks, Compact Disc Read-Only Memory (CD-ROMs), and magneto-optical disks, Read-Only Memory (ROMs), Random Access Memory (RAMs), Erasable Programmable Read-Only Memory (EPROMs), Electrically Erasable Programmable Read-Only Memory (EEPROMs), magnetic or optical cards, flash memory, or the like.
System Architecture
In one embodiment, memory 140 is volatile memory, including but not limited to, random access memory (RAM), synchronous RAM (SRAM), synchronous dynamic RAM (SDRAM), double data rate (DDR) SDRAM (DDR-SDRAM), Rambus dynamic RAM (RDRAM) or the like. Collectively, MCH 120 and ICH 160 are referred to as chipset 180. As is described herein, the term “chipset” is used in a manner well known to those skilled in the art to describe, collectively, the various devices coupled to CPU 110 to perform desired system functionality. In one embodiment, functionality of one or both MCH 120 and ICH 160 may be implemented within CPU 110.
In contrast to conventional computer systems, computer system 100 includes dynamic binary translator 300 for translating binary applications written for a source instruction set architecture (ISA) into a target instruction set architecture (ISA) of computer system 100. In one embodiment, computer system 100 may be referred to as a very long instruction word (VLIW) architecture. In one embodiment, computer system 100 is configured as an explicitly parallel instruction computing (EPIC) architecture. As described herein, VLIW architectures, EPIC architectures, and the like are collectively referred to herein as a target ISA. In contrast, as described herein, the term “source ISA” may refer to ISAs having instruction words that are smaller that the VLIW architecture capabilities of computer system 100.
In one embodiment, computer system 100 may refer to a computer architecture manufactured by the Intel® Corporation of Santa Clara, Calif., to process, for example, 64-bit, 128-bit, or larger instruction words. In contrast, source ISAs may refer to computer architectures configured to handle 32-bit instruction words. Accordingly, in the embodiments described in further detail below, VLIW instruction set architectures, such as computer system 100, are required to provide compatibility with legacy or source ISAs by translating binary applications of the source ISAs according to a target ISA of computer system 100. In one embodiment, the translation is performed using dynamic binary translator 300.
The source ISA may operate according to a segmented memory addressing model. A segmented memory addressing model divides a processor's addressable memory space (linear address space) into protected address spaces, generally referred to as segments. As a result, memory appears as a group of independent address spaces, or segments, to the devices which access memory. As such, segmentation provides a mechanism for isolating individual code, data and stacks into separate memory segments so that multiple programs or stacks can run on the same processor without interfering with one another.
Accordingly, in response to logical address 210, source ISA utilizes segment selector 212 to identify a segment descriptor 222 within segment table 220. Segment descriptor 222 describes a segment to be accessed by the application or program which issued logical address 210. In response, the source ISA identifies segment base address 224 according to segment descriptor 222. Using base address 224, the base address 224 may be combined with offset 214 to convert logical address 210 into linear address 230. As illustrated, segment base address 224 identifies the start position, or address, of segment 226 within linear address space 202. Likewise, offset 214 provides a location of the desired byte within the segment or linear address space 230.
Unfortunately, as indicated above, computer system 100, which is referred to herein as target ISA 100 may not support segmentation 200, as illustrated with reference to
Accordingly, a binary application such as the untranslated source binary application is typically comprised of multiple blocks of instructions stored in the physical static sequence. In order to execute translated source applications which function according to a segmented addressing model, translator 300 is configured as illustrated with reference to
As illustrated with reference to
In one embodiment, the target registers may include general purpose registers provided by the target ISA 100, which may be stored within chipset 180 or processor 110. Accordingly, in the embodiment illustrated, the segment descriptor or segment described by the segment descriptor, is assigned a target register, which is stored within column 330 of segment table 310. In order to further implement a segmented addressing model, translator 300 maintains source architecture state table 350. However, in contrast to conventional segmentation, target ISA does not provide segment register used by source ISA. Generally, conventional segmentation requires storage of a segment descriptor within a segment register before the segment may be accessed by an application or program.
As illustrated, state table 350 includes various entries for segment registers 350 (352-1, . . . , 352-N). As such, translator 300 maintains a source ISA state instead of allocating segment registers as utilized within conventional segmented addressing models. Unfortunately, the number of allocated segment registers within a source ISA is generally limited to, for example, six segment registers for holding up to six segment selectors. For example, the segment registers may support a specific kind of memory reference, such as code, stack or data.
Accordingly, in the embodiment illustrated, translator 300 allocates an entry within source architecture state table 350 to provide a corresponding entry with respect to each segment register utilized by the source ISA. In one embodiment, when translator 300 detects a segment register update instruction within a source application, translator 300 will identify the corresponding segment descriptor within segment table 310 to identify the assigned target register 330. Once assigned, translator 300 may update a predicate register 362 (362-1, . . . , 362-N) to identify the target register assigned to the segment. Furthermore, at such time, the assigned target register may be populated with a base address of the segment.
In an alternative embodiment, the base address is stored within target register at the time the target register is assigned to the segments described by the segment descriptor 320. In the embodiment illustrated, target ISA uses predicate registers 360, which provide a means for implementing conditional state information within target ISA. However, such state information may be maintained within an allocated data structure provided by the various target ISAs for implementing embodiments of the invention. Accordingly, once translation of a source ISA application is complete, in one embodiment, translator 300 may simulate segmented memory addressing within the target ISA, as illustrated with reference to
As illustrated in
Operation
Once translation of a source ISA application is complete, the source ISA application is executed at process block 450. During execution of the translated instructions, at process block 460 the segmented memory addressing model is simulated within the target ISA for the translated instructions. As illustrated with reference to
At process block 416, a segment descriptor associated with the segment table update instruction is identified. Once the segment descriptor is identified, at process block 418, a segment based address of a segment described by the segment descriptor is determined according to the identified segment descriptor. At process block 420, the segment base address is stored within a target ISA register assigned to the segment described by the identified segment descriptor, for example, as depicted with reference to
Once the target register is identified, at process block 438, a target ISA predicate register assigned to the identified target register is updated to identify the target register containing a base address of the segment register. In other words, in one embodiment, target ISA predicate registers are used by the translated application to provide a mapping between logical addresses contained within the translated application and the target register containing a base address of the segment associated with the logical address. In one embodiment, the mapping between predicate and target registers is illustrated in
Once each base address is loaded, at process block 448, a target ISA predicate register assigned to the corresponding target register loaded with a base address of the corresponding segment is identified. Accordingly, a translated application can identify the target register containing a base address of each segment utilized by a current application thread. In one embodiment, method 440 is repeated each time the translator encounters a segment table update instruction or a segment register update instruction within a source ISA application.
In an alternative embodiment, the mapping between source segment registers and allocated target ISA registers containing a base address of the corresponding segment may be performed utilizing a target ISA data structure or the like to provide the desired mapping. However, as will be recognized by those skilled in the art, predicate registers provide high speed translation between source ISA logical addresses and target ISA linear addresses, as described above. At process block 472, a target register containing a base address of the segment is identified by the identified target predicate register. Once identified, at process block 474, the base address of the segment is added to an offset portion of the logical address to compute a linear address within the target ISA memory model.
In one embodiment, method 462 is performed, as illustrated with reference to
Alternate Embodiments
Several aspects of one implementation of the translator for providing simulation of a segment addressing model have been described. However, various implementations of the translator provide numerous features including, complementing, supplementing, and/or replacing the features described above. Features can be implemented in software or as part of the processor or chipset in different embodiment implementations. In addition, the foregoing description, for purposes of explanation, used specific nomenclature to provide a thorough understanding of the embodiments of the invention. However, it will be apparent to one skilled in the art that the specific details are not required in order to practice the embodiments of the invention.
In addition, although an embodiment described herein is directed to a binary translator, it will be appreciated by those skilled in the art that the embodiments of the present invention can be applied to other systems. In fact, systems for implementing simulation of a memory subdivision methodology for an architecture fall within the embodiments of the present invention, as defined by the appended claims. The embodiments described above were chosen and described in order to best explain the principles of the embodiments of the invention and its practical applications. These embodiments were chosen to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated.
It is to be understood that even though numerous characteristics and advantages of various embodiments of the present invention have been set forth in the foregoing description, together with details of the structure and function of various embodiments of the invention, this disclosure is illustrative only. In some cases, certain subassemblies are only described in detail with one such embodiment. Nevertheless, it is recognized and intended that such subassemblies may be used in other embodiments of the invention. Changes may be made in detail, especially matters of structure and management of parts within the principles of the embodiments of the present invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.
Having disclosed exemplary embodiments and the best mode, modifications and variations may be made to the disclosed embodiments while remaining within the scope of the embodiments of the invention as defined by the following claims.
