Patent Application
20070106873
The present invention relates in general to the field of computers, and, in particular, to addressing devices and memory spaces in a computer system.
Memory and device input/output addressing in computer systems are implemented using a variety of addressing methods which are well known and extensively used. An address may be used to designate a fundamental element of storage, the input/output of a device, or other networked components. Addressing methods and standards may be upgraded over time to reflect many changing needs. These needs may include a growing number of devices, larger memory space or simply a need for more dynamic systems to accurately and rapidly channel data and other control signals to their destinations.
When a new version of an addressing protocol is developed, a long transitional period ensues before it can be fully implemented. This period is necessary to allow for the upgrade of existing devices and other components to become compatible with the new addressing protocol. In some cases, the cost of replacing or redesigning the entire system is prohibitive.
Thus, a mechanism that allows for both older or legacy address protocol and newer versions of the addressing protocol to coexist and communicate within the same system address space is desirable. The legacy address space, which essentially belongs to the older system, continues to remain in use for the reasons enumerated above. In operation, the legacy addresses may then be translated to new addresses. Alternatively, new addresses may be translated to legacy addresses to accommodate upgraded devices within the legacy addressing space. In addition, during the transition period legacy devices may exist on one bus while new devices exist on a second bus. It is therefore important to select for which bus or destination a given address is intended. The present invention addresses these issues.
In one aspect, the invention relates to an apparatus for translating addresses. In one embodiment, the apparatus includes an input port to receive an address of a certain length and a memory unit that is adapted to receive a portion of the input address and output another address of a predetermined length which is mapped to the input. In another embodiment, the apparatus also includes a multiplexer that is adapted to output either the input address or the address which is output by the memory unit depending on the status of a selection line. In yet another embodiment, the status of the selection line is a function of a portion of the input address. The apparatus also includes a destination select line. In still yet another embodiment, the status of the destination select line is determined by a function of a predetermined number of bits of the output from the memory unit and a certain portion of the input address.
In another aspect, the invention relates to a method of translating addresses. In one embodiment, the method includes receiving input addresses of a certain length and performing an operation on a portion of the input address to determine its destination. The method further includes the step of re-mapping input addresses of a certain length into a set of user-defined output addresses of a predetermined length. The operation performed on a portion of the input address is a logic operation to determine the destination of the address.
These and other aspects of this invention will be readily apparent from the detailed description below and the appended drawings, which are meant to illustrate and not to limit the invention and in which:
The apparatus and method for translating addresses will now be described with respect to various embodiments. In this description, like numbers refer to similar elements within various embodiments of the present invention.
Generally, the present invention provides an apparatus and method for translating addresses and routing them to one of at least two destinations. For example the translated addresses may be routed to one of two buses; one having legacy devices and the other having devices responsive to the new addressing protocol. In one embodiment, this is accomplished through the use of a memory unit and logic circuitry that essentially operates as a look-up translation table configurable by software.
An IO address of predetermined length is received on the input IO address bus 102. A part of the IO address, preferably the lower order bits 114 of the input IO address bus 102, is communicated to the input port IA 103 of the memory 104. Input IO address bus 102 is also in communication with two other input ports, 116 and 118 of the multiplexer circuit 106. Finally, another logic IO address bus 119 communicates higher order bits of the input IO address bus 102 to a first input port 120 of the digital logic circuitry 108.
A portion of the memory output bus 122 from the memory 104 through memory Port OA 123 is communicated to a third input port 124 of the multiplexer circuit 106. This portion of the memory output bus 122 is designated as “Port OA address-1” and in one embodiment has the same number of bits as the original input IO address and one less bit than the output port 123 of memory 104. The remaining portion of the memory output bus 122 from Port OA 123 is designated as “Port A IO address-2” and is communicated to the second input port 126 of the digital logic circuitry 108. In one embodiment this corresponds to the highest order bit [32] of the Port OA address space.
In operation, the memory 104 receives the lower order bits 114 of the input IO address from the input IO address bus 102 and translates them, using a translation table described below, into a new address which is then the output on Port OA 123 of the memory 104. In one embodiment the lower order bits 114 of the IO address correspond to the input 102 IO address bits [11:0].
The multiplexer circuit 106 performs an operation 128 on the higher order bits of the input IO address bus 102 at its first input port 116. In various embodiments, the multiplexer circuit 106 selects either the IO address present at its second input port 118 which correspond to IO address bits [31:0] or the “Port OA address-1” present at its third input port 124 in response to the signal from the operation 128. Finally, the multiplexer circuit 106 places on its output port the selected address for transmission on the translated IO address bus 112.
In another embodiment, the digital logic circuitry 108 performs a combination of logic operations on the higher order bits present at its first input port 120 and “Port A address-2” present at its second input port 126. The digital logic circuitry 108 then places an output signal to the destination select line 110 in response to the logic operations.
Referring also to
Referring again to
As a hypothetical example, imagine a scenario in which the length of each IO address is 32 bits wide labeled as [31:0] as shown in
When a new Port OA IO address 212 is written in a data field 204 (i.e., data element of the memory 104), an additional bit 210′ is concatenated to the actual new address 216 to designate destination of the new address. Thus, to remap the original IO address “CF9h”218 which appears on the input IO address bus 102 to new Port A IO address “1,1234_5678h”212, location “CF9h” which is occupied by the initial address “0,0000_OCF9h”220, would be rewritten with new address 212. In this scenario, when the memory sees a request to address “CF9h”, it would replace the original address “CF9h”218 with the translated address “1,1234_5678h” and the digital logic circuitry 108 sends the address 216 to the destination designated by the additional bit 210. In one embodiment, 12 bits are needed for the legacy space addressing. Eight characters of 4 bits each constitutes the new address length of 32 bits. An additional bit is necessary for routing as described above, making the translated address 33 bits long. Thus, the RAM capacity desirable for this scenario is 4k×33 bits (4k=212).
Referring again to
An artisan with ordinary skill in the art will readily recognize the standard function performed by an “OR” gate. Additionally, although the multiplexer circuit 106 is described as consisting of a specific logic gate, the skilled artisan will also readily recognize that the function performed by the “OR” gate 128 in this disclosure may be alternatively performed by an equivalent or a combination of other logic gates.
As indicated above, based on the value in selection line 134, the multiplexer 132 is adapted to select one of its two inputs, the original input IO address 102 or the “Port A address-1” on the second 118 and third 124 input ports of the multiplexer circuit 106, respectively. The selected address is subsequently placed on the translated IO address bus 112.
In accordance with yet another embodiment of the present invention, the digital logic circuitry 108 includes two “OR” gates. Higher order bits [31:12] of the original IO address, at the input port 120 of the digital logic circuitry 108, are input signals to a first “OR” gate 136. “Port A address-2”, at the second input port 126 of the digital logic circuitry 108, is one input to a second “OR” gate 138 which combines with the output of the first “OR” gate 136 to produce another output that is designated as the destination select signal 110. Again an artisan skilled in the art will readily recognize that the function performed by the combination of logic gates in the digital logic circuitry 108 may be alternatively performed by an equivalent or a combination of other logic gates.
The use of this destination select line is best understood with reference to
The input signals to the translation table 300 are preferably the lower order bits 114 of the original input IO address. The translation table 300 then performs the conversion of addresses to new addresses and concatenates an additional bit 210″. The additional bit 302 is used to designate the destination of the translated address. The additional bit 210″ is concatenated during the initialization period of the RAM. If the value of the additional bit is 1, the destination of the address is the PCI Express bus 304, otherwise the destination is the decoder circuit 306 and then the LPC bus 308 or a legacy device 310.
Those skilled in the art will recognize the many benefits and advantages afforded by the present invention. The invention enables the translation of addresses and also includes the additional ability to reroute them to one of at least two destinations.
While the invention has been particularly shown and described with references to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.
