Claims
- 1. A method of displaying images on a computer graphics system by encoding and decoding plural bit control data input to a decode logic circuit included therein, comprising the steps of:
- converting, by said decode logic circuit, a first bit from the plural bit control data into a class bit for defining plural subsets of said plural bit control data;
- designating a second bit of said plural bit control data as a control bit field to control a reset operation, the validity of said control bit field being dependent upon said class bit;
- controlling a window identification operation by outputting a first class of values, corresponding to one of the plural subsets, wherein said class bit indicates that said second bit is valid and a reset operation may be implemented; and
- controlling said window identification operation by outputting a second class of values, corresponding to another one of the plural subsets, wherein said class bit indicates that said second bit is invalid and a reset operation may not be implemented.
- 2. The method according to claim 1 further comprising a step of:
- outputting from said decode logic circuit a greater number of bits to control the first operation and the second operation than are input to said decode logic circuit by said plural bit control data.
- 3. A method of displaying images on a computer graphics system by encoding and decoding plural bit control data, input to a decode logic circuit, comprising the steps of:
- controlling a class designation operation to indicate whether simultaneous reset of attribute data is provided for pixels in an attribute buffer in said computer graphics system by converting a first bit of said plural bit control data;
- outputting a first subset of the plural bit control data from said decode logic circuit to control a window identification operation, said first subset being of a first class including said first bit and being dependent upon a value thereof to indicate that simultaneous reset of the attribute data is provided, said first subset being configured as an ordered n-tuple;
- outputting a second subset of the plural bit control data from said decode logic circuit to control said window identification operation, said second subset being of a second class including said first bit and being dependent upon the value thereof to indicate that simultaneous reset of the attribute data is not provided, said second subset being configured as an ordered n-tuple;
- designating, as one control value for controlling a reset operation, a second bit of the plural bit control data of the subset which has a predetermined position in the ordered n-tuple; and
- setting one binary value at a position other than said predetermined position in the ordered n-tuple of the subset and outputting a signal from said decode logic circuit to indicate reset of the attribute data in the attribute buffer only when said first bit is of a predetermined value.
- 4. The method according to claim 3 further comprising steps of:
- determining a second subset of the plural bit control data having the another binary value at the same predetermined position in the ordered n-tuple; and
- identifying, as an individual control value for controlling the operation, each of the positions of the ordered n-tuple of the second subset.
- 5. The method according to claim 3 further comprising steps of:
- storing, in a frame buffer, image data for each pixel being displayed on a display screen;
- storing attribute data for each pixel in the attribute; and
- storing the plural bit control data for each pixel in a control buffer to control the operation by the computer graphical system.
- 6. The method according to claim 3 wherein the attribute data is a depth value and the attribute buffer is configured as a Z-buffer for storing the depth value to display a three-dimensional representation of an image on a two-dimensional display screen.
- 7. The method according to claim 3 wherein the attribute data is a multiplicand data for use in blending colors for a pixel and the attribute buffer is configured as an alpha buffer for storing the multiplicand data.
- 8. The method according to claim 3 wherein the control value is a window ID and the operation is to display an independent window on a display screen.
- 9. The method according to claim 3 wherein the predetermined position in said ordered n-tuple is the second least significant bit filed in the plural bit control data and a binary one at the least significant bit field in the ordered n-tuple of the subset indicates reset of the attribute data for a pixel in the attribute buffer.
- 10. The method according to claim 3 wherein the predetermined position in said ordered n-tuple is the third least significant bit field in the plural bit control data and a binary one in the least significant bit field and a binary one in the second least significant bit field in the ordered n-tuple of the subset indicate reset of two different attribute data for a pixel independently.
- 11. An apparatus, included within a computer graphics system, for encoding and decoding plural bit control data input to a decode logic circuit included within said computer graphics system, comprising:
- means for converting, by said decode logic circuit a first bit from the plural bit control data into a class bit for defining plural subsets of said plural bit control data;
- means for designating a second bit of said plural bit control data as a control bit field to control a reset operation, the validity of said control bit field being dependent upon said class bit;
- means for controlling a window identification operation by outputting, from said decode logic circuit, a first class of control values corresponding to one of the plural subsets, wherein said class bit indicates that said second bit is valid and a reset operation may be implemented; and
- means for controlling said window identification operation by outputting a second class of values, corresponding to another one of the plural subsets, wherein said class bit indicates that said second bit is invalid and a reset operation may not be implemented.
- 12. The apparatus according to claim 11 further comprising:
- means for outputting from said decode logic circuit a greater number of bits to control first operation and the second operation than are input to said decode logic circuit by plural bit control data.
- 13. An apparatus, included within a computer graphics system, for encoding and decoding plural bit control data, input to a decode logic circuit, comprising:
- means for controlling a class designation operation to indicate whether simultaneous reset of attribute data is provided for pixels in an attribute buffer in said computer graphics system by converting a first bit of said plural bit control data
- means for outputting a first subset of the plural bit control data from said decode logic circuit to control a window identification operation, said first subset being of a first class including said first bit for and being dependent upon a value thereof to indicate that simultaneous reset of the attribute data is provided, said first subset being configured as an ordered n-tuple;
- means for outputting a second subset of the plural bit control data from said decode logic circuit to control said windows identification operation, said second subset being of a second class including said first bit and being dependent upon the value thereof to indicate that simultaneous reset of the attribute data is not provided, said second subset being configured as an ordered n-tuple;
- means for designating, as one control value for controlling a reset operation, a second of the plural bit control data of the subset which has a predetermined position in the ordered n-tuple; and
- means for setting one binary value at a position other than said predetermined position in the ordered n-tuple of the subset and outputting a signal from said decode logic circuit to indicate reset of the attribute data in the attribute buffer only when said first bit is of a predetermined value.
- 14. The apparatus according to claim 13 further comprising:
- means for determining a second subset of the plural bit control data having another binary value at the same predetermined position in the ordered n-tuple; and
- means for identifying, as an individual control value for controlling the operation, each of the positions of the ordered n-tuple data of the second subset.
- 15. The apparatus according to claim 13 further comprising:
- means for storing, in a frame buffer, image data for each pixel being displayed on a display screen;
- means for storing attribute data for each pixel in the attribute buffer; and
- mean for storing the plural bit control data for each pixel in a control buffer to control the operation by the computer graphics system.
- 16. The apparatus according to claim 13 wherein the attribute data is a depth value and the attribute buffer is configured as a Z-buffer for storing the depth value to display a three-dimensional representation of an image on a two-dimensional display screen.
- 17. The apparatus according to claim 13 wherein the attribute data is a multiplicand data for use in blending colors for a pixel and the attribute buffer is configured as an alpha buffer for storing the multiplicand data.
- 18. The apparatus according to claim 13 wherein the control value is a window ID and the operation is to display an independent window on a display screen.
- 19. The apparatus according to claim 13 wherein the predetermined position in said ordered n-tuple is the second least significant bit field in the plural bit control data and a binary one at the least significant bit field in the ordered n-tuple of the subset indicates rest of the attribute data for a pixel in the attribute buffer.
- 20. The apparatus according to claim 13 wherein the predetermined position in said ordered n-tuple is the third least significant bit field in the bit control data and a binary one in the least significant bit field and a binary one in the second least significant bit field in the ordered n-tuple of the subset indicate reset of two different attribute data for a pixel independently.
Parent Case Info
This is a continuation of application Ser. No. 07/870,171 filed Apr. 16, 1992, abandoned which is a continuation of application Ser. No. 07/475,462 filed Feb. 5, 1990, abandoned.
US Referenced Citations (19)
Foreign Referenced Citations (5)
Number |
Date |
Country |
0157912 |
Dec 1979 |
EPX |
0330007 |
Feb 1989 |
EPX |
0397995 |
Mar 1990 |
EPX |
62-42279 |
Feb 1987 |
JPX |
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Non-Patent Literature Citations (2)
Entry |
IBM-Technical Disclosure Bulletin, "Video Data Path in Color Raster Displays with Variable Pixel Data Structure", vol. 28, No. 11, Apr. 1986, L. Lumelsky, 4890-4893. |
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Continuations (2)
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Number |
Date |
Country |
Parent |
870171 |
Apr 1992 |
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Parent |
475462 |
Feb 1990 |
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