Patent Application
20250139488
This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0148279 filed in the Korean Intellectual Property Office on 31 Oct. 2023, the entire contents of which are incorporated herein by reference.
The present disclosure relates to a logical operation technology, and more particularly, to an apparatus and a method of implementing a logical Hadamard operation using a boundary flip and a transformation of the subsequent measurement.
A quantum computing device may be a computing device that processes data by using phenomena related to quantum mechanics such as quantum entanglement, quantum superposition, etc. The quantum entanglement may mean a state in which two or more states are quantally connected to each other, so that they cannot be handled separately in each state. The quantum superposition may mean that various result states by measurement are simultaneously present probabilistically before measuring the quantum state. The quantum computing device can use a qubit as a basic unit of information for processing data by using a phenomenon related to the quantum dynamics.
The qubit may simultaneously express values corresponding to various bits by using the quantum superposition state. For example, the qubit may express respective values as probabilities such as ‘0 with a probability of 20% and 1 with a probability of 80%’. The qubit may be determined as one state while the quantum superposition state is released when being observed.
In order to overcome difficulty in implementing quantum computing and quantum information communication due to noise or an error for quantum information, a surface code and a concatenated code are being studied as a quantum error correcting code.
The surface code can have a larger threshold for an error rate requested for a physical qubit than the concatenated code in order for the quantum error correction code to efficiently operate, and can be utilized as the quantum error correction code in the future.
Proposed is a method of implementing a logical operation utilizing a joint measurement in a quantum computer architecture that encodes the physical qubit with the surface code. In addition, a study for efficiently implementing the logical operation utilizing the joint measurement is continued.
The present disclosure is contrived in response to the above-described background, and has been made in an effort to provide an apparatus and a method of implementing a logical Hadamard operation using a boundary flip and a transformation of the subsequent measurement.
Technical objects of the present disclosure are not restricted to the technical object mentioned as above. Other unmentioned technical objects will be apparently appreciated by those skilled in the art by referencing the following description.
An exemplary embodiment of the present disclosure provides a method for a logical operation performed by a quantum computing device, which may include: acquiring a logical qubit in which a physical qubit is encoded with a surface code; when performing a logical Hadamard operation in the logical qubit, and performing a first operation using a first joint measurement, performing a boundary flip; performing the first operation by using a second joint measurement other than the first joint measurement in the boundary-flipped logical qubit; and changing an order of the logical Hadamard operation after a step of performing the first operation by using the second joint measurement.
Alternatively, an X boundary may be a boundary constituted by an X stabilizer included in the logical qubit, and a Z boundary may be a boundary constituted by a Z stabilizer included in the logical qubit.
Alternatively, the performing of the first operation by using the second joint measurement other than the first joint measurement in the boundary-flipped logical qubit may include performing a joint XZ measurement which is the second joint measurement other than a joint ZZ measurement which is the first joint measurement in the boundary-flipped logical qubit when the first operation is logical CNOT.
Alternatively, the performing of the first operation by using the second joint measurement other than the first joint measurement in the boundary-flipped logical qubit may include performing a joint ZX measurement which is the second joint measurement other than a joint XX measurement which is the first joint measurement in the boundary-flipped logical qubit when the first operation is patch extension.
Alternatively, the performing of the first operation by using the second joint measurement other than the first joint measurement in the boundary-flipped logical qubit may include performing a joint XY measurement which is the second joint measurement other than a joint ZY measurement which is the first joint measurement in the boundary-flipped logical qubit when the first operation is a logical S operation.
Alternatively, the performing of the first operation by using the second joint measurement other than the first joint measurement in the boundary-flipped logical qubit may include performing a joint ZX and XY measurement which is the second joint measurement other than a joint ZZ and ZY measurement which is the first joint measurement in the boundary-flipped logical qubit when the first operation is a logical T operation.
Alternatively, the method may further include: when there is a second operation using a third joint measurement subsequent to the changed order of the logical Hadamard operation, performing the boundary flip in the logical qubit in which the first operation is performed; performing the second operation by using a fourth joint measurement other than the third joint measurement in the logical qubit in which the boundary flip and the first operation are performed; and changing the order of the logical Hadamard operation after a step of performing the second operation by using the fourth joint measurement.
Alternatively, the method may further include, when there is a single measurement subsequent to the changed order of the logical Hadamard operation, merging the logical Hadamard operation and the single measurement to change a basis which measures the logical qubit in which the first operation is performed in the single measurement.
Alternatively, the changing of the basis which measures the logical qubit in which the first operation is performed in the single measurement may include, when the basis which measures in the single measurement is an X basis, changing the basis which measures the logical qubit in the single measurement to a Z basis by merging the logical Hadamard operation and the single measurement.
Alternatively, the changing of the basis which measures the logical qubit in which the first operation is performed in the single measurement may include, when the basis which measures in the single measurement is the Z basis, changing the basis which is measured in the single measurement to the X basis by merging the logical Hadamard operation and the single measurement.
Another exemplary embodiment of the present disclosure provides a non-transitory computer-readable medium including a computer program, wherein the computer program allows a processor of a quantum computing device to perform a method for a logical operation, in which the method may include: acquiring a logical qubit in which a physical qubit is encoded with a surface code; when performing a logical Hadamard operation in the logical qubit, and performing a first operation using a first joint measurement, performing a boundary flip of replacing an X boundary included in the logical qubit with a Z boundary, and replacing the Z boundary with the X boundary; performing the first operation by using a second joint measurement other than the first joint measurement in the boundary-flipped logical qubit; and changing an order of the logical Hadamard operation after a step of performing the first operation by using the second joint measurement.
Yet another exemplary embodiment of the present disclosure provides a quantum computing device for a logical operation, including: a processor; and a memory, in which the processor may perform an operation of acquiring a logical qubit in which a physical qubit is encoded with a surface code, when performing a logical Hadamard operation in the logical qubit, and performing a first operation using a first joint measurement, an operation of performing a boundary flip of replacing an X boundary included in the logical qubit with a Z boundary, and replacing the Z boundary with the X boundary, an operation of performing the first operation by using a second joint measurement other than the first joint measurement in the boundary-flipped logical qubit, and an operation of changing an order of the logical Hadamard operation after a step of performing the first operation by using the second joint measurement.
According to an exemplary embodiment of the present disclosure, a boundary flip, and a transformation of the subsequent measurement is used to perform a logical Hadamard operation with small time and space costs.
Effects which can be acquired in the present disclosure are not limited to the aforementioned effects and other unmentioned effects will be clearly understood by those skilled in the art from the following description.
Various aspects are now described with reference to the drawings and like reference numerals are generally used to designate like elements. In the following exemplary embodiments, for purposes of explanation, numerous specific details are set forth to provide a comprehensive understanding of one or more aspects. However, it will be apparent that the aspect(s) can be executed without the detailed matters.
Various exemplary embodiments will now be described with reference to drawings. In this specification, various descriptions are presented to provide appreciation of the present disclosure. However, it is apparent that the exemplary embodiments can be executed without the specific description.
“Component”, “module”, “system”, and the like which are terms used in the specification refer to a computer-related entity, hardware, firmware, software, and a combination of the software and the hardware, or execution of the software. For example, the component may be a processing executed on a processor, the processor, an object, an execution thread, a program, and/or a computer, but is not limited thereto. For example, both an application executed in a computing device and the computing device may be the components. One or more components may reside within the processor and/or an execution thread. One component may be localized in one computer. One component may be distributed between two or more computers. Further, the components may be executed by various computer-readable media having various data structures, which are stored therein. The components may perform communication through local and/or remote processing according to a signal (for example, data transmitted from another system through a network such as the Internet through data and/or a signal from one component that interacts with other components in a local system and a distribution system) having one or more data packets, for example.
In addition, the term “or” is intended to mean not exclusive “or” but implicit “or”. That is, when not separately specified or not clear in terms of a context, a sentence “X uses A or B” is intended to mean one of the natural inclusive replacements. That is, the sentence “X uses A or B” may be applied to any of the case where X uses A, the case where X uses B, or the case where X uses both A and B. Further, it should be understood that the term “and/or” used in this specification designates and includes all available combinations of one or more items among enumerated related items.
Further, it should be appreciated that the term “comprise” and/or “comprising” means presence of corresponding features and/or components. However, it should be appreciated that the term “comprises” and/or “comprising” means that presence or addition of one or more other features, components, and/or a group thereof is not excluded. Further, when not separately specified or it is not clear in terms of the context that a singular form is indicated, it should be construed that the singular form generally means “one or more” in this specification and the claims.
In addition, the term “at least one of A or B” should be interpreted to mean “a case including only A”, “a case including only B”, and “a case in which A and B are combined”.
Those skilled in the art need to recognize that various illustrative logical blocks, configurations, modules, circuits, means, logic, and algorithm steps described in connection with the exemplary embodiments disclosed herein may be additionally implemented as electronic hardware, computer software, or combinations of both sides. To clearly illustrate the interchangeability of hardware and software, various illustrative components, blocks, configurations, means, logic, modules, circuits, and steps have been described above generally in terms of their functionalities. Whether the functionalities are implemented as the hardware or software depends on a specific application and design restrictions given to an entire system. Skilled artisans may implement the described functionalities in various ways for each particular application. However, such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The description of the presented exemplary embodiments is provided so that those skilled in the art of the present disclosure use or implement the present disclosure. Various modifications to the exemplary embodiments will be apparent to those skilled in the art. Generic principles defined herein may be applied to other exemplary embodiments without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the exemplary embodiments presented herein. The present disclosure should be analyzed within the widest range which is coherent with the principles and new features presented herein.
In the present disclosure, terms represented by N-th such as first, second, or third are used for distinguishing at least one entity. For example, entities expressed as first and second may be the same as each other or different from each other.
In addition, the term “etc.” such as “A, B, etc.” should be interpreted to mean “a case including only A”, “a case including only B”, and “a case in which A and B are combined”.
A configuration of the quantum computing device illustrated in
Referring to
The quantum computing device 100 may include a processor 110, a memory 130, and a network unit 150. The processor 110 may be constituted by one or more cores and may include processors for data analysis and quantum processing, which include a central processing unit (CPU), a general purpose graphics processing unit (GPGPU), a tensor processing unit (TPU), and the like of the computing device. The processor 110 may generally control an overall operation of the quantum computing device 100. For example, the processor 110 may process signals, data information, etc., input or output through components included in the quantum computing device 100. As another example, the processor 110 may read a computer program stored in the memory 130 to perform the quantum processing according to an exemplary embodiment of the present disclosure. The processor 110 may perform a calculation by using quantum mechanical physical phenomena such as indexing information expression of quantum superposition and a parallel operation using quantum entanglement.
According to some exemplary embodiments of the present disclosure, the memory 130 may store any type of information generated or determined by the processor 110 or any type of information received by the network unit 150.
According to some exemplary embodiments of the present disclosure, the memory 130 may include at least one type of storage medium of a flash memory type storage medium, a hard disk type storage medium, a multimedia card micro type storage medium, a card type memory (for example, an SD or XD memory, or the like), a random access memory (RAM), a static random access memory (SRAM), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), a programmable read-only memory (PROM), a magnetic memory, a magnetic disk, and an optical disk. The quantum computing device 100 may operate in connection with a web storage performing a storing function of the memory 130 on the Internet. The description of the memory is just an example and the present disclosure is not limited thereto. The network unit 150 according to some exemplary embodiments of the present disclosure may include an arbitrary wired/wireless communication network that may transmit/receive arbitrary type data and signals. The techniques described in this specification may also be used in other networks in addition to the aforementioned networks.
Steps illustrated in
In the present disclosure, specific methodologies and definitions related to lattice surgery and the joint measurement are disclosed in a thesis and the thesis (Horsman, C., Fowler, A. G., Devitt, S., Van Meter, R.: Surface code quantum computing by lattice surgery. New Journal of Physics 14(12), 123011 (2012)) is incorporated herein by reference.
In the present disclosure, a logical qubit in which a physical qubit is encoded with the surface code may perform any quantum circuit desired by a user to be fault-tolerant (that is, while correcting the error) through at least one quantum gate (e.g., a logical-unit universal gate set, etc.). The universal gate set may include Pauli, CNOT, Hadamard (H), and Phase (S) operations as a Clifford operation, and a Phase (T) operation which is non-Clifford operation.
In the present disclosure, the quantum circuit may include at least one qubit, at least one quantum gate acting on at least one qubit, and/or a measurement.
In the present disclosure, the qubit (e.g., a physical qubit, a logical qubit, etc.) may be a basic unit of information for processing data using a phenomenon related to quantum mechanics. The qubit may simultaneously express values corresponding to various bits by using the quantum superposition state. For example, the qubit may express respective values as probabilities such as ‘0 with a probability of 20% and 1 with a probability of 80%’. The qubit may be determined as one state while the quantum superposition (entangled) state is released when being measured (observed). For example, the qubit starts in a basis state indicating a state of |0 or |1
, and may show a state changed by a quantum gate. In addition, the qubit may be determined as the state of |0
or |1
when being measured (observed). The qubit may be expressed by a 2-dimensional vector.
In the present disclosure, the quantum computing device 100 may initialize the qubit or prepare the qubit in a specific state by using various methods (e.g., using the quantum gate, etc.).
In the present disclosure, at least one quantum gate may be an element indicating an operation applied to the qubit in the quantum computer. At least one quantum gate may convert the quantum state of the qubit.
At least one quantum gate may be operated by a matrix multiplication of complex vectors. At least one quantum gate may include a Hadamard gate, a Pauli gate, a Phase shift gate (e.g., an S gate, a T gate, etc.), a CNOT gate, etc.
The Hadamard gate may be a gate that makes the state of the qubit which is the state of |0 or |1
into a superposition state in which |0
and |1
are simultaneously present. A logic symbol of the Hadamard gate may be
in the quantum circuit. A matrix equation of the Hadamard gate may be
A Hadamard operation H may be an operation that converts an X basis into a Z basis. Further, the Hadamard operation H may be an operation that converts the Z basis into the X basis.
The Phase shift gate may be a gate that changes a phase of the qubit. The Phase shift gate may include an S gate, a T gate, etc.
The S gate may be a gate that performs an operation of bringing a phase change of 90 degrees to the qubit. A logic symbol of the S gate may be in the quantum circuit. A matrix equation of the S gate may be
i may be the imaginary unit.
S† An S† gate may be a gate that exchanges a row and a column of the matrix in the S gate. A logic symbol of the S† gate may be in the quantum circuit.
The T gate may be a gate that performs an operation of bringing a phase change of 45 degrees to the qubit. A logic symbol of the T gate may be in the quantum circuit. A matrix equation of the T gate may be
i may be the imaginary unit. eiπ/4 as a complex number calculated according to the Euler's formula may be a complex number corresponding to an angle of 45 degrees on a complex plane.
The CNOT gate may be a gate that makes two qubits to the entangled state.
The CNOT gate may be a gate that performs a NOT gate operation for a second qubit (target qubit) when a first qubit (control qubit) is |1. A logic symbol of the CNOT gate may be
in the quantum circuit. ● may be the control qubit and ⊕ may be the target qubit. A matrix equation of the CNOT gate may be
The measurement may be a process of separating the state of the qubit into one of the basis states, and obtaining a measurement result through the separated state. For example, the processor 110 performs the measurement for the state of the qubit in the X or Z basis state in the quantum circuit to obtain the state of |0 or |1
. When the measured state of the qubit is the state of |0
, the processor 110 may determine the corresponding state as 0 as a classical bit. When the measured state of the qubit is the state of |1
, the processor 110 may determine the corresponding state as 1 as the classical bit. A symbol of the measurement may be
in the quantum circuit.
In the present disclosure a symbol d may mean a distance of the surface code. In the present disclosure, |0 may represent a physical qubit which is in a 0 state.
In the present disclosure, |+ may represent a physical qubit which is in a + state.
In the present disclosure, |0L may represent a physical qubit which is in the 0 state.
In the present disclosure, |+L may represent a physical qubit which is in the + state.
In the present disclosure, |YL may represent a magic state used in the S operation. For example, |Y
L may be (|0
+|1
)/√{square root over (2)}.
In the present disclosure, |AL may represent a magic state used in the T operation. For example, |A
L may be (|0
+eiπ/4|1
)/√{square root over (2)}.
In the present disclosure, a time cost may mean the number of surface code cycles used for the operation in order to correct a measurement error.
In the present disclosure, a space cost may mean the number of physical qubits used for performing the operation.
In the present disclosure, a space-time cost may mean a product of the space cost and the time cost.
According to an exemplary embodiment of the present disclosure, the processor 110 of the quantum computing device 100 may arrange a data patch in which information is stored and computed, and a first ancilla patch consumed during a logical operation process at a predetermined first interval.
The predetermined first interval is not limited to a specific value, and may be variously set according to a situation.
The data patch may correspond to a first logical qubit in which a first physical qubit is encoded with the surface code.
The first ancilla patch may correspond to a second logical qubit in which a second physical qubit is encoded with the surface code.
Each of the first logical qubit and the second logical qubit may include a data qubit storing logical information, an X stabilizer formed at one side of the data qubit, and a Z stabilizer formed at the other side of the data qubit.
The stabilizer may be a group of a series of quantum operators (Hermit operators) that describe a state of a quantum bit. The group of the quantum operators may be used to represent the state of the quantum bit in a quantum state space.
The X stabilizer may mean a quantum operator group including an X operator. The X operator may be an operator that rotates the state of the qubit around an X axis. The X operator may perform an operation of inverting the state of the qubit.
The Z stabilizer may mean a quantum operator group including a Z operator. The Z operator may be an operator that rotates the state of the qubit around a Z axis.
The Z operator may perform an operation of changing the state of the qubit.
Each of the X stabilizer and the Z stabilizer may include a measurement qubit.
The processor 110 may arrange a first logical ancilla qubit between the data patch and the first ancilla patch (220).
The processor 110 may arrange a second logical ancilla qubit to have a predetermined distance from one side of the first ancilla patch (230). The predetermined distance is not limited to a specific value, and may be variously set according to a situation.
In the present disclosure, a logical ancilla qubit (e.g., a first logical ancilla qubit, a second logical ancilla qubit, a third logical ancilla qubit, etc.) may be a qubit added to achieve a specific target in calculation. For example, the logical ancilla qubit may be a qubit placed for the logical operation.
The processor 110 may perform the joint measurement by using the data patch and the first ancilla patch (240).
As described above, specific methodologies and definitions related to the joint measurement are disclosed in a thesis and the thesis (Horsman, C. Fowler, A. G., Devitt, and S. Van Meter, R.: Surface code quantum computing by lattice surgery. New Journal of Physics 14(12), 123011 (2012)) is incorporated herein by reference.
In an exemplary embodiment, the processor 110 may perform a logical S operation in the data patch by performing a joint ZY measurement in the data patch and the first ancilla patch. For example, the processor 110 may initialize the first ancilla patch to the 0 state. The processor 110 may initialize the first logical ancilla qubit to the + state. The processor 110 may initialize the second logical ancilla qubit to the 0 state. The processor 110 may perform the joint ZY measurement to the data patch and the first ancilla patch by using the stabilizer between the data patch and the first ancilla patch.
In an exemplary embodiment, the processor 110 may perform a logical SH operation in the data patch by performing a joint XY measurement in the data patch and the first ancilla patch. For example, the processor 110 may initialize the first ancilla patch to the 0 state. The processor 110 may initialize the second logical ancilla qubit to the 0 state. The processor 110 may perform the joint XY measurement to the data patch and the first ancilla patch by using the stabilizer between the data patch and the first ancilla patch.
In an exemplary embodiment, the processor 110 may place a second ancilla patch at a location which is not duplicated with the first ancilla patch at a predetermined second interval from the data patch.
The processor 110 may arrange a third logical ancilla qubit between the data patch and the second ancilla patch.
The processor 110 may perform a logical T operation in the data patch by performing a joint ZZ & ZY measurement in the data patch, the first ancilla patch, and the second ancilla patch.
For example, the processor 110 may initialize the first ancilla patch to the 0 state. The processor 110 may prepare the second ancilla patch in a predetermined magic state. The predetermined magic state may be |AL. The processor 110 may initialize the first logical ancilla qubit and the third logical ancilla qubit to the + state. The processor 110 may initialize the second logical ancilla qubit to the 0 state. The processor 110 may perform the joint ZZ & ZY measurement to the data patch, the first ancilla patch, and the second ancilla patch by using ‘the stabilizer between the data patch and the first ancilla patch’ and ‘the stabilizer between the data patch and the second ancilla patch’.
Hereinafter, a detailed description of the configuration, step, etc., described above with reference to
Referring to
Referring to
Performing each of a parity measurement circuit 420 of the X stabilizer and a parity measurement circuit 440 of the Z stabilizer may be completed within 8 steps including a process of initializing the measurement qubit to |0. A time required for an operation of the circuit to be completed may be defined as one surface code cycle. A parity of the stabilizer may have a value of +1 or −1 according to a Z basis measurement result of the measurement qubit. When the parity of the stabilizer has the value of +1 according to the measurement result, the quantum computing device 100 may determine the case as the 0 state. When the parity of the stabilizer has the value of −1 according to the measurement result, the quantum computing device 100 may determine the case as the 1 state.
Referring to when there are a first logical qubit 511 and a second logical qubit 512 which are in any state. The quantum computing device 100 may initialize a second logical ancilla qubit 514 to |0
.
The quantum computing device 100 may generate an integrated logical qubit 520 by turning on (activating) a stabilizer between the first logical qubit 511 and the second logical qubit 512. The quantum computing device 100 may perform the joint ZY measurement in the first logical qubit 511 and the second logical qubit 512 by using the integrated logical qubit 520. The quantum computing device 100 multiplies all parities of a stabilizer 521 that determines a joint ZY measurement result among newly operating stabilizers to acquire a result of the joint ZY measurement. The parities of the stabilizer 521 may be acquired by using a parity measurement circuit 540 corresponding to the execution order. In order to complement the measurement error, a total of 1d cycle may be consumed for the joint ZY measurement. The stabilizer 521 that determines the joint ZY measurement result may be predetermined.
A 4-qubit twist defect 530 may be a stabilizer in which X, and Z and Y are mixed. An execution order of a measurement circuit of the 4-qubit twist defect 530 may be represented with the arrow in the 4-qubit twist defect 530.
The execution order of the measurement circuit of the 4-qubit twist defect 530 may be predetermined by considering an order of surrounding X and Z stabilizers.
Since the parity measurement circuit 540 is completed within 8 steps, a less time may be required than a parity measurement circuit of a 5-qubit twist defect proposed in a conventional thesis (Litinski, Daniel, and Felix von Oppen. “Lattice surgery with a twist: simplifying clifford gates of surface codes.” Quantum 2 (2018): 62).
The quantum computing device 100 may initialize a second logical ancilla qubit 613 to |0 when there are a first logical qubit 611 and a second logical qubit 612 which are in any state.
The quantum computing device 100 may generate an integrated logical qubit 620 by turning on (activating) a stabilizer between the first logical qubit 611 and the second logical qubit 612. The quantum computing device 100 may perform the joint XY measurement in the first logical qubit 611 and the second logical qubit 612 by using the integrated logical qubit 620. The quantum computing device 100 multiplies all parities of a stabilizer 621 that determines a joint XY measurement result among newly operating stabilizers to acquire a result of the joint XY measurement. The parities of the stabilizer 621 may be acquired by using a parity measurement circuit 640 corresponding to the execution order. In order to complement the measurement error, a total of 1d cycle may be consumed for the joint XY measurement. The stabilizer 621 that determines the joint XY measurement result may be predetermined.
A 4-qubit twist defect 630 may be a stabilizer in which X, and Z and Y are mixed. An execution order of a measurement circuit of the 4-qubit twist defect 630 may be represented by the arrow within the 4-qubit twist defect 630. The execution order of the measurement circuit of the 4-qubit twist defect 630 may be predetermined by considering an order of surrounding X and Z stabilizers.
Since the parity measurement circuit 640 is completed within 8 steps, a less time may be required than a parity measurement circuit of a 5-qubit twist defect proposed in a conventional thesis (Litinski, Daniel, and Felix von Oppen. “Lattice surgery with a twist: simplifying clifford gates of surface codes.” Quantum 2 (2018): 62).
Since the joint ZZ measurement and the joint ZY measurement are commutable operations, the joint ZZ measurement and the joint ZY measurement may be performed simultaneously.
The quantum computing device 100 may generate an integrated logical qubit 820 by turning on (activating) a stabilizer which is present between logical qubits when performing the joint ZZ & ZY measurement for three logical qubits 811, 812, and 813 which are in any state from the top. The quantum computing device 100 may perform the joint ZZ & ZY measurement in three logical qubits 811, 812, and 813 by using the integrated logical qubit 820.
The quantum computing device 100 multiplies all parities of a stabilizer 821 that determines the joint ZZ measurement result among newly operating stabilizers to acquire a result of the joint ZZ measurement. The stabilizer 821 that determines the joint ZZ measurement result may be predetermined.
The quantum computing device 100 multiplies all parities of a stabilizer 822 that determines a joint ZY measurement result among newly operating stabilizers to acquire a result of the joint ZY measurement. The stabilizer 822 that determines the joint ZY measurement result may be predetermined.
During a repeatedly performed process in order to complement the measurement error, a total of 1d cycle may be consumed for the joint ZY measurement.
Referring to L which is to perform the logical S operation. A first ancilla patch 912 may be |0
L. Alternatively, the first ancilla patch 912 may be prepared as |0
L (may be initialized).
The quantum computing device 100 may generate an integrated logical qubit 930 by turning on (activating) a stabilizer between the first logical qubit 921 corresponding to the data patch 911 and the second logical qubit 922 corresponding to the first ancilla patch 912.
The quantum computing device 100 may perform the joint ZY measurement in the first logical qubit 921 and the second logical qubit 922 by using the integrated logical qubit 930.
The quantum computing device 100 multiplies all parities of a stabilizer 931 that determines a joint ZY measurement result among newly operating stabilizers to acquire a result of the joint ZY measurement.
The quantum computing device 100 may measure a qubit which is present in a first region 941 as the Z basis and a qubit which is present in a second region 942 as the X basis in an integrated logical qubit 940. After measurement is completed, the second logical qubit 922 corresponding to the first ancilla patch 912 may be consumed during the operation process, and only a logical qubit 950 corresponding to an operation result may be present.
In the logical S operation performing process according to an exemplary embodiment of the present disclosure, a total of 1d cycle may be consumed.
Referring to when there are a first logical qubit 1010 and a second logical qubit 1020 which are in any state. The quantum computing device 100 may initialize a second logical ancilla qubit 1040 to |0
.
The quantum computing device 100 may generate an integrated logical qubit 1050 by turning on (activating) a stabilizer between the first logical qubit 1010 and the second logical qubit 1020. The quantum computing device 100 may perform the joint ZY measurement in the first logical qubit 1010 and the second logical qubit 1020 by using the integrated logical qubit 1050.
The logical S operation is characterized in changing the X operation to Y and changing the Z operation to Z, and when the stabilizer illustrated in
Referring to L which is to perform the logical SH operation. A first ancilla patch 1112 may be |0
L. Alternatively, the first ancilla patch 1112 may be prepared as |0
L (may be initialized).
The quantum computing device 100 may generate an integrated logical qubit 1130 by turning on (activating) a stabilizer between a first logical qubit 1121 corresponding to the data patch 1111 and a second logical qubit 1122 corresponding to the first ancilla patch 1112.
The quantum computing device 100 may perform the joint XY measurement in the first logical qubit 1121 and the second logical qubit 1122 by using the integrated logical qubit 1130.
The quantum computing device 100 multiplies all parities of a stabilizer 1131 that determines a joint XY measurement result among newly operating stabilizers to acquire a result of the joint XY measurement.
The quantum computing device 100 may measure a qubit which is present in a first region 1141 as the Z basis and a qubit which is present in a second region 1142 as the X basis in an integrated logical qubit 1140. After measurement is completed, the second logical qubit 1122 corresponding to the first ancilla patch 1112 may be consumed during the operation process, and only a logical qubit 1150 corresponding to an operation result may be present.
In the logical SH operation performing process according to an exemplary embodiment of the present disclosure, a total of 1d cycle may be consumed.
In the quantum computing device 100, a data patch 1211 may be in any state |ψL which is to perform the logical T operation. A first ancilla patch 1212 may be |0
L. Alternatively, the first ancilla patch 1212 may be prepared as |0
L (may be initialized). A second ancilla patch 1213 may be prepared |A
L.
The quantum computing device 100 may generate an integrated logical qubit 1230 by turning on (activating) ‘a stabilizer which is present between the data patch 1211 and the first ancilla patch 1212’ and ‘a stabilizer which is present between the data patch 1211 and the second ancilla patch 1213’. The quantum computing device 100 may perform the joint ZZ & ZY measurement in three logical qubits 1211, 1212, and 1213 by using the integrated logical qubit 1230.
The quantum computing device 100 multiplies all parities of a stabilizer 1231 that determines the joint ZZ measurement result among newly operating stabilizers to acquire a result of the joint ZZ measurement. The stabilizer 1231 that determines the joint ZZ measurement result may be predetermined.
The quantum computing device 100 multiplies all parities of a stabilizer 1232 that determines a joint ZY measurement result among newly operating stabilizers to acquire a result of the joint ZY measurement. The stabilizer 1232 that determines the joint ZY measurement result may be predetermined.
The quantum computing device 100 may measure the first ancilla patch 1212 which is |0L as the Z basis when the joint ZZ measurement result is +1. Accordingly, the quantum computing device 100 may measure a qubit which is present in a first region 1241 as the Z basis in an integrated logical qubit 1240 and a qubit which is present in a second region 1242 as the X basis in the integrated logical qubit 1240.
The quantum computing device 100 may measure the first ancilla patch 1212 which is |0L as the X basis when the joint ZZ measurement result is −1. Accordingly, the quantum computing device 100 may measure a qubit which is present in a first region 1251 as the Z basis in an integrated logical qubit 1250 in an integrated logical qubit 1250 and a qubit which is present in a second region 1252 as the X basis in the integrated logical qubit 1250.
In the logical T operation performing process according to an exemplary embodiment of the present disclosure, a total of 1d cycle may be consumed.
Hereinafter, a result of comparing the implementation method of the logical S operation and T operation proposed in the related art and the implementation method of the logical S operation and T operation according to an exemplary embodiment of the present disclosure will be described below.
Table 1 below is a table in which the logical S operation method proposed in the related art and the time cost, the space cost, and the space-time cost of the logical S operation according to an exemplary embodiment of the present disclosure are compared with each other.
> z and 5-qubit defect
> z and 4-qubit detect
indicates data missing or illegible when filed
Referring to Table 1, a method (Fowler, A., G., Mariantoni, M. Martinis, J. M. & Cleland, A. N. “Surface codes: Towards practical large-scale quantum computation.” Physical Review A 86.3 (2012): 032324.) proposed by Fowler in 2012 as a case of performing the logical S by using the logical Hadamard and CNOT operations requires |YL which is the magic state. Since a large cost is consumed for the logical Hadamard and CNOT operations, the time and space costs increase. Although not considered in the table, a separate cost is required even in a magic state distillation process of preparing |Y
L which is the magic state.
In a logical S operation performing method (Haah, Jeongwan, and Matthew B., Hastings. “Measurement sequences for magic state distillation.” Quantum 5 (2021): 383.) introduced in a study by Haah in 2021, the joint ZZ measurement, and |YL which is the magic state are used. The corresponding technique requires small time and space costs, but a cost required for preparing |Y
L which is the magic state is excluded therefrom, so a separate cost is also required for the magic state distillation process.
A logical S operation performing method (Litinski, Daniel, “A game of surface codes: Large-scale quantum computing with lattice surgery.”, Quantum 3 (2019): 128.) presented in a study by Litinski in 2019 is a scheme that uses the joint ZY measurement in a logical qubit of two-patch wide by using the 5-qubit twist defect. The corresponding technique does not require |YL which is the magic state, but uses the logical qubit of two-patch wide, so the space cost increases.
Table 2 below is a table in which the logical T operation method proposed in the related art and the time cost, the space cost, and the space-time cost of the logical T operation according to an exemplary embodiment of the present disclosure are compared with each other.
>
>
indicates data missing or illegible when filed
Referring to Table 2, a logical T operation performing method (Zhou, Xinlan, Debbie W. Leung, and Isaac L. Chuang. “Methodology for quantum logic gate construction.” Physical Review A 62.5 (2000): 052316.) proposed in a study by Zhou in 2000 is a teleportation circuit using the logical CNOT and S operations. Since the corresponding technique requires the logical S operation, the large time and space costs are required.
In a study (Sergey Bravyi, Graeme Smith, and John A. Smolin. “Trading classical and quantum computational resources.” Physical Review X 6.2 (2016): 021043.) by Bravyi in 2016 and a study (Fowler, Austin G. and Craig Gidney. “Low overhead quantum computation using lattice surgery.” arXiv preprint arXiv:1808.06709 (2018).) by Fowler in 2018, the logical T operation performing method is introduced by using |AL which is the magic state, and the joint ZZ measurement. In the corresponding technique, a smaller cost is used than the method using the logical CNOT, but the logical S operation is used, so a time cost of 2d is required.
A logical T operation performing method (Litinski, Daniel. “A game of surface codes: Large-scale quantum computing with lattice surgery.” Quantum 3 (2019): 128) presented in the study by Litinski in 2019 is a scheme that uses the joint ZZ & ZY measurement in the logical qubit of two-patch wide by using the 5-qubit twist defect. The corresponding technique does not require |AL which is the magic state, but uses the logical qubit of two-patch wide, so the space cost increases.
As described above with reference to
Further, since the quantum computing device 100 according to an exemplary embodiment of the present disclosure may constitute a layout of the logical qubit by the logical qubit of one-patch wide, it may be suitable to place the logical qubit according to a layout such as checkerboard-type, row-type, etc.
The 5-qubit twist defect used in two-patch wide may take a longer time of the measurement circuit than the X and Z stabilizers in the related art. Accordingly, a longer time is required for 1 surface code cycle, and this increases a required time of an entire circuit. On the contrary, since the parity measurement circuit of the 4-qubit twist defect used in the quantum computing device 100 according to an exemplary embodiment of the present disclosure is enabled to be performed within the same time as the X and Z stabilizers in the related art, 1 surface code cycle may not be increased.
Meanwhile,
Steps illustrated in
Referring to
When the processor 110 performs a logical Hadamard operation in a logical qubit, and performs a first operation using a first joint measurement, the processor 110 may perform a boundary flip (1320).
In an exemplary embodiment, the boundary flip may refer to replacing an X boundary included in the logical qubit with a Z boundary, and the Z boundary with an X boundary.
The X boundary may be a boundary constituted by an X stabilizer included in the logical qubit.
The Z boundary may be a boundary constituted by a Z stabilizer included in the logical qubit.
The processor 110 may perform a first operation by using a second joint measurement other than the first joint measurement in a boundary-inverted logical qubit (1330).
When a measurement of an operation subsequent to the logical Hadamard operation is the joint XX measurement, the processor 110 may transform the operation as in Equation 1 below.
When the measurement of an operation subsequent to the logical Hadamard operation is the joint ZZ measurement, the processor 110 may transform the operation as in Equation 2 below.
In Equations 1 and 2, an arrow may mean that a left formula of the arrow may be changed to a right formula of the arrow. ⊗ may represent a tensor product, and † may represent a conjugate-transpose. Referring to Equations 1 and 2, a left relationship of the arrow is established between a Hadamard operation H, and a Pauli operation (X, Z), and an Identity operation I, and when this is transformed as in the right side of the arrow, it can be seen that performing the X operation after the H operation is the same as performing the H operation after the Z operation.
In an exemplary embodiment, the processor 110 may perform the joint XZ measurement which is the second joint measurement other than the joint ZZ measurement which is the first joint measurement in the boundary-inverted logical qubit when the first operation is the logical CNOT.
In an exemplary embodiment, the processor 110 may perform the joint ZX measurement which is the second joint measurement other than the joint XX measurement which is the first joint measurement in the boundary-inverted logical qubit when the first operation is patch extension. The patch extension may mean that one patch which is in any ψ(psi) state performs the joint ZZ measurement with a patch which is in the + state, or performs the joint XX measurement with a patch which is in the 0 state. Since a merged patch is still in the ψ(psi) state, the same effect as increasing the patch may be just achieved.
In an exemplary embodiment, the processor 110 may perform the joint XY measurement which is the second joint measurement other than the joint ZY measurement which is the first joint measurement in the boundary-inverted logical qubit when the first operation is the logical S operation.
In an exemplary embodiment, the processor 110 may perform the joint ZX and XY measurement which is the second joint measurement other than the joint ZZ and ZY measurement which is the first joint measurement in the boundary-inverted logical qubit when the first operation is the logical T operation.
The processor 110 may change an order of the logical Hadamard operation after a step of performing the first operation by using the second joint measurement (1340).
In an exemplary embodiment, when there is another operation other than the measurement subsequent to the changed order of the logical Hadamard operation, the processor 110 may repeatedly perform the above steps 1320 and 1330. For example, when there is a second operation using a third joint measurement subsequent to the changed order of the logical Hadamard operation, the processor 110 may perform the boundary flip in the logical qubit in which the first operation is performed. The processor 110 may perform the second operation by using a fourth joint measurement other than the third joint measurement in a logical qubit in which the boundary flip and the first operation are performed. The processor 110 may change the order of the logical Hadamard operation after a step of performing the second operation by using the fourth joint measurement.
In an exemplary embodiment, when there is a single measurement subsequent to the changed order of the logical Hadamard operation, the processor 110 merges the logical Hadamard operation and the single measurement to change a basis which measuring the logical qubit in which the first operation is performed in the single measurement.
For example, when the basis measured in the single measurement is the X basis, the processor 110 merges the logical Hadamard operation and the single measurement to change the basis measured in the single measurement to the Z basis.
As another example, when the basis measured in the single measurement is the Z basis, the processor 110 merges the logical Hadamard operation and the single measurement to change the basis measured in the single measurement to the X basis.
Hereinafter, a detailed description of the configuration, step, etc., described above with reference to
Referring to
The processor 110 may correct the logical operation according to a parity measurement result of a newly turned-on stabilizer.
Referring to
In an exemplary embodiment, a logical qubit 1510 represents a qubit that corresponds to a stabilizer, and logical X and Z before the boundary flip. In the logical qubit 1510, XL
In an exemplary embodiment, even though the logical operation is multiplied by the stabilizer, the logical operation may be the same as the logical operation in the related art. Accordingly, in a logical qubit 1520, XL
In an exemplary embodiment, the X boundary of logical qubit 1530 may be extended beyond the existing X boundaries (XL
In the logical qubit 1530, XL
In the logical qubit 1540, XL
In an exemplary embodiment, the X boundary of logical qubit 1550 may be extended beyond the existing X boundary (XL
In the logical qubit 1550, XL
In the logical qubit 1560, XL
In an exemplary embodiment, specific stabilizers 1521, 1531, 1541, 1551, 1561 may indicate stabilizers that require correction because their values can randomly be 0 or 1.
In an exemplary embodiment, the processor 110 may correct logical operations based on the values of specific stabilizers 1521, 1531, 1541, 1551, 1561.
Referring to L, and then control the logical CNOT. The logical CNOT operation may be dissolved into the joint ZZ measurement and the joint XX measurement. The logical Hadamard operation which is to be performed in a control qubit of the logical CNOT may be moved after the logical CNOT while changing the joint ZZ measurement to the joint XZ measurement. The processor 110 may perform a process 1620 of performing the joint XZ measurement. For example, the processor 110 may perform the boundary flip in |Ψ
L in order to change a boundary facing |ψ
L to the X boundary. The processor 110 may newly turn on a mixed stabilizer in which X and Z are mixed. The processor 110 multiplies a parity of the stabilizer marked with a black point to acquire a joint XZ measurement result. An execution order of the physical CNOT in the parity measurement circuit of the mixed stabilizer in which X and Z are mixed is represented as an arrow and a number in the qubit 1630. The corresponding order may be predetermined not to overlap with a physical CNOT execution order of surrounding stabilizers based on the orders specified in the X stabilizer 1403 and the Z stabilizer 1404 of
Referring to L, and the joint ZY measurement. As illustrated in a quantum circuit 1700, the processor 110 may move the logical Hadamard operation to be applied to any to an operation after the logical S operation while changing the joint ZY measurement to the joint XY measurement.
Referring to L and |0
L which are the magic state, and the joint ZZ and ZY measurement. As illustrated in a quantum circuit 1800, the processor 110 may move the logical Hadamard operation to be applied to any |ψ
L to an operation after the logical T operation while changing the joint ZZ measurement to the joint ZY measurement, and changing the joint ZY measurement to the joint XY measurement. Since the joint ZX measurement and the joint XY measurement are commutable operations, the joint ZX measurement and the joint XY measurement may be performed simultaneously.
Referring to
In an exemplary embodiment, as illustrated in a quantum circuit 1920, when the basis measured in the single measurement is the X basis, the processor 110 merges the logical Hadamard operation and the single measurement to change the basis measured in the single measurement to the Z basis.
Hereinafter, a result of comparing the implementation method of the logical H operation proposed in the related art and the implementation method of the logical H operation according to an exemplary embodiment of the present disclosure will be described below.
Table 3 below is a table in which the logical H operation method proposed in the related art and whether to perform the physical H operation, the time cost, the space cost, and the space-time cost in the logical H operation according to an exemplary embodiment of the present disclosure are compared with each other.
Referring to Table 3, in a method (Dominic Horsman, Austin G Fowler, Simon Devitt, Rodney Van Meter, “Surface code quantum computing by lattice surgery” New Journal of Physics, December 2012) proposed by Horsman in 2012 as a case of performing the physical Hadamard, rotation is performed by merging with a surround region. In this case, since a swap operation of the physical qubit is required, a clearance is required for each of all logical qubits (patches), so the number of physical qubits required per logical qubit becomes 2d2.
In a study (Alexander Erhard, Hendrik Poulsen Nautrup, Michael Meth, Lukas Postler, Roman Stricker, Martin Stadler, Vlad Negnevitsky, Martin Ringbauer, Philipp Schindler, Hans J. Briegel, Rainer Blatt, Nicolai Friis, Thomas Monz “Entangling logical qubits with lattice surgery” Nature, vol. 589, pp. 220-224, January 2021) by Erhard in 2021, quantum teleportation is utilized in order to perform the Hadamard operation in one data patch. Accordingly, one logical qubit which is in 0 state is consumed, and data to which Hadamard is applied is stored in the logical qubit which is in the 0 state. When a qubit layout such as Checkerboard-type, row-type, etc., is considered, the Hadamard operation additionally uses the logical qubit, so the Hadamard operation becomes a consideration target upon routing. Besides, a time for returning data to an original location again is also added. Accordingly, the Hadamard operation influences the time cost in addition to the space cost.
As described above with reference to
The quantum computing device 100 according to an exemplary embodiment of the present disclosure may be enabled to perform the H operation with smaller time and space costs than the method in the related art through the boundary flip and the subsequent measurement transformation.
The quantum computing device 100 according to an exemplary embodiment of the present disclosure may change the basis of the operation afterwards instead of performing the physical Hadamard in the process of performing the logical Hadamard.
The quantum computing device 100 according to an exemplary embodiment of the present disclosure may use a boundary flip technique to easily transform the boundary of the logical qubit according to the changed basis.
The quantum computing device 100 according to an exemplary embodiment of the present disclosure uses the boundary flip to transform the boundary of the logical qubit without additional qubit consumption within a shorter than the scheme in the related art.
The present disclosure has generally been described above in association with a computer executable instruction which may be executed on one or more computers, but it will be well appreciated by those skilled in the art that the present disclosure can be implemented through a combination with other program modules and/or a combination of hardware and software.
In general, the module in the present specification includes a routine, a procedure, a program, a component, a data structure, and the like that execute a specific task or implement a specific abstract data type. Further, it will be well appreciated by those skilled in the art that the method of the present disclosure can be implemented by other computer system configurations including a personal computer, a handheld computing device, microprocessor-based or programmable home appliances, and others (the respective devices may operate in connection with one or more associated devices as well as a single-processor or multi-processor computer system, a mini computer, and a main frame computer.
The exemplary embodiments described in the present disclosure may also be implemented in a distributed computing environment in which predetermined tasks are performed by remote processing devices connected through a communication network. In the distributed computing environment, the program module may be positioned in both local and remote memory storage devices.
The computer generally includes various computer readable media. Media accessible by the computer may be computer readable media regardless of types thereof and the computer readable media include volatile and non-volatile media, transitory and non-transitory media, and mobile and non-mobile media. As a non-limiting example, the computer readable media may include both computer readable storage media and computer readable transmission media.
The computer readable storage media include volatile and non-volatile media, transitory and non-transitory media, and mobile and non-mobile media implemented by a predetermined method or technology for storing information such as a computer readable instruction, a data structure, a program module, or other data. The computer readable storage media include a RAM, a ROM, an EEPROM, a flash memory or other memory technologies, a CD-ROM, a digital video disk (DVD) or other optical disk storage devices, a magnetic cassette, a magnetic tape, a magnetic disk storage device or other magnetic storage devices or predetermined other media which may be accessed by the computer or may be used to store desired information, but are not limited thereto.
The computer readable transmission media generally implement the computer readable instruction, the data structure, the program module, or other data in a carrier wave or a modulated data signal such as other transport mechanism and include all information transfer media. The term “modulated data signal” means a signal acquired by setting or changing at least one of characteristics of the signal so as to encode information in the signal. As a non-limiting example, the computer readable transmission media include wired media such as a wired network or a direct-wired connection and wireless media such as acoustic, RF, infrared and other wireless media. A combination of any media among the aforementioned media is also included in a range of the computer readable transmission media.
An exemplary environment that implements various aspects of the present disclosure including a computer 2002 is shown and the computer 2002 includes a processing device 2004, a system memory 2006, and a system bus 2008. The system bus 2008 connects system components including the system memory 2006 (not limited thereto) to the processing device 2004. The processing device 2004 may be a predetermined processor among various commercial processors. A dual processor and other multi-processor architectures may also be used as the processing device 2004.
The system bus 2008 may be any one of several types of bus structures which may be additionally interconnected to a local bus using any one of a memory bus, a peripheral device bus, and various commercial bus architectures. The system memory 2006 includes a read only memory (ROM) 2010 and a random access memory (RAM) 2012. A basic input/output system (BIOS) is stored in the non-volatile memories 2010 including the ROM, the EPROM, the EEPROM, and the like and the BIOS includes a basic routine that assists in transmitting information among components in the computer 2002 at a time such as in-starting. The RAM 2012 may also include a high-speed RAM including a static RAM for caching data, and the like.
The computer 2002 also includes an internal hard disk drive (HDD) 2014 (for example, EIDE and SATA) —the internal hard disk drive (HDD) 2064 may also be configured for an external purpose in an appropriate chassis (not illustrated), a magnetic floppy disk drive (FDD) 2016 (for example, for reading from or writing in a mobile diskette 2018), and an optical disk drive 2020 (for example, for reading a CD-ROM disk 2022 or reading from or writing in other high-capacity optical media such as the DVD). The hard disk drive 2014 and 2064, the magnetic disk drive 2016, and the optical disk drive 2020 may be connected to the system bus 2008 by a hard disk drive interface 2024, a magnetic disk drive interface 2026, and an optical disk drive interface 2028, respectively. An interface 2024 for implementing an external drive includes, for example, at least one of a universal serial bus (USB) and an IEEE 1394 interface technology or both of them.
The drives and the computer readable media associated therewith provide non-volatile storage of the data, the data structure, the computer executable instruction, and others. In the case of the computer 2002, the drives and the media correspond to storing of predetermined data in an appropriate digital format. In the description of the computer readable storage media, the mobile optical media such as the HDD, the mobile magnetic disk, and the CD or the DVD are mentioned, but it will be well appreciated by those skilled in the art that other types of storage media readable by the computer such as a zip drive, a magnetic cassette, a flash memory card, a cartridge, and others may also be used in an exemplary operating environment and further, the predetermined media may include computer executable commands for executing the methods of the present disclosure.
Multiple program modules including an operating system 2030, one or more application programs 2032, other program module 2034, and program data 2036 may be stored in the drive and the RAM 2012. All or some of the operating system, the application, the module, and/or the data may also be cached by the RAM 2012. It will be well appreciated that the present disclosure may be implemented in operating systems which are commercially usable or a combination of the operating systems.
A user may input instructions and information in the computer 2002 through one or more wired/wireless input devices, for example, pointing devices such as a keyboard 2038 and a mouse 2040. Other input devices (not illustrated) may include a microphone?, an IR remote controller, a joystick, a game pad, a stylus pen, a touch screen, and others. These and other input devices are often connected to the processing device 2008 through an input device interface 2042 connected to the system bus 2004, but may be connected by other interfaces including a parallel port, an IEEE 1394 serial port, a game port, a USB port, an IR interface, and others.
A monitor 2044 or other types of display devices are also connected to the system bus 2008 through interfaces such as a video adapter 2046, and the like. In addition to the monitor 2044, the computer generally includes other peripheral output devices (not illustrated) such as a speaker, a printer, others.
The computer 2002 may operate in a networked environment by using a logical connection to one or more remote computers including remote computer(s) 2048 through wired and/or wireless communication. The remote computer(s) 2048 may be a workstation, a server computer, a router, a personal computer, a portable computer, a micro-processor based entertainment apparatus, a peer device, or other general network nodes and generally includes multiple components or all of the components described with respect to the computer 2002, but only a memory storage device 2050 is illustrated for brief description. The illustrated logical connection includes a wired/wireless connection to a local area network (LAN) 2052 and/or a larger network, for example, a wide area network (WAN) 2054. The LAN and WAN networking environments are general environments in offices and companies and facilitate an enterprise-wide computer network such as the Intranet, and all of them may be connected to a worldwide computer network, for example, the Internet.
When the computer 2002 is used in the LAN networking environment, the computer is connected to a local network 2052 through a wired and/or wireless communication network interface or an adapter 2056. The adapter 2056 may facilitate the wired or wireless communication to the LAN 2052 and the LAN 2052 also includes a wireless access point installed therein in order to communicate with the wireless adapter 2056. When the computer 2002 is used in the WAN networking environment, the computer 2002 may include a modem 2058 or may be connected to a communication server on the WAN 2054, or has other means that configure communication through the WAN 2054 such as the Internet, etc. The modem 2058 which may be an internal or external and wired or wireless device is connected to the system bus 2008 through the serial port interface 2042. In the networked environment, the program modules described with respect to the computer 2002 or some thereof may be stored in the remote memory/storage device 2050. It will be well known that an illustrated network connection is exemplary and other means configuring a communication link among computers may be used.
The computer 2002 performs an operation of communicating with predetermined wireless devices or entities which are disposed and operated by the wireless communication, for example, the printer, a scanner, a desktop and/or a portable computer, a portable data assistant (PDA), a communication satellite, predetermined equipment or place associated with a wireless detectable tag, and a telephone. This at least includes wireless fidelity (Wi-Fi) and Bluetooth wireless technology. Accordingly, communication may be a predefined structure like the network in the related art or just ad hoc communication between at least two devices.
The wireless fidelity (Wi-Fi) enables connection to the Internet, and the like without a wired cable. The Wi-Fi is a wireless technology such as the device, for example, a cellular phone which enables the computer to transmit and receive data indoors or outdoors, that is, anywhere in a communication range of a base station. The Wi-Fi network uses a wireless technology called IEEE 802.11 (a, b, g, and others) in order to provide safe, reliable, and high-speed wireless connection. The Wi-Fi may be used to connect the computers to each other or the Internet and the wired network (using IEEE 802.3 or Ethernet). The Wi-Fi network may operate, for example, at a data rate of 11 Mbps (802.11a) or 54 Mbps (802.11b) in unlicensed 2.4 and 5 GHz wireless bands or operate in a product including both bands (dual bands).
Those skilled in the art of the present disclosure will appreciate that various exemplary logic blocks, modules, processors, means, circuits, and algorithm steps described in association with the exemplary embodiments disclosed herein can be implemented by electronic hardware, various types of programs or design codes (designated as “software” herein for easy description), or a combination of all thereof. In order to clearly describe the intercompatibility of the hardware and the software, various exemplary components, blocks, modules, circuits, and steps have been generally described above in association with functions thereof. Whether the functions are implemented as the hardware or software depends on design restrictions given to a specific application and an entire system. Those skilled in the art of the present disclosure may implement functions described by various methods with respect to each specific application, but it should not be analyzed that the implementation determination departs from the scope of the present disclosure.
Various exemplary embodiments presented herein may be implemented as manufactured articles using a method, a device, or a standard programming and/or engineering technique. The term “manufactured article” includes a computer program, a carrier, or a medium which is accessible by a predetermined computer readable device. For example, a computer readable medium includes a magnetic storage device (for example, a hard disk, a floppy disk, a magnetic strip, or the like), an optical disk (for example, a CD, a DVD, or the like), a smart card, and a flash memory device (for example, an EEPROM, a card, a stick, a key drive, or the like), but is not limited thereto. The term “machine-readable media” includes a wireless channel and various other media that can store, possess, and/or transfer instruction(s) and/or data, but is not limited thereto.
It will be appreciated that a specific order or a hierarchical structure of steps in the presented processes is one example of exemplary accesses. It will be appreciated that the specific order or the hierarchical structure of the steps in the processes within the scope of the present disclosure may be rearranged based on design priorities. Appended method claims provide elements of various steps in a sample order, but the method claims are not limited to the presented specific order or hierarchical structure.
The description of the presented exemplary embodiments is provided so that those skilled in the art use or implement the present disclosure. Various modifications of the exemplary embodiments will be apparent to those skilled in the art and general principles defined herein can be applied to other embodiments without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the exemplary embodiments presented herein, but should be analyzed within the widest range which is coherent with the principles and new features presented herein.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0148279 | Oct 2023 | KR | national |
