Apparatus and method of ion current compensation

Abstract

Embodiments provided herein generally include apparatus, plasma processing systems and methods for generation of a waveform for plasma processing of a substrate in a processing chamber. Embodiments of the disclosure include an apparatus and method for generating a pulsed-voltage waveform that includes coupling a main voltage source to an electrode during a first phase of a process of generating a pulsed-voltage waveform, wherein the electrode is disposed within a processing chamber, coupling a ground node to the electrode during a second phase of the process of generating the pulsed-voltage waveform, coupling a first compensation voltage source to the electrode during a third phase of the process of generating the pulsed-voltage waveform, and coupling a second compensation voltage source to the electrode during a fourth phase of the process of generating the pulsed-voltage waveform.

Description

BACKGROUND

Field

Embodiments of the present disclosure generally relate to a system used in semiconductor device manufacturing. More specifically, embodiments of the present disclosure relate to a plasma processing system used to process a substrate.

Description of the Related Art

Reliably producing high aspect ratio features is one of the key technology challenges for the next generation of semiconductor devices. One method of forming high aspect ratio features uses a plasma-assisted etching process in which a plasma is formed in a processing chamber and ions from the plasma are accelerated towards a surface of a substrate to form openings in a material layer disposed beneath a mask layer formed on the surface of the substrate.

In a typical plasma-assisted etching process, the substrate is positioned on a substrate support disposed in a processing chamber, a plasma is formed over the substrate, and ions are accelerated from the plasma towards the substrate across a plasma sheath, i.e., region depleted of electrons, formed between the plasma and the surface of the substrate.

It has been found that conventional RF plasma-assisted etching processes, which only deliver sinusoidal waveform containing RF signals to one or more of the electrodes in a plasma processing chamber, do not adequately or desirably control the sheath properties and generated ion energies, which leads to undesirable plasma processing results. The undesirable processing results can include excessive sputtering of the mask layer and the generation of sidewall defects in high-aspect ratio features.

Accordingly, there is a need in the art for plasma processing and biasing methods that are able to provide desirable plasma-assisted etching process results.

SUMMARY

Embodiments provided herein generally include apparatus, plasma processing systems and methods for generation of a waveform for plasma processing of a substrate in a processing chamber.

BRIEF DESCRIPTION OF THE DRAWINGS

So that the manner in which the above-recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only exemplary embodiments and are therefore not to be considered limiting of its scope and may admit to other equally effective embodiments.

FIG. 1 is a schematic cross-sectional view of a processing system, according to one or more embodiments, configured to practice the methods set forth herein.

FIG. 2A shows a voltage waveform that may be applied to an electrode of a processing chamber, according to one or more embodiments.

FIG. 2B shows a voltage waveform that is established on a substrate due to a voltage waveform applied to an electrode of a processing chamber.

FIG. 3A illustrates a typical ion energy distribution (IED) when using a single frequency excitation waveform.

FIG. 3B is a graph illustrating an IED function (IEDF), in accordance with certain embodiments of the present disclosure.

FIG. 4A illustrates a pulsed-voltage (PV) waveform generated using a waveform generator of FIG. 5A, in accordance with certain embodiments of the present disclosure.

FIG. 4B illustrates a PV waveform generated using a waveform generator of FIG. 5C, in accordance with certain embodiments of the present disclosure.

FIG. 4C illustrates a measurement waveform generated using a waveform generator of FIG. 5A, in accordance with certain embodiments of the present disclosure.

FIG. 5A illustrates an example implementation of a waveform generator for biasing a substrate to achieve IED control, in accordance with certain aspects of the present disclosure.

FIG. 5B illustrates an example implementation of a waveform generator for biasing a substrate to achieve IED control, in accordance with certain aspects of the present disclosure.

FIG. 5C illustrates an example implementation of a waveform generator for biasing a substrate to achieve IED control, in accordance with certain aspects of the present disclosure.

FIG. 6 illustrates an example filter topology for use with the waveform generator of FIG. 5C, in accordance with certain embodiments of the present disclosure.

FIG. 7 is a timing diagram illustrating state of switches of the waveform generator of FIG. 5A, 5B, or 5C in accordance with certain aspects of the present disclosure.

FIG. 8 is a process flow diagram illustrating a method for waveform generation.

DETAILED DESCRIPTION

With technology node advancing towards 2 nm, fabrication of smaller features with larger aspect ratios involve atomic precision for plasma processing. For etching processes where the plasma ions play an important role, ion energy control is challenging the semiconductor equipment industry. Traditionally RF biased techniques use a sinusoidal wave to excite plasma and accelerate ions.

Some embodiments of the present disclosure are generally directed to techniques for generating a pulsed-voltage (PV) waveform for controlling ion energy distribution (IED). For example, a pulsed-voltage waveform and a radio frequency (RF) waveform may be applied to the same node in a plasma chamber to implement a low energy peak and a high-energy peak in the IED function with little to no intermediate energies between the low energy and high-energy peaks, as described in more detail herein. Ions associated with the high-energy peak have the energy and directionality to reach to the bottom of a high-aspect ratio feature that is being etched and enable etching reactions. Although ions with low energy cannot reach the bottom of the feature during etching, the low energy ions are still important for etch processes. Ions with intermediate energies are not beneficial for etch processes as they do not have the desired directionality and will hit the sidewall of a feature being etched, often resulting in an undesired bowing of the sidewalls in the etched feature. Some embodiments are directed to techniques for generating a PV waveform having high-energy and low energy peaks, with little to no intermediate energy ions.

Plasma Processing System Examples

FIG. 1 is a schematic cross-sectional view of a processing system 10 configured to perform one or more of the plasma processing methods set forth herein. In some embodiments, the processing system 10 is configured for plasma-assisted etching processes, such as a reactive ion etch (RIE) plasma processing. However, it should be noted that the embodiments described herein may be also be used with processing systems configured for use in other plasma-assisted processes, such as plasma-enhanced deposition processes, for example, plasma-enhanced chemical vapor deposition (PECVD) processes, plasma-enhanced physical vapor deposition (PEPVD) processes, plasma-enhanced atomic layer deposition (PEALD) processes, plasma treatment processing or plasma-based ion implant processing, for example, plasma doping (PLAD) processing.

As shown, the processing system 10 is configured to form a capacitively coupled plasma (CCP), where the processing chamber 100 include an upper electrode (e.g., chamber lid 123) disposed in a processing volume 129 facing a lower electrode (e.g., the substrate support assembly 136) also disposed in the processing volume 129. In a typical capacitively coupled plasma (CCP) processing system, a radio frequency (RF) source is electrically coupled to one of the upper or lower electrode delivers an RF signal configured to ignite and maintain a plasma (e.g., the plasma 101), which is capacitively coupled to each of the upper and lower electrodes and is disposed in a processing region therebetween. Typically, the opposing one of the upper or lower electrodes is coupled to ground or to a second RF power source for additional plasma excitation. As shown, the processing system 10 includes a processing chamber 100, a substrate support assembly 136, and a system controller 126.

The processing chamber 100 typically includes a chamber body 113 that includes the chamber lid 123, one or more sidewalls 122, and a chamber base 124, which collectively define the processing volume 129. The one or more sidewalls 122 and chamber base 124 generally include materials that are sized and shaped to form the structural support for the elements of the processing chamber 100 and are configured to withstand the pressures and added energy applied to them while a plasma 101 is generated within a vacuum environment maintained in the processing volume 129 of the processing chamber 100 during processing. In one example, the one or more sidewalls 122 and chamber base 124 are formed from a metal, such as aluminum, an aluminum alloy, or a stainless steel alloy.

A gas inlet 128 disposed through the chamber lid 123 is used to deliver one or more processing gases to the processing volume 129 from a processing gas source 119 that is in fluid communication therewith. A substrate 103 is loaded into, and removed from, the processing volume 129 through an opening (not shown) in one of the one or more sidewalls 122, which is sealed with a slit valve (not shown) during plasma processing of the substrate 103.

In some embodiments, a plurality of lift pins 20 movably disposed through openings formed in the substrate support assembly 136 are used to facilitate substrate transfer to and from a substrate supporting surface 105A. In some embodiments, the plurality of lift pins 20 are disposed above and are coupled to and/or are engageable with a lift pin hoop (not shown) disposed in the processing volume 129. The lift pin hoop may be coupled to a shaft (not shown) that sealingly extends through the chamber base 124. The shaft may be coupled to an actuator (not shown) that is used to raise and lower the lift pin hoop. When the lift pin hoop is in a raised position, it engages with the plurality of lift pins 20 to raise the upper surfaces of the lift pins above the substrate supporting surface 105A, lifting the substrate 103 therefrom and enabling access to a non-active (backside) surface the substrate 103 by a robot handler (not shown). When the lift pin hoop is in a lowered position, the plurality of lift pins 20 are flush with or recessed below the substrate supporting surface 105A, and the substrate 103 rests thereon.

The system controller 126, also referred to herein as a processing chamber controller, includes a central processing unit (CPU) 133, a memory 134, and support circuits 135. The system controller 126 is used to control the process sequence used to process the substrate 103, including the substrate biasing methods described herein. The CPU 133 is a general-purpose computer processor configured for use in an industrial setting for controlling the processing chamber and sub-processors related thereto. The memory 134 described herein, which is generally non-volatile memory, may include random access memory, read-only memory, floppy or hard disk drive, or other suitable forms of digital storage, local or remote. The support circuits 135 are conventionally coupled to the CPU 133 and comprise cache, clock circuits, input/output subsystems, power supplies, and the like, and combinations thereof. Software instructions (program) and data can be coded and stored within the memory 134 for instructing a processor within the CPU 133. A software program (or computer instructions) readable by CPU 133 in the system controller 126 determines which tasks are performable by the components in the processing system 10.

Typically, the program, which is readable by CPU 133 in the system controller 126, includes code, which, when executed by the processor (CPU 133), performs tasks relating to the plasma processing schemes described herein. The program may include instructions that are used to control the various hardware and electrical components within the processing system 10 to perform the various process tasks and various process sequences used to implement the methods described herein. In one embodiment, the program includes instructions that are used to perform one or more of the operations described below in relation to FIG. 8.

The plasma control system generally includes a first source assembly 196 for establishing at least a first pulsed-voltage (PV) waveform at a bias electrode 104, and a second source assembly 197 for establishing at least a second PV waveform at an edge control electrode 115. The first PV waveform or the second PV waveform may be generated using one or more components within a waveform generator assembly 150, which may correspond to a waveform generator as described in more detail herein with respect to FIGS. 4A-5C. In one embodiment, a waveform generator assembly 150 includes a waveform generator 500 illustrated in FIG. 5A that is configured to produce a PV waveform similar to the PV waveform 400 illustrated in FIG. 4A at the bias electrode 104 and the edge control electrode 115.

In some embodiments, a waveform generator assembly 150 includes a PV waveform generating source and a RF source, such as the waveform generator 550 illustrated in FIG. 5C, that is configured to produce a PV waveform similar to the PV waveform 450 illustrated in FIG. 4B at the bias electrode 104, the edge control electrode 115 and/or the support base 107 (e.g., power electrode or cathode). The waveform generator 550 of the waveform generator assembly 150 of the first source assembly 196 can be configured to deliver a PV waveform and an RF signal to the support base 107 (e.g., power electrode or cathode) or the bias electrode 104. In some embodiments, as shown in FIG. 1, a separate waveform generator assembly 150 within a third source assembly 198 includes at least an RF source that is configured to deliver an RF signal to the support base 107 (e.g., power electrode or cathode).

The applied RF signal provided from the first source assembly 196, the second source assembly 197 or the third source assembly 198 may be configured to generate (maintain and/or ignite) a plasma 101 in a processing region disposed between the substrate support assembly 136 and the chamber lid 123. In some embodiments, the RF signal is used to ignite and maintain a plasma 101 using the processing gases disposed in the processing volume 129 and fields generated by the RF power (RF signal) delivered to the support base 107 and/or the bias electrode 104. The processing volume 129 is fluidly coupled to one or more dedicated vacuum pumps (not shown) through a vacuum outlet 120, which maintain the processing volume 129 at sub-atmospheric pressure conditions and evacuate processing and/or other gases, therefrom. In some embodiments, the substrate support assembly 136, disposed in the processing volume 129, is disposed on a support shaft 138 that is grounded and extends through the chamber base 124. The applied RF signal provided from a waveform generator assembly 150 in the first source assembly 196, the second source assembly 197 or the third source assembly 198 may be provided by an RF generator 506 (FIG. 5C) that is implemented using an RF signal source 581 and a RF matching network 582, in some embodiments. In some embodiments, as discussed further below, the RF generator 506 is configured to deliver an RF signal having a frequency that is greater than 40 MHz, such as between about 40 MHz and about 200 MHz.

Referring back to FIG. 1, the substrate support assembly 136 generally includes a substrate support 105 (e.g., ESC substrate support) having a substrate supporting surface 105A and a support base 107. In some embodiments, the substrate support assembly 136 can additionally include an insulator plate 111 and a ground plate 112, as is discussed further below. The support base 107 is electrically isolated from the chamber base 124 by the insulator plate 111, and the ground plate 112 is interposed between the insulator plate 111 and the chamber base 124. The substrate support 105 is thermally coupled to and disposed on the support base 107. In some embodiments, the support base 107 is configured to regulate the temperature of the substrate support 105, and the substrate 103 disposed on the substrate support 105, during substrate processing. In some embodiments, the support base 107 includes one or more cooling channels (not shown) disposed therein that are fluidly coupled to, and in fluid communication with, a coolant source (not shown), such as a refrigerant source or water source having a relatively high electrical resistance. In some embodiments, the substrate support 105 includes a heater (not shown), such as a resistive heating element embedded in the dielectric material thereof. Herein, the support base 107 is formed of a corrosion-resistant thermally conductive material, such as a corrosion-resistant metal, for example aluminum, an aluminum alloy, or a stainless steel and is coupled to the substrate support with an adhesive or by mechanical means.

Typically, the substrate support 105 is formed of a dielectric material, such as a bulk sintered ceramic material, such as a corrosion-resistant metal oxide or metal nitride material, for example, aluminum oxide (Al₂O₃), aluminum nitride (AlN), titanium oxide (TiO), titanium nitride (TiN), yttrium oxide (Y₂O₃), mixtures thereof, or combinations thereof. In embodiments herein, the substrate support 105 further includes the bias electrode 104 embedded in the dielectric material thereof.

In one configuration, the bias electrode 104 is a chucking pole used to secure (i.e., chuck) the substrate 103 to the substrate supporting surface 105A of the substrate support 105 and to bias the substrate 103 with respect to the plasma 101 using one or more of the pulsed-voltage biasing schemes described herein. Typically, the bias electrode 104 is formed of one or more electrically conductive parts, such as one or more metal meshes, foils, plates, or combinations thereof. In some embodiments, the substrate surface and the bias electrode 104 form a capacitive element (e.g., referred to as an electrostatic chuck capacitor (C_esc)), which, in some embodiments, includes the dielectric material layer of the substrate support 105 disposed between the bias electrode 104 and the substrate supporting surface 105A, as shown in FIG. 1.

In some embodiments, the bias electrode 104 is electrically coupled to a clamping network, which provides a chucking voltage thereto, such as static DC voltage between about −5000 V and about 5000 V, using an electrical conductor, such as the coaxial power delivery line 106 (e.g., a coaxial cable). The clamping network includes a DC power supply 155 (e.g., a high voltage DC supply) and a filter 151 (e.g., a low-pass filter).

The substrate support assembly 136 may further include the edge control electrode 115 that is positioned below the edge ring 114 and surrounds the bias electrode 104 and/or is disposed a distance from a center of the bias electrode 104. In general, for a processing chamber 100 that is configured to process circular substrates, the edge control electrode 115 is annular in shape, is made from a conductive material, and is configured to surround at least a portion of the bias electrode 104. In some embodiments, such as shown in FIG. 1, the edge control electrode 115 is positioned within a region of the substrate support 105. In some embodiments, as illustrated in FIG. 1, the edge control electrode 115 includes a conductive mesh, foil, and/or plate that is disposed a similar distance (i.e., Z-direction) from the substrate supporting surface 105A of the substrate support 105 as the bias electrode 104.

The edge control electrode 115 can be biased by use of a waveform generator assembly that is different from the waveform generator assembly 150 that is used to bias the bias electrode 104. In some embodiments, the edge control electrode 115 can be biased by use of a waveform generator assembly 150 that is also used to bias the bias electrode 104 by splitting part of the power to the edge control electrode 115. In one configuration, the waveform generator assembly 150 of the first source assembly 196 is configured to bias the bias electrode 104, and the waveform generator assembly 150 of a second source assembly 197 is configured to bias the edge control electrode 115.

A power delivery line 157 electrically connects the output of the waveform generator assembly 150 of the first source assembly 196 to the bias electrode 104. While the discussion below primarily discusses the power delivery line 157 of the first source assembly 196, which is used to couple the waveform generator assembly 150 of the first source assembly 196 to the bias electrode 104, the power delivery line 158 of the second source assembly 197, which couples the waveform generator assembly 150 of the second source assembly 197 to the edge control electrode 115, will include the same or similar components. The electrical conductor(s) within the various parts of the power delivery line 157 may include: (a) one or a combination of coaxial cables, such as a flexible coaxial cable that is connected in series with a rigid coaxial cable, (b) an insulated high-voltage corona-resistant hookup wire, (c) a bare wire, (d) a metal rod, (e) an electrical connector, or (f) any combination of electrical elements in (a)-(e).

In some embodiments, the processing chamber 100 further includes a quartz pipe 110, or collar, that at least partially circumscribes portions of the substrate support assembly 136 to prevent the substrate support 105 and/or the support base 107 from contact with corrosive processing gases or plasma, cleaning gases or plasma, or byproducts thereof. Typically, the quartz pipe 110, the insulator plate 111, and the ground plate 112 are circumscribed by a cathode liner 108. In some embodiments, a plasma screen 109 is positioned between the cathode liner 108 and the sidewalls 122 to prevent plasma from forming in a volume underneath the plasma screen 109 between the cathode liner 108 and the one or more sidewalls 122.

FIG. 2A shows a voltage waveform that may be established at an electrode of a processing chamber. FIG. 2B illustrates an example of different types of voltage waveforms 225 and 230 established at a substrate surface due to different voltage waveforms, similar to the voltage waveform shown in FIG. 2A, that are separately established at an electrode within the processing chamber. The waveforms include two stages: an ion current stage and a sheath collapse stage, as shown. At the beginning of the ion current stage, a drop of substrate voltage creates a high voltage sheath above the substrate, accelerating positive ions to the substrate. The positive ions that bombard the surface of the substrate during the ion current stage deposit a positive charge on the substrate surface, which if uncompensated for causes a gradually increase the substrate voltage positively during the ion current stage, as illustrated by voltage waveform 225 in FIG. 2B. However, the uncontrolled accumulation of positive charge on the substrate surface undesirably gradually discharges the sheath and chuck capacitors, slowly decreasing the sheath voltage drop and bringing the substrate potential closer to zero, as illustrated by voltage waveform 225. The accumulation of positive charge results in the voltage drop in the voltage waveform established at the substrate surface (FIG. 2B). However, a voltage waveform that is established at the electrode that has a negative slope during the ion current stage, as shown in FIG. 2A, can be generated so as to establish a square shaped region (e.g., near zero slope) for an established substrate voltage waveform, as shown by curve 230 in FIG. 2B. Implementing the slope in the waveform established at the electrode during the ion current stage may be referred to as current compensation. The voltage difference between the beginning and end of the ion current phase determines an ion energy distribution function (IEDF) width. The greater the voltage difference, the wider the IEDF width. To achieve mono-energetic ions and a narrower IEDF width, operations are performed to flatten the substrate voltage waveform in the ion current phase using current compensation. In some embodiments of the present disclosure, a RF signal is overlaid on the voltage waveform shown in FIG. 2A.

Generation Technique for Waveform Generation

Certain embodiments of the present are generally directed to techniques for waveform generation that facilitate plasma processing of a substrate using simultaneous plasma generation and ion energy distribution (IED) control while reducing undesirable IED bowing profiles formed in the etched high aspect-ratio features. For example, a pulsed-voltage (PV) waveform may be generated with an RF signal overlaid on the PV waveform. In some embodiments, the generated waveform may also include a ramp signal to facilitate current compensation, as described herein.

FIG. 3A illustrates a typical IED when using a single RF frequency excitation waveform. As shown, the IED has a bimodal shape having a high-energy peak 306, a low energy peak 302, and intermediate energy ions (e.g., associated with an intermediate energy region 304). From the aspect of plasma etching processes, only the ions at or near the high-energy peak have the energy and directionality to overcome the ion generated charging effect, created in the material that is being etched, and reach the bottom of a feature and enable etching reactions. Ions with intermediate energies are not beneficial for etch processes as they do not have the directionality and will tend to hit the sidewall of the feature, often resulting in an undesired IED bowing profile. Ions with low energy are important for etch processes as they clean the mask surface and maintain the shape of the mask layer, preventing hole clogging. Some embodiments of the present disclosure are directed to creating an energy profile having a high-energy peak and a low energy peak, with little to no intermediate energy between the high and low energy peaks.

FIG. 3B is a graph illustrating an IED function (IEDF), in accordance with certain embodiments of the present disclosure. As shown, the IEDF includes a lower energy peak 301 and a higher energy peak 303. The energy associated with the low energy peak may be less than a few hundred eVs (e.g., less 1K eV), and the energy associated with the high-energy peak may be a few hundred eVs to tens of thousands eVs, depending on aspect ratio of the feature to be formed in substrate. For instance, in some cases, the energy associated with the high-energy peak may be between 4 k eV to 10 k eV. As shown, no ions exist (or at least fewer than conventional implementations) between the lower energy peak 301 and the higher energy peak 303. Some embodiments are directed to techniques for implementing the ion energy distribution shown in FIG. 3B using a PV waveform tailoring technique, as described in more detail herein.

FIG. 4A illustrates a PV waveform 400 generated using a waveform generator, in accordance with certain embodiments of the present disclosure. As shown, the PV waveform 400 includes waveform regions 401 and 405. The waveform region 401 includes a direct current (DC) signal, and the waveform region 405 includes a voltage staircase that can be used for ion current compensation.

During a portion of the waveform region 401 within a pulse waveform cycle, plasma bulk electrons are attracted to the surface of the substrate (e.g., substrate 103) due to the rising edge 402 of the PV waveform 400. As discussed above, the substrate surface and the electrode (e.g., bias electrode 104) form a capacitive element (e.g., referred to as an electrostatic chuck capacitor (C_esc)), which during this stage will cause an equal amount of positive charge on the electrode (e.g., as compared to the negative charge on the substrate) to cancel the field generated by the accumulation of electrons provided by the bulk plasma.

At the falling edge 403 of the PV waveform 400, the ions are neutralized by the electrons due to the application of the PV waveform 400 to the electrode. Therefore, a negative voltage V₀ is established at the electrode, and a negative DC sheath potential V_dc is established on the substrate surface. This is the origin of the higher energy peak 303. The DC sheath potential (V_dc), or the higher ion energy can be approximated using a voltage drop (ΔV) at the falling edge 403 and the ratio between C_esc and sheath capacitance (C_sheath) based on the equation:

$V_{dc}=\frac{C_{\mathrm{esc}}}{C_{\mathrm{esc}}+C_{\mathrm{sheath}}}\times \Delta V$

Thus, the waveform region 401 serves to sustain the plasma (e.g., while producing the lower energy peak 301) in the chamber and establish a DC sheath potential V_dc for the higher energy peak 303.

As incoming ions neutralize the electrons on the substrate surface and positive charges are accumulated on the substrate surface, the DC sheath potential V_dc decreases if there is no means of ion compensation. Consequently, ions incident onto the substrate surface will not be mono-energetic due to the change in the DC sheath potential. In an effort to compensate for the collection of the positive charge on the substrate during the ion current stage found within the waveform region 405, in some embodiments, a voltage staircase is applied to the electrode to compensate for the change in the sheath potential V_dc, thereby maintaining a constant sheath potential V_dc (mono-energy peak). In some embodiments, the voltage staircase, applied to the bias electrode 104 in the waveform region 405, is divided into two or more sub-steps, each having a time duration Δt that can be constant or varied between sub-steps. In the first sub-step 406, which has a time duration Δt, a total amount of positive charges AQ=I_ion×Δt is accumulated on the substrate surface, where the ion current (I_ion) can be calculated based on a time derivative of the electrode voltage (V) and the sheath capacitance (C_sheath) as

$I_{\mathrm{ion}}=C_{\mathrm{sheath}}\frac{\mathrm{dV}}{\mathrm{dt}},$ and thus the DC sheath potential V_dc decreases by ΔQ/C_sheath. To compensate this change in the DC sheath potential V_dc, a voltage drop ΔV_C at a falling edge 407 is applied, where the voltage drop ΔV_C is chosen as

$\Delta V_C=\Delta {Q\left(\frac{1}{C_{\mathrm{sheath}}}+\frac{1}{C_{\mathrm{esc}}}\right)}^{-1}=I_{\mathrm{ion}}\times \Delta t\times {\left(\frac{1}{C_{\mathrm{sheath}}}+\frac{1}{C_{\mathrm{esc}}}\right)}^{-1}.$ The required amount of voltage drop ΔV_C applied during one or more of the sub-steps of the voltage staircase can be determined from a known or measured ion current I_ion.

In some embodiments, the ion current I_ion that is used to determine the voltage drop ΔV_C for one or more of the sub-steps of the voltage staircase is pre-measured by applying a measurement waveform 399 (FIG. 4C) to the electrode. As shown in FIG. 4C, the measurement waveform 399 includes a waveform region 401 and a measurement region 419. The measurement waveform 399 is measured as it is provided to the electrode (e.g., bias electrode 104) by, first, applying a voltage pulse to form the waveform region 401. After the falling edge 403 is formed, the time decay of the electrode voltage is measured during the measurement region 419. The measurement waveform 399 can include one or more cycles that are used to calculate or estimate the uncompensated ion current due to the voltage decay (i.e., rate dV/dt) measured during at least a portion of the period of the measurement region 419, which is illustrated by curve 418. The output voltage at the end of the falling edge 403 is typically measured during this process so that it can be used as the reference voltage for the subsequent ion compensation stage found in the PV waveform 400 or 450.

Therefore, once the ion current I_ion has been determined the time duration Δt and voltage drop ΔV_C for each of the sub-steps are determined to compensate for the voltage decay created by the ion current during the ion current stage of the PV waveform 400 or 450. In general, the formed sub-steps will approximate a linear compensation curve, such as curve 411 in FIG. 4A, such that the portion of the waveform established at the substrate during plasma processing will include the square shaped region, illustrated by curve 230 in FIG. 2B, during the ion current stage of the PV waveform 400 or 450. One or more software algorithms within the system controller 126 can be used to measure and determine the ion current based on the measurement waveform 399 and also determine the characteristics (e.g., time duration Δt and voltage drop ΔV_C) of each of the sub-steps that are to be used within a PV waveform 400 or 450 to compensate for the ion current.

Once a desirable voltage drop ΔV_C is determined for a first sub-step 406, the voltage drop ΔV_C can be implemented by connecting the electrode to a first voltage source that is configured to apply a voltage of V₁=V₀−ΔV_C at the end of the first sub-step 406 (i.e., at the falling edge 407 of the of the waveform region 405). In some embodiments, the output of the first voltage source that is used to create the voltage drop ΔV_C is a fixed voltage. In other embodiments, the output voltage of the first voltage source is adjusted to a desired set point by a command signal provided from the system controller 126 based on the determined voltage drop ΔV_C.

Similarly, once a desirable voltage drop ΔV_C is determined for a second sub-step 408, the voltage drop ΔV_C can be implemented by connecting the electrode to a second voltage source that is configured to apply a voltage of V₂=V₁−ΔV_C at the end of the first sub-step 408 (i.e., at the falling edge 409 of the of the waveform region 405). In one embodiment, the voltage drop ΔV_C applied at the falling edge 409 has the same magnitude as the voltage drop ΔV_C applied at the falling edge 407, and thus voltage V₂=V₁−ΔV_C=V₀−2 ΔV_C. However, in some embodiments, it may be desirable for the magnitude of the voltage drop ΔV_C applied at the falling edge 409 to be different from the voltage drop ΔV_C applied at the falling edge 407. In some embodiments, the output of the second voltage source is set at a fixed voltage that is used to achieve the voltage drop ΔV_C. In other embodiments, the output voltage of the second voltage source is adjusted to a desired set point by a command signal provided from the system controller 126 based on the determined voltage drop ΔV_C.

It should be noted that although in the example shown in FIG. 4A includes two sub-steps 406 and 408 having an equal time duration Δt in the waveform region 405, the number n of the sub-steps in the waveform region 405 is not limited to two sub-steps. In some embodiments, with the PV waveform 400 having n sub-steps in the waveform region 405, the electrode is connected to a voltage source that can apply a voltage of V_L=V₀−(i−1)ΔV_C during the i-th sub-step (i=1, 2, . . . , n). In some embodiments, the number n of the sub-steps in the waveform region 405 is five or less. A time duration Δt_i can be different for each of the sub-steps (i=1, 2, n), in which case a voltage drop at the end of the i-th sub-step is determined by

$\Delta V_{C_i}=I_{\mathrm{ion}}\times \Delta t_i\times {\left(\frac{1}{C_{\mathrm{sheath}}}+\frac{1}{C_{\mathrm{esc}}}\right)}^{-1}.$

It should be also noted the above equation used to determine the voltage drop ΔV_C is for a case in which effects of parasitic capacitances or stray capacitances, transmission line inductance, or the like are not included, thus a voltage drop ΔV_C to compensate a change in the DC sheath potential due to positive charges accumulated at the substrate surface may be different when correcting factors based on different chamber designs and plasma conditions.

FIG. 5A illustrates an example implementation of a waveform generator 500 for biasing a substrate to achieve IED control, in accordance with certain embodiments of the present disclosure. In some embodiments, the waveform generator 500 is configured to generate the PV waveform 400 (FIG. 4A), which can be established at the bias electrode 104 or support base 107. However, the waveform generator 500 may be used to implement one or more of the waveform generator assemblies 150, described above with respect to FIG. 1.

The waveform generator 500 includes a main voltage source 502 (e.g., a DC voltage source) for implementing the positive voltage during the waveform region 401, a first compensation voltage source 505A (e.g., the first voltage source) and a second compensation voltage source 505B (e.g., the second voltage source) that are connected in parallel for implementing the voltage staircase during the waveform region 405. The waveform generator 500 generates the PV waveform 400 at an output node 504. In one example, the output node 504 is coupled to the bias electrode 104 in the substrate support 105 (e.g., ceramic puck) or the support base 107. If the output node 504 is coupled to the support base 107, the total capacitance C_total (e.g.

$\frac{1}{C_{\mathrm{total}}}=\frac{1}{C_{\mathrm{esc}}}+\frac{1}{C_{\mathrm{SB}}},$ where C_SB is the capacitance of the dielectric layer disposed between the support base 107 and the bias electrode 104) between the output node 504 and the substrate 103 will be greater than if the output node 504 is coupled to the bias electrode 104 (e.g., C_esc), which may result in a lower voltage drop across C_esc and more voltage drop on the sheath.

As shown in FIG. 5A, a switch 520 (e.g., a high voltage solid-state relay) is coupled between the main voltage source 502 and the output node 504, and a switch 522 (e.g., a high voltage solid-state relay) is coupled between a ground node 508 and the output node 504. A switch 523A and a switch 523B are coupled between the first compensation voltage source 505A and the output node 504, and between the second compensation voltage source 505B and the output node 504, respectively. While FIG. 5A illustrates a configuration that includes two compensation voltage sources that are used to form the voltage staircase, this configuration is not intended to be limiting as to the scope of the disclosure provided herein since the waveform generator 500 could include three or more waveform generators that are connected in parallel to form three or more sub-steps within the voltage staircase. As will be discussed further below, the timing of the opening and closing of the various switches can be controlled by commands sent from the system controller 126.

FIG. 5B illustrates an implementation of a waveform generator 580 for biasing a substrate to achieve IED control, in accordance with certain embodiments of the present disclosure. In one embodiment, the waveform generator 580 is configured to generate the PV waveform 400 (FIG. 4A), which can be established at the bias electrode 104 or support base 107. The waveform generator 580 may also be used to implement one or more of the waveform generator assemblies 150, described above with respect to FIG. 1.

The waveform generator 580 includes a main voltage source 502 (e.g., a DC voltage source) for implementing the positive voltage during the waveform region 401, a first compensation voltage source 505A (e.g., the first voltage source) and a second compensation voltage source 505B (e.g., the second voltage source) that are connected in series to allow for the implementation of the voltage staircase during the waveform region 405. The waveform generator 580 generates the PV waveform 400 at an output node 504. The output node 504 may be coupled to the bias electrode 104 in the substrate support 105 (e.g., ceramic puck) or the support base 107. As shown in FIG. 5B, a switch 520 (e.g., a high voltage solid-state relay) is coupled between the main voltage source 502 and the output node 504, and a switch 522 (e.g., a high voltage solid-state relay) is coupled between a ground node 508 and the output node 504. A switch 523A is coupled between a first port of the first compensation voltage source 505A and the output node 504. The second compensation voltage source 505B is coupled between a ground and a switch 523B. The switch 523B is configured to selectively couple a second port of the first compensation voltage source 505A to a ground node during the formation of the falling edge 407, and then serially couple the first port of the second compensation voltage source 505B to the second port of the first compensation voltage source 505A, thus coupling the second compensation voltage source 505B and the first compensation voltage source 505A together, during the formation of the falling edge 409. As will be discussed further below, the timing of the opening and closing of the various switches can be controlled by commands sent from the system controller 126. While FIG. 5B illustrates two series connected voltage sources to form the voltage staircase, this configuration is not intended to be limiting as to the scope of the disclosure provided herein since the waveform generator 580 could include three or more waveform generators that are connected in series to form three or more sub-steps within the voltage staircase. In a system configuration that includes three or more waveform generators, in the connection between each adjacent pair of waveform generators will include a two-position switch, which is similar to switch 523B shown in FIG. 5B, to allow the serial connection of each waveform generator to form each of sub-steps in the voltage staircase.

RF Overlay Configuration Example

FIG. 4B illustrates a PV waveform 450 generated using a waveform generator, in accordance with certain embodiments of the present disclosure. As shown, the PV waveform 450 includes waveform regions 451 and 455. The waveform region 451 includes a direct current (DC) signal overlaid with a RF signal 454, and the waveform region 455 includes a voltage staircase (e.g., for current compensation) overlaid with the RF signal 454. The RF signal 454 may also be overlaid on the voltage staircase signal during the waveform region 455 to continue sustaining the plasma (e.g., while producing the lower energy peak 301) in the chamber and establishing a DC sheath potential for the higher energy peak 303. It should be noted that although in the example shown in FIG. 4B includes two sub-steps 456 and 458 having an equal time duration Δt in the waveform region 455, the number n of the sub-steps in the waveform region 455 is not limited to two sub-steps, and thus could include more or less sub-steps.

The RF signal 454 is generally used to sustain the plasma in the chamber and produces the lower energy peak 301 described with respect to FIG. 3B. The RF signal 454 may have a frequency between 40 MHz to 200 MHz, in some embodiments. The frequency of the RF signal 454 may be higher than the ion sheath transit frequency, such as a frequency>40 MHz. In this case, the average ion transit time across the sheath thickness is longer than the period of the RF signal 454, resulting in the ions experiencing multiple cycles of RF signal 454 and obtaining the average energy associated with the multiple cycles to create the lower energy peak 301. Therefore, ions are accelerated by the average sheath potential caused by the RF signal 454 such that a single ion energy peak is achieved. The high-frequency RF excitation produces ions with a mono-energy peak. In other words, ions traveling across the sheath experience the average sheath potential driven by the RF signal 454, creating a single ion energy peak instead of a continuous energy distribution.

FIG. 5C illustrates an example implementation of a waveform generator 550 for biasing a substrate to achieve IED control, in accordance with certain embodiments of the present disclosure. In some embodiments, the waveform generator 550 is configured to generate the PV waveform 450 (FIG. 4B), which can be established at the bias electrode 104 or support base 107. The waveform generator 550 may be used to implement one or more of the waveform generator assemblies 150, described above with respect to FIG. 1.

The waveform generator 550 includes a main voltage source 502 (e.g., a DC voltage source) for implementing the positive voltage during the waveform region 401, a first compensation voltage source 505A (e.g., a DC voltage source) and a second compensation voltage source 505B (e.g., a DC voltage source) for implementing the voltage staircase during the waveform region 405, and an RF generator 506 (also referred to as an RF signal generator) for providing the RF signal 454. The waveform generator 550 generates the PV waveform 450 at an output node 504. The output node 504 may be coupled to the bias electrode 104 in the substrate support 105 (e.g., ceramic puck) or the support base 107.

In the embodiments illustrated in FIG. 5C, RF filter 540 may be implemented in a path between the main voltage source 502 and the switch 520, an RF filter 542 may be implemented in a path between the ground node 508 and switch 522, an RF filter 544A may be implemented between the first compensation voltage source 505A and the output node 504, and an RF filter 544B may be implemented between the second compensation voltage source 505B and the output node 504. The RF filters 540, 542, 544A, 544B may be implemented as low-pass filters configured to block the RF signal(s) provided from the RF generator 506. The main voltage source 502, the first compensation voltage source 505A, and the second compensation voltage source 505B are protected by respective RF filters 540, 544A, 544B from the output of the RF generator 506. In other words, the RF filters 540, 544A, 544B are configured to block the high-frequency RF signals provided from the RF generator 506. The ground node 508 is isolated from the RF generator 506 by the RF filter 542 (e.g., a low pass filter) when the switch 522 is closed. In some embodiments, each of the RF filters 540, 542, 544A, 544B may be implemented as a parallel LC topology, as shown in FIG. 6.

FIG. 6 illustrates a parallel LC filter topology 600 having a capacitive element 602 and an inductive element 604. As shown, the capacitive element 602 may be coupled in parallel to the inductive element 604 and between nodes 610, 612. Each of the RF filters 540, 542, 544 may be implemented using the parallel LC filter topology 600. For instance, for RF filter 542, the node 610 may be coupled to the ground node 508 and the node 612 may be coupled to switch 522. As one example, for a 40 MHz RF signal, the capacitive element 602 may be 100 pico-farads (pF) and the inductive element 604 may be 158 nano-henries (nH) to block the 40 MHz RF signal. In other words, the parallel LC filter topology 600 is a resonant circuit that effectively acts as an open circuit for a 40 MHz signal, isolating the main voltage source 502, the ground node 508, the first compensation voltage source 505A, or the second compensation voltage source 505B from the 40 MHz RF signal.

Waveform Generation Examples

FIG. 7 is a timing diagram 700 illustrating states of switch 520 (labeled as “S1”), switch 522 (labeled as “S2”), switch 523A (labeled as “S3”), and switch 523B (labeled as “S4”), in accordance with certain embodiments of the present disclosure. In general, during operation, the switches 520, 523A, 523B are not closed simultaneously with the switch 522 (S2) to avoid electrically shorting the main voltage source 502, the first compensation voltage source 505A, and/or the second compensation voltage source 505B to the ground node 508. While the discussion below primarily discloses a switch timing process that is performed on a system that includes a waveform generator 500 to form a PV waveform 400, this configuration is not intended to limiting as to the scope of the disclosure provided herein since the switch timing process could also be implemented on a system that includes a waveform generator 550 to form a PV waveform 450.

Referring to FIGS. 4A, 5A and 7, in some embodiments, during phase 1 of a waveform cycle (e.g., a cycle of PV waveform 400), switch 520 (S1) may be closed to produce the rising edge 402 as shown in FIG. 4A. Switch 520 (S1) may be closed for a period ranging from 20 ns to 2000 ns to allow enough number of electrons to be collected at the substrate surface. After the period associated with the waveform region 401, the switch 520 (S1) may be opened and the switch 522 (S2) may be closed, which connects the output node 504 to ground, to produce the falling edge 403 during phase 2 of the waveform cycle. After opening the switch 520 (S1), switch 522 (S2) may be closed for a time period ranging from 10 ns to 100 ns.

In some embodiments, during phase 1 while switch 520 (S1) is closed, a negative charge accumulates on the substrate 103 shown in FIG. 1. The voltage drop across the capacitor formed by the bias electrode 104 and the substrate 103 on the substrate 103 cannot change instantaneously due to capacitive effects. Thus, during phase 2, once switch 520 (S1) is opened and switch 522 (S2) is closed, the voltage at the output node 504 (e.g., at bias electrode 104 shown in FIG. 1) drops from a positive voltage to zero (ground potential) as shown in FIG. 4A as the switch 522 connects the bias electrode 104 to ground In other words, the positive charge on the bias electrode 104 attracts electrons from ground, causing the drop to the negative voltage V₀ at the substrate surface at the output node 504 upon closure of switch S2.

After the period (i.e., the time duration Δt) associated with the first sub-step 406 in the waveform region 405 is reached, the switch 522 (S2) may be opened and the switch 523A (S3) is closed to produce the falling edge 407 during phase 3 of the waveform cycle as shown in FIG. 4. After opening the switch 522 (S2), the switch 523A (S3) may be closed for a time period ranging from 100 ns to 2000 ns. During phase 3 of the waveform cycle, both switches 520, 522 remain open, and the switch 523A is closed to allow the first compensation voltage source 505A to be connected to the output node 504 (e.g., to the chamber).

After the period (i.e., the time duration Δt) associated with the sub-step 408 in the waveform region 405 is reached, the switch 523A (S3) may be opened and switch 523B (S4) may be closed to produce the falling edge 409 during phase 4 of the waveform cycle as shown in FIG. 4. In one embodiment, the magnitude of the output of the second compensation module 502B will equal to the magnitude of the voltage applied at the falling edge 407 plus the additional voltage needed to reach the additional voltage drop ΔV_C that is to be applied during the falling edge 409 (i.e., V₂=V₀−ΔV_C1−ΔV_C2). After opening the switch 523A (S3), switch 523B (S4) may be closed for a time period ranging from 100 ns to 2000 ns. During phase 4 of the waveform cycle, both switches 520, 522 remain open, and the switch 523B is closed.

In some embodiments in which the waveform generator 580 is implemented, the timing sequence illustrated in FIG. 7 is altered such that switch 523A (S3) will remain closed while switch 523B (S4) is used to couple the first compensation voltage source 505A and the second compensation voltage source 505B together during phase 4 of the waveform cycle. At the end of phase 4 the switch 523A is opened and switch 523B is switched to a position that connects the first compensation voltage source 505A to ground so that, or in preparation for, the waveform cycle to be repeated.

The embodiments of the present disclosure provide a process-favorable dual-peak IED and a method to achieve such IED on substrate surface for plasma processing chambers with simultaneous plasma excitation and sustainment. One advantage of embodiments of the present disclosure as compared to traditional ion energy control techniques is the simultaneous plasma generation and IED control. After one PV waveform cycle has been completed, a plurality of additional PV waveform cycles will be serially repeated multiple times, as illustrated in FIGS. 4A-4C by the partial illustration of the repeated second voltage waveform cycle. In some embodiments, voltage waveform established at the electrode has an on-time, which is defined as the ratio of the ion current time period (e.g., length of waveform region 405) and the waveform period T_P (e.g., length of waveform region 401+length of waveform region 405), is greater than 50%, or greater than 70%, such as between 80% and 95%. In some embodiments, a PV waveform that has a waveform cycle has a period T_P of about 2.5 μs is serially repeated within a PV waveform burst that has a burst period that is between about 100 microseconds (μs) and about 10 milliseconds (ms). The burst of PV waveforms can have a burst duty cycle that is between about 5%−100%, such as between about 50% and about 95%, wherein the duty cycle is the ratio of the burst period divided by the burst period plus a non-burst period (i.e., no PV waveforms are generated) that separates the burst periods.

FIG. 8 is a process flow diagram illustrating a method 800 for waveform generation. The method 800 may be performed by a waveform generation system including a waveform generator, such as the waveform generator 500, and/or a system controller such as the system controller 126.

At activity 802, the waveform generation system couples (e.g., by closing the switch 520) a main voltage source (e.g., main voltage source 502) to an output node (e.g., the output node 504) during a first phase (e.g., phase 1 shown in FIG. 7) of a PV waveform (e.g., PV waveform 400), for between about 20 ns and about 2000 ns. The output node may be coupled to an electrode disposed within a processing chamber (e.g., processing chamber 100). For example, the output node may be coupled to the bias electrode 104 or the support base 107.

At activity 804, the waveform generation system couples (e.g., by closing switch 522) a ground node (e.g., ground node 508) to the output node during a second phase (e.g., phase 2 shown in FIG. 7) of the waveform, for between about 10 ns and about 100 ns. As discussed above, the closing of switch 522 will thus cause the falling edge 403 to be formed.

At activity 806, the waveform generation system couples (e.g., by closing switch 523A) a first compensation voltage source (e.g., first compensation voltage source 505A) to the output node during a third phase (e.g., phase 3 shown in FIG. 7) of the waveform, for between about 100 ns and about 2000 ns. The closing of switch 523A and opening of switch 522 will thus cause the falling edge 407 to be formed.

At activity 808, the waveform generation system couples (e.g., by closing switch 523B) a second compensation voltage source (e.g., second compensation voltage source 505B) to the output node during a fourth phase (e.g., phase 4 shown in FIG. 7) of the waveform, for between about 100 ns and about 2000 ns. When using either the waveform generator 500 or waveform generator 550 configuration illustrated in FIG. 5A or 5C, the closing of switch 523B and opening of switch 523A will thus cause the falling edge 407 to be formed.

In some embodiments that include the waveform generator 550, an RF signal generator (e.g., RF generator 506) is coupled to the output node through a filter (e.g., high-pass filter 546) during the first phase. The RF signal generator may be coupled to the output node during the first phase, the second phase, the third phase, and the fourth phase of the waveform. The main voltage source and the ground node are decoupled (e.g., by opening switches 520, 522) from the output node during the third phase and the fourth phase. In some embodiments, the main voltage source is coupled to the output node through a filter (e.g., RF filter 540), and the ground node is coupled to the output node through a filter (e.g., RF filter 542).

In some embodiments, two or more compensation voltage sources (e.g., first compensation voltage source 505A and the second compensation voltage source 505B) are coupled to the output node during a third phase and a fourth phase, respectively, of the waveform, the main voltage source and the ground node being decoupled from the output node during the third and fourth phases. The first and second compensation voltage sources may be each coupled to the output node through a filter (e.g., RF filter 544).

The term “coupled” is used herein to refer to the direct or indirect coupling between two objects. For example, if object A physically touches object B and object B touches object C, then objects A and C may still be considered coupled to one another—even if objects A and C do not directly physically touch each other. For instance, a first object may be coupled to a second object even though the first object is never directly physically in contact with the second object.

While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

1. A waveform generator for generating a pulsed-voltage waveform for plasma processing, comprising: a main voltage source selectively coupled to an output node during a first phase of the generated pulsed-voltage waveform, wherein the output node is configured to be coupled to an electrode disposed within a processing chamber, andthe output node is selectively coupled to a ground node during a second phase of the generated pulsed-voltage waveform, subsequent to the first phase;a first compensation voltage source selectively coupled to the output node during a third phase of the generated pulsed-voltage waveform, subsequent to the second phase; anda second compensation voltage source selectively coupled to the output node during a fourth phase of the generated pulsed-voltage waveform, subsequent to the third phase.

2. The waveform generator of claim 1, further comprising: a first switch configured to couple the main voltage source to the output node during the first phase of the pulsed-voltage waveform;a second switch configured to couple the ground node to the output node during the second phase of the pulsed-voltage waveform; anda third switch configured to couple the first compensation voltage source to the output node during the third phase of the pulsed-voltage waveform.

3. The waveform generator of claim 2, further comprising: a fourth switch configured to couple the second compensation voltage source to the output node during the fourth phase of the pulsed-voltage waveform.

4. The waveform generator of claim 2, further comprising: a fourth switch configured to selectively couple the first compensation voltage to a ground during the third phase and to the second compensation voltage source to the output node during the fourth phase of the pulsed-voltage waveform.

5. The waveform generator of claim 1, further comprising: a radio frequency (RF) signal generator; anda first filter coupled between the RF signal generator and the output node.

6. The waveform generator of claim 5, further comprising: a second filter coupled between the ground node and the output node;a third filter coupled between the main voltage source and the output node;a fourth filter coupled between the first compensation voltage source and the output node; anda fifth filter coupled between the second compensation voltage source and the output node.

7. The waveform generator of claim 1, wherein the main voltage source, the first compensation voltage source, and the second compensation voltage source each comprise a direct current (DC) voltage source.

8. A method for generating a pulsed-voltage waveform, comprising: coupling a main voltage source to an output node during a first phase of generating a pulsed-voltage waveform, wherein the output node is coupled to an electrode disposed within a processing chamber;coupling a ground node to the output node during a second phase of the generated pulsed-voltage waveform, subsequent to the first phase;coupling a first compensation voltage source to the output node during a third phase of the generated pulsed-voltage waveform, subsequent to the second phase; andcoupling a second compensation voltage source to the output node during a fourth phase of the generated pulsed-voltage waveform, subsequent to the third phase.

9. The method of claim 8, further comprising coupling a first port of the first compensation voltage source to the ground node and coupling a second port of the output node during the third phase; andcoupling the first port of the first compensation voltage source to the second compensation voltage source during the fourth phase.

10. The method of claim 8, wherein the first phase of the generated pulsed-voltage waveform is between 20 ns and 2000 ns,the second phase of the generated pulsed-voltage waveform is between 10 ns and 100 ns,the third phase of the generated pulsed-voltage waveform is between 100 ns and 2000 ns, andthe fourth phase of the generated pulsed-voltage waveform is between 100 ns and 2000 ns.

11. The method of claim 8, wherein an RF signal generator is coupled to the output node during the first phase, the second phase, the third phase, and the fourth phase of the generated pulsed-voltage waveform.

12. The method of claim 11, wherein the RF signal generator is coupled to the output node through a first filter,the ground node is coupled to the output node through a second filter,the main voltage source is coupled to the output node through a third filter,the first compensation voltage source is coupled to the output node through a fourth filter, andthe second compensation voltage source is coupled the output node through a fifth filter.

13. The method of claim 11, wherein the main voltage source, the first compensation voltage source, and the second compensation voltage source each comprise a direct current (DC) voltage source.

14. An apparatus for waveform generation, comprising: an electrode of a process chamber;a main voltage source;a first compensation voltage source;a second compensation voltage source; anda non-volatile memory having program information stored therein, wherein the program information comprises a number of instructions which, when executed by a processor, causes the apparatus to: couple the main voltage source to the electrode during a first phase of a process of forming a pulsed-voltage waveform;couple the electrode to a ground node during a second phase of the pulsed-voltage waveform, subsequent to the first phase;couple the first compensation voltage source to the electrode during a third phase of the pulsed-voltage waveform, subsequent to the second phase; andcouple the second compensation voltage source to the electrode during a fourth phase of the pulsed-voltage waveform, subsequent to the third phase.

15. The apparatus of claim 14, wherein the instructions which, when executed by a processor, further causes the apparatus to: couple the first compensation voltage source to the ground node during the third phase; andcouple the first compensation voltage source to the second compensation voltage source during the fourth phase.

16. The apparatus of claim 14, wherein the first phase of the pulsed-voltage waveform is between 20 ns and 2000 ns,the second phase of the pulsed-voltage waveform is between 10 ns and 100 ns,the third phase of the pulsed-voltage waveform is between 100 ns and 2000 ns, andthe fourth phase of the pulsed-voltage waveform is between 100 ns and 2000 ns.

17. The apparatus of claim 14, further comprising an RF signal generator coupled to the electrode during the first phase, the second phase, the third phase, and the fourth phase of the pulsed-voltage waveform.

18. The apparatus of claim 17, wherein the RF signal generator is coupled to the electrode through a first filter,the ground node is coupled to the electrode through a second filter,the main voltage source is coupled to the electrode through a third filter,the first compensation voltage source is coupled to the electrode through a fourth filter, andthe second compensation voltage source is coupled the electrode through a fifth filter.

19. The apparatus of claim 14, wherein the main voltage source, the first compensation voltage source, and the second compensation voltage source each comprise a direct current (DC) voltage source.