Patent Grant
8237718
1. Field of the Invention
The present invention relates to the field of display screen technology. More specifically, embodiments of the present invention relate to flat panel display screens that are useful in conjunction with portable electronic devices.
2. Related Art
As the components required to build a computer system have reduced in size, new categories of computer systems have emerged. One of the new categories of computer systems is the “palmtop” computer system. A palmtop computer system is a computer that is small enough to be held in the hand of a user and can therefore be “palm-sized.” Most palmtop computer systems are used to implement various Personal Information Management (PIM) applications such as an address book, a daily organizer and electronic notepads, to name a few. Palmtop computers with PIM software have been know as Personal Digital Assistants (PDAs). Many PDAs have a small flat display screen associated therewith.
In addition to PDAs, small flat display screens have also been implemented within other portable electronic devices; such as cell phones, electronic pagers, remote control devices and other wireless portable devices.
Liquid crystal display (LCD) technology, as well as other flat panel display technologies, have been used to implement many of the small flat display screens used in portable electronic devices. These display screens contain a matrix of pixels, with each pixel containing subpixels for color displays. Some of the displays, e.g., color displays, use a back lighting element for projecting light through an LCD matrix. Other displays, e.g., black and white, use light reflectivity to create images through the LCD matrix and these displays do not need back lighting elements when used in lit surroundings. Whether color or in black and white, because the displays used in portable electronic devices are relatively small in area, every pixel is typically needed and used by the operating system in order to create displays and present information to the user. Additionally, because the display device is typically integrated together with the other elements of the portable electronic device, the operating systems of the portable electronic devices typically expect the display unit to have a standard pixel dimension, e.g., a standard array of (m×n) pixels is expected.
In an attempt to address this problem, some computer systems do not display edge-located characters to avoid the contrast problems associated with the screen edge. Many desktop computer systems, for example, simply try to avoid the display of edge-located characters on the cathode ray tube (CRT) screen or on a late flat panel display. However, this solution is not acceptable in the case of a small display screen where every pixel is needed for image and information presentation. What is needed is a display that makes maximal use of the available screen pixels while eliminating the problems associated with edge displayed characters in a display format where the pixels of the character are of the same or similar color as the edge region 28. What is also needed is a solution that is also compatible with standard display screen dimensions, formats and driver circuitry. Further, what is needed is a solution that controls the color of border pixels, yet simplifies the design and lowers the cost of displays by reducing and/or eliminating the dependency of border pixel control on separate timing components.
Accordingly, embodiments of the present invention provide an electronic device, e.g., a cell phone, portable computer system, PDA, electronic pager, etc., having a screen that makes maximal use of the available screen pixels while eliminating the problems associated with edge displayed characters in display formats where the pixels of the character are of the same or similar color as the edge region. Embodiments of the present invention are particularly useful in negative mode passive matrix LCD displays that utilize a brighter background and a darker foreground. Embodiments provide the above benefits while being compatible with standard display screen dimensions, formats and driver circuitry. Embodiments of the present invention therefore provide a small display screen with improved viewability, especially at the edge locations. Further, embodiments provide a solution that controls the color of border pixels, yet simplifies the design and lowers the cost of displays by reducing and/or eliminating the dependency of border pixel control on separate timing components. The present invention provides these advantages and others not specifically mentioned above but described in the sections to follow.
A display device is described herein having a display matrix including a pixel border of width x and located around the edge locations of the matrix for improved viewability. In particular, the border region can be several pixels wide, e.g., 1<x<5. In one embodiment, the border region is two pixels wide and surrounds a display region in which images are generated from a frame buffer memory. In one implementation, both the border region and the display region are implemented using a negative display mode passive display matrix using supertwisted nematic liquid crystal display (LCD) technology. Other passive matrix techniques could also be used in addition to LCD technology, such as, electronic paper, electronic ink, or microelectromechanical machine systems (MEMS), etc.
In one embodiment, the pixels of the border region are controllable between an on state and an off state and have an adjustable threshold voltage level. The threshold voltage level can originate from a gray scale bias circuit which can be controlled by a contrast adjustment. This allows the border brightness and the background brightness to be matched in response to contrast adjustments. In one embodiment, the display screen is a negative mode display in which the pixels are normally black when off. The pixel border is useful in providing contrast in display modes having a white background with black characters displayed therein. In these display modes, the border region is uniformly turned on to provide a white border. As discussed above, the white border adjusts with the background brightness in response to contrast adjustments. The present invention can be applied in either monochrome or color displays. The pixel border is also advantageous in that it can be used with conventional character generation processes of the operating system of the computer used to drive the display screen. In one embodiment, the novel display can be used within a portable computer system or other portable electronic device.
More specifically, an embodiment of the present invention includes a display unit (and a computer system including the display unit) comprising: a passive matrix of independently controllable pixels comprising n rows and m columns of discrete pixels, the passive matrix operable to generate an image in response to electronic signals driven from row and column drivers coupled to the passive matrix, the image representative of information stored in a frame buffer memory; and a pixel border having a predetermined width, the pixel border surrounding the passive matrix and comprising a plurality of pixels which are uniformly controlled between an on and an off state by a common threshold signal.
A display unit is constituted in one embodiment herein by a passive matrix of independently controllable pixels characterized by an active area of n rows and m columns of discrete pixels and a pixel border. In one embodiment, m and n are both 160. The passive matrix is operable to generate an image in response to electronic signals driven from row and column drivers coupled to it, representative of information stored in a frame buffer memory. The pixel border has a predetermined width, and surrounds the passive matrix active area. In one embodiment, the predetermined width is two pixels. The border pixel color state is controlled herein by the frame buffer memory. The pixel border color state is controlled to correspond to information contained in a locus of the frame buffer memory. This locus may be, in various embodiments herein, a single pixel, a row of pixels, or a number of rows of pixels of frame buffer memory. Each row of pixels may be equal to m and/or n, and may be 160. In one embodiment, the frame buffer controls the border pixels directly via a liquid crystal display controller and drivers, without a timing generation mechanism, such as a timing ASIC. In one embodiment, the display unit constitutes a part of a portable electronic device.
In one embodiment, a method of controlling the color of the border pixels constitutes a process including monitoring a locus within the frame buffer memory for information, determining a color for the border pixels corresponding thereto, generating a pixel border color signal corresponding to the color, transferring the pixel border color signal to the liquid crystal display controller, which generates a pixel border color writing signal and impels the drivers to write a color to the border pixels accordingly. The hardware abstraction layer monitors the frame buffer memory locus, determines the border pixel color, and generates the pixel border color signal. In one embodiment, impelling the drivers to write a color to the pixel border does not involve a timing synchronization mechanism external from the hardware abstraction layer.
In the following detailed description of the present invention, a controllable pixel border for a negative display mode passive matrix display screen which provides contrast improvement for increased viewability of edge-displayed characters, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be recognized by one skilled in the art that the present invention may be practiced without these specific details or with equivalents thereof. In other instances, well known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present invention.
The following co-pending US application is hereby incorporated by reference, Ser. No. 09/818,081, by Shawn Gettemy, Sherridythe Fraser, and David Lum, entitled “Controllable Pixel Border for a Negative Mode Passive Matrix Display Device,” filed Mar. 26, 2001, itself a continuation-in-part of co-pending U.S. application Ser. No. 09/709,142, by Canova, et al., entitled “Pixel Border For Improved Viewability of a Display Device,” filed Nov. 8, 2000 and which is also hereby incorporated by reference, both assigned to the assignee of the present invention.
Although the display screen of the present invention can be implemented in a variety of different electronic systems such as a pager, a cell phone, a remote control device, etc., one exemplary embodiment includes the integration of the display screen with a portable electronic device.
The digitizer 160 records both the (x, y) coordinate value of the current location of the stylus and also simultaneously records the pressure that the stylus exerts on the face of the digitizer pad. The coordinate values (spatial information) and pressure data are then output on separate channels for sampling by the processor 101 (
Also included in computer system 100 of
System 110 also includes an optional cursor control or directing device 107 coupled to the bus for communicating user input information and command selections to the central processor 101. In one implementation, device 107 is a touch screen device (also a digitizer) incorporated with screen 105. Device 107 is capable of registering a position on the screen 105 where the stylus makes contact and the pressure of the contact. The digitizer can be implemented using well known devices, for instance, using the ADS-7846 device by Burr-Brown that provides separate channels for spatial stroke information and pressure information.
The display device 105 utilized with the computer system 100 may be a liquid crystal device, cathode ray tube (CRT), field emission device (FED, also called fiat panel CRT) or other display device suitable for creating graphic images and alphanumeric characters recognizable to the user. Any of a number of display technologies can be used, e.g., LCD, FED, plasma, etc., for the flat panel display 105. In one embodiment, the display 105 is a flat panel multi-mode display capable of both monochrome and color display modes.
Signal communication device 108, also coupled to bus 99, can be a serial port (or USB port) for communicating with the cradle 60. In addition to device 108, wireless communication links can be established between the device 100 and a host computer system (or another portable computer system) using a Bluetooth wireless device 360, an infrared device 355, or a GSM radio device 240. Device 100 may also include a wireless modem device 240 and/or a wireless radio, e.g., a GSM wireless radio with supporting chipset. The wireless modem device 240 is coupled to communicate with the processor 101 but may not be directly coupled to port 108.
In one implementation, the Mobitex wireless communication system may be used to provide two way communication between system 100 and other networked computers and/or the Internet via a proxy server. In other embodiments, TCP protocol can be used or SMS can be used. System 100 of
It is appreciated that, in one embodiment, the digitizer region 106a and 106b are separate from the display screen 105 and therefore does not consume any display area.
Importantly, bus 54 is also coupled to a cradle 60 for receiving and initiating communication with a palm top (“palm-sized”) portable computer system 100 of the present invention. Cradle 60 provides an electrical and mechanical communication interface between bus 54 (and anything coupled to bus 54) and the computer system 100 for two way communications. Computer system 100 also contains various wireless communication mechanisms 64 for sending and receiving information from other devices, specifically a wireless modem 240 (
In one embodiment, the passive matrix technology used is negative mode display supertwisted nematic LCD technology. In negative mode display, the pixels are naturally black when in the off state and are bright when turned on.
Surrounding region 314 of
The pixel border region 312 is useful for giving contrast improvement for the viewability of edge located characters. In one implementation, the present invention uses negative mode display LCD in which the pixels are naturally black. Using this technology, in one display format, the background pixels are driven to be bright or white, while the foreground pixels (e.g., those that make up the characters in a text display) are darker or black. In this mode, the pixels of the pixel border 312 are generally displayed white to match the background pixel color. Specifically, the pixel border 312 is useful for giving contrast improvement for characters displayed along the edges, e.g., upper, lower, right and left, of region 314 (see
It is appreciated that if drivers are available to drive a matrix larger in size than the frame buffer region, then in this alternative case, the conventional drivers may be used to drive the pixels of the border region in accordance with the present invention. In this particular embodiment, the timing generator will supply the border data to the border pixels.
The display drivers 326 are coupled to the pixels within the display matrix 310. The display matrix 310 generates images by the modulation of light by discrete pixel elements. The display matrix 310 can be a passive-matrix liquid crystal display (LCD) technology but could also be of any passive display technology, as described above.
In passive LCD technology, the pixels comprise the intersection of one row line and one column line, e.g., the intersection of two electrodes, and typically does not include any active element. An exemplary pixel 460b of the matrix region 314 is shown and an exemplary pixel 460a of the border region 312 is shown. Pixel 460b is shown in more detail in
Driving signals are synchronized to meet, in time, at the intersection of a row and a column line to activate the respective pixel with a localized electric field, as is well known, to switch the pixel. The rows 420 of the frame buffer matrix 314 are scanned sequentially (according to synchronized row driver 422) from row 1 to row n to display a frame within region 314. Frames are generated from 30-50 Hz. For each row on-time, associated column data is shifted into the column drivers 410 by a column loader 412. In one example, the row on-time signal may be a square pulse for each column of data, from column 1 to column m. The column line then has its own pulse which depends on the gray scale of the pixel. However, the present invention may operate with any of the well known passive matrix driving schemes.
According to
As shown by the voltage transfer curve 810 for the negative mode display supertwisted nematic LCD of
The threshold driver circuits 430a and 430b of
Advantageously, circuit 610 of
By providing a white border region 312, the contrast along the left edge of the character, “A,” is much improved thereby improving viewability of the character. This advantageous result is achieved without any requirement of changing the operating system of the computer because the standard (m×n) pixel region 314 of the display remains unchanged. Furthermore, because the border pixels of region 312 have their own special driver circuitry, standard (m×n) driver circuits and software can be used with the present invention to generate images within region 314.
Exemplary Logical System
With reference now to
OS 1010 provides display control data to a hardware abstraction layer (HAL) 1020 whenever an application change is commanded, and/or whenever a display background color change is demanded. HAL 1020 functions as a translation stratum between the OS 1010 and various hardware components of the computer system; specifically, in the present implementation, the display functionality 315. In one embodiment, HAL 1020 also resides in portions of the CPU and memory. HAL 1020 translates display control commands, including border pixel control, originating in OS 1010 and writes them into its resident video frame buffer 320.
HAL 1020 transfers display control data, including control data for the border pixels, to LCD controller 322. LCD controller 1022 functions to control the information to be displayed on LCD matrix 310 accordingly. In one embodiment, LCD controller 322 exercises this control via a timing generator (e.g., timing generator 324;
In one embodiment, LCD controller 322 controls the display directly through row and column drivers 326(422) and 326(410). In the present embodiment, no ASIC or other timing generator is required. In another embodiment, LCD controller 322 controls the display by a combination of varying degrees of both direct control of the drivers under command of HAL 1020 and with ASIC 324.15 involvement.
Exemplary Single Memory Location Implementation
Referring now to
The actual memory capacity of frame buffer 320.16 is greater than m×n, e.g., in the present example, 160×160. A relatively large amount of memory content resides within frame buffer 320.16 and remains unused, unassigned, and unmapped. Such additional memory capacity within frame buffer 320.16 remains in memory locations therein unmapped, e.g., unassigned with respect to the OS control of active area display. Several embodiments of the present invention utilize one or more of these unmapped frame buffer memory locations to control the pixel border.
In the present embodiment, one unmapped, e.g., extra pixel 161 of memory content within frame buffer 320.16 (
Pixel 161 constitutes a single memory location within the frame buffer 320.16, and effectively constitutes a 161×1 frame buffer memory locus. A HAL (e.g., HAL 1020;
A timing generator, such as ASIC 324.15 (
The present implementation utilizes memory capacity of existing frame buffers to achieve the control over the border pixel color, without requiring utilization of the 160×160 or other m×n content reserved for applications of the OS (e.g., OS 1010;
Exemplary 160 Memory Location Implementation
With reference to
Pixel frame buffer 317.17 (
For example, each of the areas in video frame buffer 317.17 is mapped directly to the color of the columns constituting the pixel border area 312. The color of each constituent vertical line of the columns is replicated by a timing generator, such as ASIC 324.15 (
Advantageously, the present implementation requires a less sophisticated timing generation mechanism than in the implementation discussed above (e.g.,
In the present implementation, with respect to the active area 314.17 (
The ASIC or other timing generator function, with respect to controlling the border pixel color, is relatively simple. The ASIC or other timing generator merely replicates a full line, e.g., row, on the first two and last two rows of display 1700 (
Exemplary 640 Memory Location Implementation
Now with reference to
Importantly, in the present embodiment, display 314 is a liquid crystal module (LCM). Advantageously, the present implementation requires a less sophisticated timing generation mechanism than in either implementation discussed above (e.g.,
In the present implementation, a HAL (e.g., HAL 1020;
Active area 314.18 is depicted as having upper and lower halves. Memory locations across each horizontal row 161, 162, 163, and 164 in the frame buffer 320.18 replicate the color of vertical lines 1 through 160 constituting the vertical pixelation of active area 314.18 (
Thus, frame buffer locations 163 and 164 replicate, e.g., duplicate, in the border area 312 the pixel color found in column 1 of the active area 314.18. Correspondingly, frame buffer locations 161 and 162 replicate, e.g., duplicate, in the border area 312 the pixel color found in column 160 of the active area 314.18. ASIC (e.g., ASIC 324.15;
In one embodiment, duplication of the colors in border pixel area 312 is carried through each edge constituting a fourth of border pixel area 312; e.g., pixel 160b is duplicated and replicated down the entire right border of border pixel region 312 and pixel 1b is duplicated and replicated down the entire left border of border pixel region 312.
In one embodiment, the duplication is carried through only half of each edge constituting a fourth of border pixel area 312; e.g., pixel 160b is duplicated and replicated down the top half of the right border of border pixel region 312 and pixel 1b is duplicated and replicated down the top half of the left border of border pixel region 312. Correspondingly, in the present embodiment, pixel 160x is duplicated and replicated up the bottom half of the right border of border pixel region 312 and pixel 1x is duplicated and replicated up the bottom half of the left border of border pixel region 312. Other embodiments may utilize and/or combine any other permutations of this pixel replication and duplication scheme. For example, one embodiment applies replication and duplication of pixel 1b down the entire left side and replication and duplication of pixel 160x up the entire right side. In another embodiment, one edge utilizes duplication along the entire side, with the opposite edge utilizing duplication of halves, bottom-up and top-down.
The mapping of pixels in the border area 312 to the content of frame buffer 320.18 memory rows 161 through 163 requires a relatively sophisticated, complex coding. However, these coding requirements are met totally within the HAL, which in the present implementation bears adequate heretofore unused capacity to handle the corresponding coding burden. Advantageously, neither the timing ASIC or other timing generator nor the LCD drivers, are burdened by these mapping and coding tasks. Accordingly, within the present embodiment, the timing ASIC may be simpler, cheaper, less demanding of power and computational resources (e.g., and/or correspondingly more functional in other useful aspects).
Exemplary All-HAL Control Implementation
With reference to
Importantly, in the present embodiment, control of each and every border pixel in border area 312 is effectuated through the HAL, via its frame buffer 320.20, with no timing ASIC or other timing generator necessary. Advantageously, dispensing with a timing ASIC or other timing generator increases both power and computational efficiency, and reduces unit costs. In the present embodiment, display 314 is a liquid crystal module (LCM).
With reference now to
OS 1010 provides display control data to a hardware abstraction layer (HAL) 1020 whenever an application change is commanded, and/or whenever a display background color change is demanded. HAL 1020 functions as a translation stratum between the OS 1010 and various hardware components of the computer system; specifically, in the present implementation, the display functionality 319. In one embodiment, HAL 1020 also resides in portions of the CPU and memory. HAL 1020 translates display control commands, including border pixel control, originating in OS 1010 and writes them into its resident video frame buffer 320.
HAL 1020 transfers display control data, including control data for the border pixels, to LCD controller 322. LCD controller 1022 functions to control the information to be displayed on LCD matrix 310 accordingly. HAL achieves this control by generating signals that control the LCD matrix 310 by triggering its row and column drivers 326(422) and 326(410). In the present embodiment, LCD controller 322 controls the display directly through row and column drivers 326(422) and 326(410); no ASIC or other timing generator is required.
In the present implementation, HAL 1020 reads information contained in four (4) single pixel wide 160 pixels content rows within its frame buffer 320.20 and commands LCD drivers 326(410), 326(420) directly. The LCD driver controls the color of each pixel in the rows and columns 312 (
Active area 314.20 is depicted as having upper and lower halves. Memory locations across each horizontal row 161, 162, 163, and 164 in the frame buffer 320.20, unmapped with respect to the active area 314.20, replicate the color of vertical lines 1 through 160 constituting the vertical pixelation of active area 314.20 (
Thus, frame buffer locations 163 and 164 replicate, e.g., duplicate, in the border area 312 the pixel color found in column 1 of the active area 314.20. Correspondingly, frame buffer locations 161 and 162 replicate, e.g., duplicate, in the border area 312 the pixel color found in column 160 of the active area 314.20. HAL 1020 then replicates the same color vertically in the entire vertical border columns 163 and 164 to the left of active area 314.20, and in the entire vertical border columns 161 and 162 to the right of active area 314.20. Horizontal border pixel rows (a) and (b), and (x) and (y), respectively above and below active area 317.20, duplicate the color in the corresponding active area pixels 1 through 160, immediately adjacent to the border pixels in horizontal rows (b) and (x).
In one embodiment, duplication of the colors in border pixel area 312 is carried through each edge constituting a fourth of border pixel area 312; e.g., pixel 160b is duplicated and replicated down the entire right border of border pixel region 312 and pixel 1b is duplicated and replicated down the entire left border of border pixel region 312.
In one embodiment, the duplication is carried through only half of each edge constituting a fourth of border pixel area 312; e.g., pixel 160b is duplicated and replicated down the top half of the right border of border pixel region 312 and pixel 1b is duplicated and replicated down the top half of the left border of border pixel region 312. Correspondingly, in the present embodiment, pixel 160x is duplicated and replicated up the bottom half of the right border of border pixel region 312 and pixel 1x is duplicated and replicated up the bottom half of the left border of border pixel region 312. Other embodiments may utilize and/or combine any other permutations of this pixel replication and duplication scheme. For example, one embodiment applies replication and duplication of pixel 1b down the entire left side and replication and duplication of pixel 160x up the entire right side. In another embodiment, one edge utilizes duplication along the entire side, with the opposite edge utilizing duplication of halves, bottom-up and top-down.
The mapping of pixels in the border area 312 to the content of frame buffer 320.20 memory rows 161 through 163 requires a relatively sophisticated, complex coding. However, these coding requirements are met totally within the HAL 1020, which in the present implementation bears adequate heretofore unused capacity to handle the corresponding coding burden. Advantageously, the LCD controller 322 are not burdened in any way by these mapping and coding tasks. Accordingly, within the present embodiment, the HAL makes use of otherwise unused capacity, increasing the efficiency and economy of each unit.
Exemplary Method
Referring to
Beginning with step 2110, a HAL (e.g., HAL 1020;
In step 2120, the HAL determines a color for pixels constituting the border (e.g., border pixels 312;
In step 2130, it is determined whether the HAL will require external synchronization to transfer border pixel data for display upon the pixels constituting the border, or whether the HAL will perform such synchronization internally.
If it is determined (step 2130) that no such synchronization external to the HAL is required, e.g., wherein the HAL performs any required synchronization internally, process 2100 proceeds via step 2140, wherein the HAL transfers border pixel data, in the form of the border pixel color signal, via an LCD controller (e.g., LCD controller 322;
If it is determined (step 2130) that synchronization external to the HAL is required, process 2100 proceeds via step 2145, wherein the HAL transfers border pixel data, in the form of the border pixel color signal, via an LCD controller (e.g., LCD controller 322;
The ASIC or other timing generator synchronizes the data with the visual information formatted by the OS (e.g., for control of the active area information display), generates a corresponding border pixel color writing signal, and transfers the data, in the form of the border pixel color writing signal, to the LCD drivers; step 2146.
In the event that the HAL performed any requisite synchronization internally, the border pixel color writing signal is generated by the LCD controller in response to the HAL transferring a border pixel color signal to the LCD controller (step 2140).
Whether the border pixel color writing signal is generated by the LCD driver in direct response to the HAL transferring a border pixel color signal (step 2140), or whether the border pixel color writing signal is generated by the ASIC or other timing mechanism, external to the HAL (step 2146), the LCD drivers are impelled by the border pixel color writing signal to write color data to the border pixels (e.g., border pixels 312;
In summary, a display unit is constituted in one embodiment herein by a passive matrix of independently controllable pixels characterized by an active area of n rows and m columns of discrete pixels and a pixel border. In one embodiment, m and n are both 160. The passive matrix is operable to generate an image in response to electronic signals driven from row and column drivers coupled to it, representative of information stored in a frame buffer memory. The pixel border has a predetermined width, and surrounds the passive matrix active area. In one embodiment, the predetermined width is two pixels. The border pixel color state is controlled herein by the frame buffer memory. The pixel border color state is controlled to correspond to information contained in a locus of the frame buffer memory. This locus may be, in various embodiments herein, a single pixel, a row of pixels, or a number of rows of pixels of frame buffer memory. Each row of pixels may be equal to m and/or n, and may be 160. In one embodiment, the frame buffer controls the border pixels directly via a liquid crystal display controller and drivers, without a timing generation mechanism, such as a timing ASIC. In one embodiment, the display unit constitutes a part of a portable electronic device.
In one embodiment, a method of controlling the color of the border pixels constitutes a process including monitoring a locus within the frame buffer memory for information, determining a color for the border pixels corresponding thereto, generating a pixel border color signal corresponding to the color, transferring the pixel border color signal to the liquid crystal display controller, which generates a pixel border color writing signal and impels the drivers to write a color to the border pixels accordingly. The hardware abstraction layer monitors the frame buffer memory locus, determines the border pixel color, and generates the pixel border color signal. In one embodiment, impelling the drivers to write a color to the pixel border does not involve a timing synchronization mechanism external from the hardware abstraction layer.
The preferred embodiment of the present invention, an apparatus and method for achieving a controllable, variable color pixel border for a negative display mode display screen with a passive matrix drive, is thus described. While the present invention has been described in particular embodiments, it should be appreciated that the present invention should not be construed as limited by such embodiments, but rather construed according to the below claims.
The present application is a continuation application of U.S. application Ser. No. 10/980,133, now U.S. Pat. No. 7,724,270, by David Lum and Yichang Chang, filed Nov. 1, 2004, which is hereby incorporated by reference and which itself is a continuation of U.S. application Ser. No. 10/087,369, now U.S. Pat. No. 6,831,662, by David Lum and Yichang Chang, filed Feb. 28, 2002, which is hereby incorporated by reference and which itself is a continuation-in-part application of U.S. application Ser. No. 09/818,081, now U.S. Pat. No. 7,425,970, by Shawn Gettemy, Sherridythe Fraser, and David Lum, filed Mar. 26, 2001 and which is hereby incorporated by reference, and which itself is a continuation-in-part of U.S. application Ser. No. 09/709,142, now U.S. Pat. No. 6,961,029, by Canova, et al., filed Nov. 8, 2000 and which is also hereby incorporated by reference. The incorporated referenced applications are assigned to the assignee of the present invention.
| Number | Name | Date | Kind |
|---|---|---|---|
| 6154225 | Kou et al. | Nov 2000 | A |
| 6288704 | Flack et al. | Sep 2001 | B1 |
| Number | Date | Country |
|---|---|---|
| EP 0 394 814 | Apr 1990 | FR |
| Number | Date | Country | |
|---|---|---|---|
| 20110316867 A1 | Dec 2011 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 10980133 | Nov 2004 | US |
| Child | 12787315 | US | |
| Parent | 10087369 | Feb 2002 | US |
| Child | 10980133 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 09818081 | Mar 2001 | US |
| Child | 10087369 | US | |
| Parent | 09709142 | Nov 2000 | US |
| Child | 09818081 | US |
