Claims
- 1. A memory device, comprising:
a digit line pair; a voltage generator, operatively coupled to the digit line pair, that charges voltages on the digit line pair to Vcc/2 after an initial power on condition has been completed; and a circuit, operatively coupled to the digit line pair and distinct from the voltage generator, which has a higher current carrying capacity than the voltage generator, and which is activatable during the initial power on condition of the memory device to equilibrate voltages on the digit line pair to Vcc/2.
- 2. The memory device of claim 1, wherein the circuit comprises:
a sense amplifier that drives the digit line pair to opposite rails upon an occurrence of an internal pulse received during the initial power on condition; and an equilibration circuit that equilibrates voltages on the digit line pair to Vcc/2 upon the occurrence of the internal pulse during the initial power on condition.
- 3. The memory device of claim 1, further comprising:
an internal row address signal (RAS) generator, coupled to the circuit, operable to produce an internal RAS in response to the initial power on condition; and wherein the circuit includes
a sense amplifier that upon an occurrence of the internal RAS pulse during the initial power on condition drives the digit line pair to opposite rails, and an equilibration circuit that upon the occurrence of the internal RAS pulse during the initial power on condition equilibrates voltages on the digit line pair to Vcc/2 and permits a common capacitor plate to charge to Vcc/2.
- 4. The memory device of claim 1, wherein the memory device is a dynamic random access memory (DRAM).
- 5. A memory device, comprising:
a digit line pair; a signal generator operable to produce a pulse in response to an initial power on condition; a sense amplifier, operatively coupled to the digit line pair, that is activatable by the pulse during the initial power on condition of the memory device to drive the digit line pair to opposite rails; and an equilibration circuit, operatively coupled to the digit line pair, that is activatable by the pulse during the initial power on condition to equilibrate voltages on the digit line pair to Vcc/2 and to permit a common capacitor plate to charge to Vcc/2.
- 6. The memory device of claim 5, wherein the signal generator includes an internal row address signal (RAS) generator, which is operable to produce the pulse as an internal RAS in response to the initial power on condition.
- 7. The memory device of claim 5, wherein the memory device is a dynamic random access memory (DRAM).
- 8. A computer comprising:
a microprocessor; and a memory device, coupled to the microprocessor, which includes
a digit line pair, a voltage generator, operatively coupled to the digit line pair, that charges voltages on the digit line pair to Vcc/2 after an initial power on condition has been completed, and a circuit, operatively coupled to the digit line pair and distinct from the voltage generator, which has a higher current carrying capacity than the voltage generator, and which is activatable during the initial power on condition of the memory device to equilibrate voltages on the digit line pair to Vcc/2.
- 9. The computer of claim 8, wherein the circuit comprises:
a sense amplifier that drives the digit line pair to opposite rails upon an occurrence of an internal pulse received during the initial power on condition; and an equilibration circuit that equilibrates voltages on the digit line pair to Vcc/2 upon the occurrence of the internal pulse during the initial power on condition.
- 10. The computer of claim 8, wherein the memory device further comprises:
an internal row address signal (RAS) generator, coupled to the circuit, operable to produce an internal RAS in response to the initial power on condition; and wherein the circuit includes
a sense amplifier that upon an occurrence of the internal RAS pulse during the initial power on condition drives the digit line pair to opposite rails, and an equilibration circuit that upon the occurrence of the internal RAS pulse during the initial power on condition equilibrates voltages on the digit line pair to Vcc/2 and permits a common capacitor plate to charge to Vcc/2.
- 11. The computer of claim 8, wherein the memory device is a dynamic random access memory (DRAM).
- 12. A computer comprising:
a microprocessor; and a memory device, coupled to the microprocessor, which includes
a digit line pair, a signal generator operable to produce a pulse in response to an initial power on condition, a sense amplifier, operatively coupled to the digit line pair, that is activatable by the pulse during the initial power on condition of the memory device to drive the digit line pair to opposite rails, and an equilibration circuit, operatively coupled to the digit line pair, that is activatable by the pulse during the initial power on condition to equilibrate voltages on the digit line pair to Vcc/2 and to permit a common capacitor plate to charge to Vcc/2.
- 13. The computer of claim 12, wherein the signal generator includes an internal row address signal (RAS) generator, which is operable to produce the pulse as an internal RAS in response to the initial power on condition.
- 14. The computer of claim 12, further comprising a voltage generator operatively coupled to the digit line pair.
- 15. The computer of claim 14, wherein the sense amplifier and the equilibration circuit have a higher current carrying capacity than the voltage generator.
- 16. The computer of claim 12, wherein the memory device is a dynamic random access memory (DRAM).
- 17. A computer comprising:
a microprocessor; and a dynamic random access memory (DRAM), coupled to the microprocessor, which includes
a clock controller; an address decoder operatively coupled to the clock controller; an I/O circuit operatively coupled to the clock controller and address decoder; and a memory array, operatively coupled to the I/O circuit and the address decoder, comprising:
digit line pair; an internal row address signal (RAS) generator operable to produce an internal RAS in response to an initial power on condition; a sense amplifier that upon an occurrence of the internal RAS pulse during the initial power on condition drives the digit line pair to opposite rails; and an equilibration circuit that upon the occurrence of the internal RAS pulse during the initial power on condition equilibrates voltages on the digit line pair to Vcc/2 and permits a common capacitor plate to charge to Vcc/2.
- 18. The computer of claim 17, further comprising a voltage generator operatively coupled to the digit line pair.
- 19. The computer of claim 18, wherein the sense amplifier and the equilibration circuit have a higher current carrying capacity than the voltage generator.
- 20. A computer comprising:
a microprocessor; and a dynamic random access memory (DRAM), coupled to the microprocessor, which includes
a clock controller; an address decoder operatively coupled to the clock controller; an I/O circuit operatively coupled to the clock controller and address decoder; and a memory array, operatively coupled to the I/O circuit and the address decoder, comprising:
a voltage generator for providing a stable Vcc/2; a digit line pair; a sense amplifier that upon an occurrence on an internally generated RAS pulse during initialization of the DRAM drives the digit line pair to opposite rails; and an equilibration circuit that upon the occurrence of the internal RAS pulse during the initial power on condition equilibrates voltages on the digit line pair to Vcc/2 to assist the voltage generator in charging a common capacitor plate to Vcc/2 so that the DRAM is enabled for normal operation.
- 21. The computer of claim 20, wherein the sense amplifier and the equilibration circuit have a higher current carrying capacity than the voltage generator.
- 22. A computer comprising:
a microprocessor; and a dynamic random access memory (DRAM), coupled to the microprocessor, which includes
a clock controller; an address decoder operatively coupled to the clock controller; an I/O circuit operatively coupled to the clock controller and address decoder; and a memory array, operatively coupled to the I/O circuit and the address decoder, the memory array comprising:
a digit line pair; an internal row address signal (RAS) generator operable to produce an internal RAS pulse in response to an initial power on condition; a sense amplifier constructed and arranged for driving the digit line pair to opposite rails upon an occurrence of the internal RAS pulse during the initial power on condition; and an equilibration circuit that upon the occurrence of the internal RAS pulse during the initial power on condition equilibrates voltages on the digit line pair to a first equilibrated voltage and permits a common capacitor plate to charge to the first equilibrated voltage.
- 23. The computer of claim 22, further comprising a voltage generator operatively coupled to the digit line pair.
- 24. The computer of claim 23, wherein the sense amplifier and the equilibration circuit have a higher current carrying capacity than the voltage generator.
Parent Case Info
[0001] This application is a Continuation of U.S. application Ser. No. 09/629,306, filed Jul. 31, 2000, which is a Continuation of U.S. application Ser. No. 08/858,532, filed May 19, 1997, now U.S. Pat. No. 6,115,307.
Continuations (2)
|
Number |
Date |
Country |
Parent |
09629306 |
Jul 2000 |
US |
Child |
10224950 |
Aug 2002 |
US |
Parent |
08858532 |
May 1997 |
US |
Child |
09629306 |
Jul 2000 |
US |