Apparatus for and method of processing data

Abstract

Disclosed herein is a data processing apparatus for processing a plurality of input signals to increase the number of bits thereof to disperse 0s and 1s therein and thereafter converting the input signals into a serial signal, including signal generating means for generating the serial signal having a second bit rate which is represented by the product of a first bit rate of the input signals, the number of the input signals, and a ratio of a bit length after the number of bits is increased to a bit length before the number of bits is increased.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a communication system which incorporates a signal processing apparatus according to an embodiment of the present invention;

FIG. 2 is a block diagram of the signal processing apparatus shown in FIG. 1;

FIG. 3 is a diagram showing data formats by the signal processing apparatus shown in FIG. 1 while it is in operation;

FIG. 4 is a diagram showing data formats by the signal processing apparatus shown in FIG. 1 while it is in operation;

FIGS. 5A and 5B are diagrams showing formats of serial signals output from the signal processing apparatus shown in FIG. 1;

FIG. 6 is a block diagram of a signal processing apparatus according to a modification of the present invention; and

FIG. 7 is a format of a signal used by the signal processing apparatus shown in FIG. 6.

Claims

1. A data processing apparatus for processing a plurality of input signals to increase the number of bits thereof to disperse 0s and 1s therein and thereafter converting the input signals into a serial signal, comprising signal generating means for generating said serial signal having a second bit rate which is represented by the product of a first bit rate of said input signals, the number of said input signals, and a ratio of a bit length after said number of bits is increased to a bit length before said number of bits is increased.

2. The data processing apparatus according to claim 1, wherein said signal generating means comprises: a plurality of data processing means for processing said plurality of input signals, respectively; andserial signal generating means for generating said serial signal;wherein each of said data processing means includes inserting means for, before a fist data sequence of the input signal is bit-extended, inserting synchronizing data of a predetermined pattern which is not generated by bit-extending said fist data sequence, into said fist data sequence, andextending means for extending said first data sequence with said synchronizing data inserted therein by said inserting means to disperse 0s and 1s therein for thereby generating a second data sequence, andsaid serial signal generating means generates said serial signal having said second bit rate from a plurality of said second data sequences generated respectively by said plurality of data processing means.

3. The data processing apparatus according to claim 2, wherein said synchronizing data comprises 16-bit word synchronization data, and said extending means includes means for performing an 8B/10B conversion process on said first data sequence.

4. The data processing apparatus according to claim 1, wherein said second bit rate is 3.7125 Gb/s or 4.25 Gb/s.

5. A method of processing a plurality of input signals to increase the number of bits thereof to disperse 0s and 1s therein and thereafter converting the input signals into a serial signal, comprising the step of generating said serial signal having a second bit rate which is represented by the product of a first bit rate of said input signals, the number of said input signals, and a ratio of a bit length after said number of bits is increased to a bit length before said number of bits is increased.

6. The method according to claim 5, wherein said step of generating said serial signal comprises the steps of: processing said plurality of input signals, respectively; andgenerating said serial signal;wherein each of said steps of processing said input signals includes the steps of before a fist data sequence of the input signal is bit-extended, inserting synchronizing data of a predetermined pattern which is not generated by bit-extending said fist data sequence, into said fist data sequence, andextending said first data sequence with said synchronizing data inserted therein to disperse 0s and 1s therein for thereby generating a second data sequence, andsaid step of generating said serial signal includes the step of generating said serial signal having said second bit rate from a plurality of said second data sequences generated respectively by said steps of processing said plurality of input signals.

7. The method according to claim 6, wherein said synchronizing data comprises 16-bit word synchronization data, and said step of extending said first data sequence includes the step of performing an 8B/10B conversion process on said first data sequence.

8. The method according to claim 5, wherein said second bit rate is 3.7125 Gb/s or 4.25 Gb/s.

9. A data processing apparatus for processing a plurality of input signals to increase the number of bits thereof to disperse 0s and 1s therein and thereafter converting the input signals into a serial signal, comprising a signal generating section configured to generate said serial signal having a second bit rate which is represented by the product of a first bit rate of said input signals, the number of said input signals, and a ratio of a bit length after said number of bits is increased to a bit length before said number of bits is increased.