Apparatus for biasing ultra-low voltage logic circuits

Abstract

An apparatus for biasing ultra-low voltage logic circuits is disclosed. An integrated circuit device includes multiple transistors and a global body bias circuit. The global body bias circuit includes a first transistor and second transistors connected in series between a power supply and a second power supply or ground. The gate and source of the first transistor are connected to the first power supply. The gate and source of the second transistor are connected to the second power supply. The drains and bodies of the first and second transistors are connected together to form an output connected to the bodies of the other transistors within the integrated circuit device.

Description

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates to integrated circuit devices in general, and in particular to an apparatus for biasing logic circuits within integrated circuit devices. Still more particularly, the present invention relates to an apparatus for biasing ultra-low voltage logic circuits within an integrated circuit device.

2. Description of the Prior Art

Metal-oxide semiconductor field-effect transistors (MOSFETs) are commonly found in integrated circuit devices. A MOSFET includes a gate, a source, and a drain. The flow of charge carriers through a channel between the source and drain can be controlled by applying a voltage at the gate of a MOSFET. A depletion-mode MOSFET includes a doped or conducting channel under a gate even when no voltage is applied to the gate. An enhancement-mode MOSFET, in contrast, requires a gate-to-source bias voltage be applied in order to generate an inversion layer to serve as a conducting channel. Such bias voltage is known as a threshold voltage, V t . A positive voltage between the gate and source is required to induce a strong channel for an N-channel enhancement-mode MOSFET. As for a P-channel enhancement-mode MOSFET, current flows when the gate-to-source voltage is negative below the negative threshold voltage of the P-channel enhancement-mode MOSFET.

However, even when the gate voltage is less than the threshold voltage, a current, commonly referred to as a subthreshold current, still exists within the channel and its value is given by I DS (V GS )=(W/L) I 0 10 −(Vg−Vt)/s , where V GS is a gate voltage with respect to a source, I 0 is a constant approximately equals to 300 nA for N-channel MOSFETs and 70 nA for P-channel MOSFETs, s is the subthreshold swing ˜80 mV/decade, V t is the threshold voltage, and W and L are the electrical width and length of a MOSFET, respectively.

The threshold voltage of an enhancement-mode MOSFET is determined by several intrinsic factors, such as channel length, channel width, doping, gate oxide thickness, etc. Extrinsic factors, such as ambient temperature, can also affect the threshold voltage. Furthermore, the threshold voltage is strongly influenced by the voltage applied to the substrate or well (or generally known as the body) of a MOSFET in that a more positive bias will lead to a less positive threshold voltage. If the threshold voltage of a transistor is too low, the transistor may have an unacceptable amount of leakage current when the actual supply voltage is greater than the desired supply voltage. Conversely, if the threshold voltage of a transistor is too high, then there is a reduced likelihood that the transistor will be fully turned on. Although many aspects of a semiconductor manufacturing process can be controlled, there is still a wide variation of threshold voltage values among all the many transistors within an integrated circuit device.

The switching power dissipated by complementary-metal oxide semiconductor (CMOS) circuits is given by P active =C×V dd 2×f, where C is the capacitance of switching nodes, V dd is the power supply voltage, and f is the frequency of the nodes switching. In many applications, it is desirable to reduce the switching power to either preserve power due to power supply limitations, or to reduce heating due to various cooling constraints. To this end, the switching power may be reduced by either reducing the capacitance, the frequency, or the operating voltage. Capacitance reductions are often limited by process and manufacturing constraints such as lithographic resolution and tolerances. The frequency often represents a desired output of the circuits and, as such, a reduction may prove a serious compromise to the desired end of a logic circuit. Thus, the power supply voltage remains a key variable that can allow for the reduction of active power.

Subthreshold logic, in which CMOS circuits are operated at V dd <V t , has been an approach used for ultra-low power CMOS circuits where speed is not critical and V dd can be reduced to approximately one volt. In principle, CMOS logic circuits can maintain stable operation to as low as V dd =4ηkT/Q e , where h is an ideality, typically ˜1.4, and is affected by process details of the MOSFETs involved, k is the Boltzmann's constant, Q e is the elementary charge of the electron, and T is the ambient temperature in Kelvin. In practice, however, CMOS logic circuits can operate at or nearby the above-mentioned limit only when the OFF currents of N-channel and P-channel MOSFETs, I off -N and I off -P, respectively, are very nearly equal to each other.

CMOS processing involves the use of independent doping steps for N-type and P-type MOSFETs as well as other process variables, which result in variation in the V t s and in turn the I off s of the N-type and P-type MOSFETs independent of one another. Thus, even when a process is devised to provide I off -N=I off -P nominally, there will be significant variations from one wafer to another which, in turn, limits the minimum V dd at which such logic circuits fabricated in such a process will function. Consequently, it is desirable to provide a practical means of ensuring I off -N=I off -P by providing appropriate N-well and substrate biases in order to allow operation of CMOS logic circuits to values of V dd approaching or equal to the theoretical limit of approximately 4ηkT/Q e or approximately 100 mV at room temperature. In light of such, the present disclosure describes an apparatus for providing precise threshold matching among several sub-threshold logic circuits.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide an apparatus for predictably varying the I off ratios between N-channel and P-channel transistors for logic circuits that may accrue benefits from such condition. It is another object of the present invention to provide an apparatus for distributing the required N-well and substrate biases without using any explicit wiring or any conventional interconnect layers.

In accordance with a preferred embodiment of the present invention, an integrated circuit device includes multiple transistors and a global body bias circuit. The global body bias circuit includes a first transistor and second transistors connected in series between a power supply and a second power supply or ground. The gate and source of the first transistor are connected to the first power supply. The gate and source of the second transistor are connected to the second power supply. The drains and bodies of the first and second transistors are connected together to form an output connected to the bodies of the other transistors within the integrated circuit device.

All objects, features, and advantages of the present invention will become apparent in the following detailed written description.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention itself, as well as a preferred mode of use, further objects, and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:

FIG. 1 a is a schematic diagram of a global body bias circuit having one output, in accordance with a preferred embodiment of the present invention;

FIG. 1 b is a schematic diagram of a global body bias circuit having one output, in accordance with an alternative embodiment of the present invention;

FIG. 2 a is a pictorial illustration of the global body bias circuit from FIG. 1 a implemented on a substrate, in accordance with a preferred embodiment of the present invention;

FIG. 2 b is a pictorial illustration of various logic circuits that receive the global body bias circuit from FIG. 1 a implemented on a substrate, in accordance with a preferred embodiment of the present invention;

FIG. 3 is an implementation example of the global body bias circuit from FIG. 1 ;

FIG. 4 is a schematic diagram of a global body bias circuit having two outputs, in accordance with a preferred embodiment of the present invention;

FIGS. 4 a - 4 b are schematic diagrams of the global body bias circuit from FIG. 4 having additional input controls; and

FIG. 5 is an implementation example of the global body bias circuit from FIG. 4 .

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

In accordance with a preferred embodiment of the present invention, a global body bias circuit is utilized to match the I off of N-channel and P-channel transistors with each other within a logic circuit by adjusting the bias of a global N-well and a substrate (or a global P-well). I off is the amount of current a transistor draws from its drain when its gate is tied to its source.

Referring now to the drawings and in particular to FIG. 1 a , there is depicted a schematic diagram of a global body bias circuit having one output, in accordance with a preferred embodiment of the present invention. As shown, a global body bias circuit 10 includes a P-channel transistor 11 and an N-channel transistor 12 connected in series. The gate and source of P-channel transistor 11 are connected to a power supply V dd that provides a voltage ranging between 0.2 V-0.3 V. The gate and source of N-channel transistor 12 are connected to ground (or to a power supply V ss ). The bodies and the drains of P-channel transistor 11 and N-channel transistor 12 are connected together to form an output 15 for providing a body bias to other transistors within an integrated circuit device, as will be further described in an example shown in FIG. 3 .

The widths of P-channel transistor 11 and N-channel transistor 12 can be in various ratios, but are preferred to be equal. Usually, to minimize power, the widths of transistors 11 and 12 are set to a minimum width allowable by the process technology in order to minimize capacitance. Since both P-channel transistor 11 and N-channel transistor 12 are gated off and the drain currents must be equal, the output voltage at output 15 can find a body bias needed to provide an equal amount of I off to transistors in other logic circuits.

In a process where source/drain junction leakage to wells of transistors can sometimes be higher than the amount of I off , it may be necessary to match on subthreshold voltage on currents (i.e., I DS at V GS =V dd −V ss ) instead, which will increase the standby leakage of the global well voltage generators, but not for the logic circuits. Such is done by connecting the gate of N-channel transistor 12 from FIG. 1 to V dd instead of V ss , and by connecting the gate of P-channel transistor 11 from FIG. 1 to V ss instead of V dd . The result is shown in FIG. 1 b.

Referring now to FIG. 1 b , there is depicted a schematic diagram of a global body bias circuit having one output, in accordance with an alternative embodiment of the present invention. As shown, a global body bias circuit 20 includes a P-channel transistor 21 and an N-channel transistor 22 connected in series. The source of P-channel transistor 21 and the gate of N-channel transistor 22 are connected to a power supply V dd that provides a voltage ranging between 0.2 V-0.3 V. The source of N-channel transistor 22 and the gate of P-channel transistor 21 are connected to ground (or to a power supply V ss ). The bodies and the drains of P-channel transistor 21 and N-channel transistor 22 are connected together to form an output 25 for providing a body bias to other transistors within an integrated circuit device.

To minimize the generator standby current, it is possible to use a voltage divider network and to tie the well voltage generator transistor gates to intermediate voltages that maintain device currents above junction leakage levels but below the maximum subthreshold voltage I on . I on is the amount of current a transistor will draw from its drain when its gate is driven at full voltage.

With reference now to FIG. 2 a , there is depicted a pictorial illustration of global body bias circuit 10 implemented on a P-type substrate, in accordance with a preferred embodiment of the present invention. As shown, the body of P-channel transistor 11 , which is an N-well, is connected to the body of N-channel transistor 12 , which is the P-type substrate, via a silicide layer 14 to form output 15 . Instead of using contacts, the connections from silicide layer 14 to the N-well and the P-substrate are preferably made by an N + diffusion and a P + diffusion, respectively. Such method of body connections is particularly attractive because P-channel transistor 11 and N-channel transistor 12 can all be tied locally to the P-substrate with butted junctions.

Similarly, all logic circuits that receive a body bias from a global body bias circuit, such as global body bias circuit 10 from FIG. 1 a may use a structure similar to the one shown in FIG. 2 a . With reference now to FIG. 2 b , there is depicted a pictorial illustration of various logic circuits that receive a global body bias circuit implemented on a substrate, in accordance with a preferred embodiment of the present invention. As shown, connections from a silicide layer 24 to the N-well and the P-substrate are preferably made by an N + diffusion and a P + diffusion, respectively. By taking advantage of a common substrate connection available to the entire integrated circuit as shown in FIGS. 2 a and 2 b , the need to distribute a well bias within a level of interconnect, or wiring is eliminated. As a result, a denser and cheaper integrated circuit can be obtained.

Referring now to FIG. 3 , there is illustrated an implementation example of global body bias circuit 10 from FIG. 1 , in accordance with a preferred embodiment of the present invention. In this example, a two-input NAND gate 30 is a circuit that needs to be biased. As shown, two-input NAND gate 30 includes two P-channel transistors 31 - 32 and two N-channel transistors 33 - 34 connected in a manner that is well-known in the art. In order to provide body bias to NAND gate 30 , output 15 of global body bias circuit 10 from FIG. 1 is connected to the bodies of transistors 31 - 34 .

In order to provide more flexibility in setting transistors to a higher amount of I off than is capable by body bias circuit 10 from FIG. 1 , a global body bias circuit having two outputs is needed. With reference now to FIG. 4 , there is depicted a schematic diagram of a global body bias circuit having two outputs, in accordance with a preferred embodiment of the present invention. As shown, a global body bias circuit 40 includes P-channel transistors 41 - 43 and N-channel transistors 44 - 46 . Each gate and source of P-channel transistors 41 - 43 are connected to a power supply V dd that provides a voltage ranging between 0.2 V-0.3 V. Each gate and source of N-channel transistors 44 - 46 are connected to ground (or a power supply V ss ). The bodies and the drains of transistors 41 and 44 are connected to the bodies of transistors 43 and 45 . In addition, the body and the drain of transistor 42 are connected together to form an output 47 for providing a body bias to other P-channel transistors within an integrated circuit device. Similarly, the body and the drain of transistor 46 are connected together to form an output 48 for providing a body bias to other N-channel transistors within the same integrated circuit device, as will be further described in an example shown in FIG. 5 .

Global body bias circuit 40 allows the bodies of P-channel transistors and N-channel transistors within a logic circuit to be biased independently. Global body bias circuit 40 also allows the I off -N/I off -P to be programmed to a set ratio such as m/n, and I off -N is the I off of N-channel transistors, and I off -P is the I off of P-channel transistors. Thus, I off -N/I off -P can be increased by choosing m and n as large as they are desired. The arrangement of global body bias circuit 40 allows a higher performance circuit to be programmed at the expense of higher standby power when appropriate. With global body bias circuit 40 , isolate P-wells as well as N-wells are required. The required P-wells and N-wells may be provided by using either silicon-on-insulator (SOI) technology with body contacts or triple well technology.

Since global body bias circuit 40 requires explicit wiring to at least N-wells (because N-wells and P-wells are independent from each other), global body bias circuit 40 is simple enough (and hence small enough) to be scattered liberally throughout a product design, which may lessen the wiring penalty for the well bias. Furthermore, different circuit blocks may now have their drive current locally enhanced or depressed to tune performance as needed to keep in time with other circuit blocks.

Variations of global body bias circuit 40 are separately illustrated in FIGS. 4 a and 4 b . A global body bias circuit 40 a in FIG. 4 a allows the amount of I off to be continuously varied with R adj while I off -N and I off -P are kept at a fixed ratio of n/m. Thus, if R adj is replaced by a transistor, the performance and standby power of global body bias circuit 40 a can be modulated “on the fly.” Global body bias circuit 40 a sets N-channel transistors at $$ I off ⁢ N = n ⁢   ⁢ I off_x ⁢ ⅇ V dd ⁢ R ( 2 ⁢ R + R adj ) ⁢ Se

and P-channel transistors at $$ I off ⁢ P = m ⁢   ⁢ I off_x ⁢ ⅇ V dd ⁢ R ( 2 ⁢ R + R adj ) ⁢ Se

where Se=ηkT/Q e and I off — x is the drain current of an N-channel transistor x.

A global body bias circuit 40 b in FIG. 4 b has an enable body cut-off of subthreshold leakage during inactive periods. Global body bias circuit 40 b sets N-channel transistors at $$ I off ⁢ N = n ⁢   ⁢ I off_y ⁢ ⅇ V dd ⁢ R ( 2 ⁢ R + R adj ) ⁢ Se

and P-channel transistors at $$ I off ⁢ P = m ⁢   ⁢ I off_y ⁢ ⅇ V dd ⁢ R ( 2 ⁢ R + R adj ) ⁢ Se

where Se=ηkT/Q e and I off — y is the drain current of an N-channel transistor y and R n and R p are the effective source-to-drain resistances of N-channel T n and P-channel transistor T p , respectively, and R m is the effective source-to-drain resistance of N-channel transistor T m , in FIG. 4 b.

Referring now to FIG. 5 , there is illustrated an implementation example of global body bias circuit 40 from FIG. 4 , in accordance with a preferred embodiment of the present invention. In this example, a two-input NAND gate 50 is a circuit that needs to be biased. As shown, two-input NAND gate 50 includes two P-channel transistors 51 - 52 and two N-channel transistors 53 - 54 connected in a manner that is well-known in the art. In order to provide body bias to NAND gate 50 , output 47 of global body bias circuit 40 from FIG. 4 is connected to the bodies of P-channel transistors 51 - 52 , while output 48 of global body bias circuit 40 is connected to the bodies of N-channel transistors 53 - 54 .

As has been described, the present invention provides an apparatus for biasing ultra-low voltage logic circuits within an integrated circuit.

While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.

Claims

1. An integrated circuit device comprising:a plurality of transistors; and a global body bias circuit having an output connected to the bodies of said plurality of transistors, wherein said global body bias circuit includes a first and second transistors connected in series between a first power supply and a second power supply, wherein a gate and a source of said first transistor are connected to said first power supply, wherein a gate and a source of said second transistor are connected to said second power supply, wherein drains and bodies of said first and second transistors are connected together to form said output.

2. The integrated circuit device of claim 1, wherein said first transistor is a P-channel transistor and said second transistor is an N-channel transistor.

3. The integrated circuit device of claim 1, wherein said first power supply provides voltages in the range of approximately 0.2 V to 0.3 V.

4. The integrated circuit device of claim 1, wherein said second power supply provides 0 V.

5. The integrated circuit device of claim 1, wherein widths of said first and second transistors are identical.

6. The integrated circuit device of claim 1, wherein said drains of said first and second transistors are connected together via a silicide layer.

7. An integrated circuit device comprising:a plurality of transistors; and a global body bias circuit having a first output and a second output, wherein each of said first output and said second output is connected to a corresponding one of said plurality of transistors, wherein said global body bias circuit includes a first transistor and second transistors connected in series between a first power supply and a second power supply, wherein a gate and a source of said first transistor are connected to said first power supply, wherein a gate and a source of said second transistor are connected to said second power supply, wherein drains and bodies of said first and second transistors are connected together for biasing bodies of a third transistor and a fourth transistor of said global body bias circuit, wherein gates of said third and said fourth transistors are connected to said first power supply and said second power supply, respectively.

8. The integrated circuit device of claim 7, wherein said first transistor is a P-channel transistor and said second transistor is an N-channel transistor.

9. The integrated circuit device of claim 7, wherein said third transistor is a P-channel transistor and said fourth transistor is an N-channel transistor.

10. The integrated circuit device of claim 7, wherein said third transistor is of a second width.

11. The integrated circuit device of claim 7, wherein said power supply provides voltages in the range of approximately 0.2 V to 0.3 V.

12. The integrated circuit device of claim 7, wherein said second power supply provides 0 V.

13. The integrated circuit device of claim 7, wherein widths of said first and second transistors are identical.

14. The integrated circuit device of claim 7, wherein said drains of said first and second transistors are connected together via a silicide layer.