BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates an apparatus for charging a battery by using a programmable power adapter.
2. Description of the Related Art
A traditional approach has a programmable DC/DC converter (such as a buck converter or a buck/boost converter) equipped close to a battery for charging the battery. The input of this programmable DC/DC converter is coupled to the output of a power adapter with a constant current and/or constant voltage. The drawback of the traditional approach is low efficiency. The buck converter or the buck/boost converter will cause further power loss.
BRIEF SUMMARY OF THE INVENTION
The present invention is provided to eliminate the need of a DC/DC converter and improve the efficiency for battery charge.
An exemplary embodiment of an apparatus for charging a battery is provided. The apparatus comprises a power adaptor and a controller. The power adaptor has a communication interface coupled to a cable of the power adapter for receiving command-data. The power adaptor generates a DC voltage and a DC current in accordance with the command-data. The controller is coupled to the battery for detecting a battery voltage of the battery. The controller generates the command-data in accordance with the battery voltage. The DC voltage and the DC current generated by the power adaptor are coupled to the cable, and the DC voltage and the DC current are programmable in accordance with the command-data. The command-data generated by the controller is coupled the cable through a communication circuit of the controller.
A detailed description is given in the following embodiments with reference to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
FIG. 1 shows an exemplary embodiment of a charging apparatus;.
FIG. 2 shows an exemplary embodiment of a controller of the charging apparatus in FIG. 1;
FIG. 3 shows an exemplary embodiment of a control circuit of the charging apparatus in FIG. 1;
FIG. 4 shows an exemplary embodiment of a programmable power supply circuit of the charging apparatus in FIG. 1;
FIG. 5 shows an exemplary embodiment of a switching controller of the programmable power supply circuit in FIG. 4;
FIG. 6 shows an exemplary embodiment of a switching control circuit of the programmable power supply circuit in FIG. 4; and
FIG. 7 shows an exemplary embodiment of a feedback circuit of the switching control circuit in FIG. 6.
DETAILED DESCRIPTION OF THE INVENTION
The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
FIG. 1 shows a communication interface CMA coupled to a cable 40 through a connector 41 for receiving command-data Dc and generating an output voltage VO and an output current IO in accordance with the command-data Dc. The cable 40 is the output cable of a power adapter 10. The output voltage VO and the output current IO generated by the power adaptor 10 are delivered to the cable 40. A controller (CNTR_B) 70 is coupled to a battery 65 to detect a battery-voltage VB of the battery 65 for generating the command-data Dc in accordance with the battery-voltage VB. An terminal of a switch 60 is coupled to the cable 40 for receiving the output voltage VO and the output current IO through a connector 42. Another terminal of the switch 60 is coupled to the battery 65 for charging the battery 65. The output voltage VO and the output current IO are programmable in accordance with the command-data Dc. The command-data Dc generated by the controller 70 is coupled to the cable 40 through a communication interface CMB of the controller 70. The controller 70 is coupled the connector 42 to detect a connector-voltage VA. The controller 70 generates a control signal SX in response to the connector-voltage VA. The control signal SX is coupled to control the on/off state of the switch 60. The switch 60 will be turned off if the voltage drop of the cable 40 and the connector 42 is high. The controller 70 further has a communication port (COMM) 95 coupled to a host CPU (not shown), such as a CPU of a mobile-phone or a CPU of a notebook/PC, etc.
The power adapter 10 comprises an input terminal coupled to an AC power source (line voltage input) VAC for generating a DC voltage of the output voltage VO and a DC current of the output current IO. The power adapter 10 further comprises a programmable power supply circuit (AC/DC) 100 for generating the output voltage VO and the output current IO in accordance with the control of a control circuit (CNTR_A) 20. The control circuit 20 is coupled to the cable 40 via the communication interface CMA for receiving and sending the command-data Dc. The control circuit 20 generates a data-bus signal NA coupled to control the programmable power supply circuit 100. One example for the approach of the communication interface CMA and CMB can be found in a prior art of U.S. Pat. No. 8,154,153 titled “Method and apparatus for providing a communication channel through an output cable of a power supply”.
FIG. 2 shows an exemplary embodiment of the controller 70 in accordance with the present invention. The controller 70 includes an analog-to-digital converter (ADC) 80 coupled to the battery 65 (shown in FIG. 1) through a multiplexer (MUX) 87, resistors 83 and 84, and a switch 85 for detecting the battery-voltage VB. The analog-to-digital converter 80 is further coupled to the connector 42 (shown in FIG. 1) via the multiplexer 87 and resistors 81 and 82 for detecting the connector-voltage VA. A microcontroller (MCU) 75 comprises a memory 76. The memory 76 comprises a program memory and a data memory. The microcontroller 75 generates a control signal SY coupled to control the on/off state of the switch 85. The microcontroller 75 generates the control signal SX coupled to control the on/off state of the switch 60. The microcontroller 75 further generates a data-bus signal NB coupled to control the multiplexer 87, reads the data from the analog-to-digital converter 80, and reads/writes the command-data Dc through a communication circuit 90 and the communication interface CMB.
FIG. 3 shows an exemplary embodiment of the control circuit 20 in accordance with the present invention. The control circuit 20 comprises a microcontroller (MCU) 25. The microcontroller 25 comprises a memory 26, and the memory 26 comprises a program memory and a data memory. The microcontroller 25 generates the data-bus signal NA. The data-bus signal NA is coupled to read/write the command-data Dc through a communication circuit 30 and the communication interface CMA.
FIG. 4 shows an exemplary embodiment of the programmable power supply circuit 100 in accordance with the present invention. A switching controller (PWM) 180 generates a switching signal SW coupled to switch a transformer 110 through a transistor 120 for generating the output voltage VO and the output current IO in accordance with a feedback signal SFB. A switching control circuit 200 generates a feedback signal FB in response to the output voltage VO (such as the DC voltage of the output voltage VO) and a programmable voltage reference VRV (shown in FIG. 6). The programmable voltage reference VRV is determined by the command-data Dc. Furthermore, the switching control circuit 200 generates the feedback signal FB in response to the output current IO (such as the DC voltage of the output current IO) and a programmable current reference VRI. The programmable current reference VRI is determined by the command-data Dc.
A current-sense device, such as a resistor 135, generates a current-sense signal VCS in accordance with the output current IO. In other words, the power adaptor 10 can detect the output current IO (such as the DC current of the output current IO) through the resistor 135 to generate the current-sense signal VCS. The switching control circuit 200 is coupled to detect the output voltage VO and the current-sense signal VCS for developing the feedback loop and generate the feedback signal FB. The switching control circuit 200 generates the feedback signal FB coupled to the switching controller 180 through an opto-coupler 150 for generating the feedback signal SFB and regulating the output voltage VO and the output current IO. A capacitor 170 is coupled to receive a voltage-feedback signal COMV for the voltage-loop compensation. A capacitor 175 is coupled to receive a current-feedback signal COMI to compensate the current-loop for the regulation of the output current IO. A resistor 151 is utilized to bias an operating current of the opto-coupler 150.
The opto-couplers 150 generates the feedback signal SFB in accordance with the feedback signal FB. The switching controller 180 generates the switching signal SW for switching the primary-side winding of the transformer 110 and generating the output voltage VO and the output current IO at the secondary-side of the transformer 110 through a rectifier 130 and output capacitors 140 and 145. A resistor 125 is coupled to sense the switching current of the transformer 110 for generating a current signal CS coupled to the switching controller 180.
FIG. 5 shows an exemplary embodiment of the switching controller 180. The switching controller 180 comprises an oscillator (OSC) 181 for generating a clock signal PLS. The clock signal PLS is coupled to enable a flip-flop 185 and the switching signal SW. The feedback signal SFB is coupled to compare with the current signal CS through a buffer 190, resistors 192 and 193 and a comparator 195. The buffer 190 and the resistors 192 and 193 generate a level-shifted feedback signal SFB1 in accordance with the feedback signal SFB. An input of the comparator 195 receives the current signal CS, and another input thereof receives the level-shifted feedback signal SFB1. For the pulse width modulation (PWM), the comparator 195 is coupled to reset the flip-flop 185 and disable the switching signal SW when the current signal CS is higher than the level-shifted feedback signal SFB1.
FIG. 6 shows an exemplary embodiment of the switching control circuit 200 in accordance with the present invention. The data-bus signal NA is coupled to control a multiplexer (MUX) 296, an analog-to-digital converter (ADC) 295, and digital-to-analog converters (DACs) 291 and 292. In detailed, the digital-to-analog converters 291 and 292 are controlled by the microcontroller 25 of the control circuit 20 (shown in FIG. 3) through receiving the data-bus signal NA and registers (REG) 281 and 282. The current-sense signal VCS is coupled to generate a current signal VI through a feedback circuit 210. The current signal VI is coupled to the multiplexer 296. Resistors 286 and 287 develop a voltage divider for generating a feedback signal VFB in accordance with the output voltage VO. The feedback signal VFB is also coupled to the multiplexer 296. The output of the multiplexer 296 is coupled the analog-to-digital converter 295. Therefore, via the data-bus signal NA, the microcontroller 25 can read and/or detect the information of the output current IO and the output voltage VO (such as the DC current of the output current IO and the DC voltage of the output voltage VOx′) through the analog-to-digital converter 295. The microcontroller 25 controls the output of the digital-to-analog converters 291 and 292. The digital-to-analog converter 291 generates the programmable voltage reference VRV for controlling the output voltage VO. The digital-to-analog converter 292 generates the programmable current reference VRI for controlling the output current IO. The registers 281 and 282 will be reset to an initial value in response to the power-on of the switching control circuit 200. For example, the initial value of the register 281 will produce a minimum value of the programmable voltage reference VRV that generates a 5V output voltage VO. The initial value of the register 282 will produce a minimum value of the programmable current reference VRI that induces the generation of the output current IO with 0.5 A. The feedback circuit 210 generates the voltage-feedback signal COMV, the current-feedback signal COMI, and the feedback signal FB in response to the programmable voltage reference VRV, the programmable current reference VRI, the feedback signal VFB, and the current-sense signal VCS.
FIG. 7 shows an exemplary embodiment of the feedback circuit 210 in accordance with the present invention. The feedback circuit 210 comprises resistors 211 and 212 and a capacitor 215 coupled to receive the current-sense signal VCS and filter the noise in the current-sense signal VCS. The capacitor 215 is coupled to an operational amplifier 220. Resistors 218 and 219 determine the gain of the operational amplifier 220. The operational amplifier 220 generates the current signal VI by amplifying the current-sense signal VCS. An error amplifier 230 receives the current signal VI and the programmable current reference VRI and generates the current-feedback signal COMI in accordance with the current signal VI and the programmable current reference VRI. The current-feedback signal COMI is coupled to the capacitor 175, shown in FIG. 4, for the current-loop compensation. An error amplifier 240 receives the feedback signal VFB and the programmable voltage reference VRV and generates the voltage-feedback signal COMV in accordance with the feedback signal VFB and the programmable voltage reference VRV. The voltage-feedback signal COMV is coupled to the capacitor 170, shown in FIG. 4, for the voltage-loop compensation. The voltage-feedback signal COMV is further coupled to a buffer (OD) 235 to generate the feedback signal FB. The current-feedback signal COMI is further coupled to a buffer (OD) 245. The output of the buffer 245 is coupled to the output of the buffer 235. The buffer 235 and the buffer 245 have the open-drain output, thus they can be wire-OR connected.
According to the description above, the present invention provides a controller to replace traditional buck converter or a buck/boost converter which takes cause further power loss. The invention achieves higher efficiency and takes less power loss.
While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Patent Application
20140239882
